CY7C1041GE-10ZSXI

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Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.com CY7C1041G CY7C1041GE 4-Mbit (256K words × 16-bit) Static RAM with Error-Correcting Code (ECC) 4-Mbit (256K words × 16-bit) Static RAM with Error-Correcting Code (ECC) Features ■ ■ ■ Data writes are performed by asserting the Chip Enable (CE) and Write Enable (WE) inputs LOW, while providing the data on I/O0 through I/O15 and address on A0 through A17 pins. The Byte High Enable (BHE) and Byte Low Enable (BLE) inputs control write operations to the upper and lower bytes of the specified memory location. BHE controls I/O8 through I/O15 and BLE controls I/O0 through I/O7. High speed ❐ tAA = 10 ns/15 ns Embedded ECC for single-bit error correction[1, 2] Low active and standby currents ❐ Active current: ICC = 38 mA typical ❐ Standby current: ISB2 = 6 mA typical ■ Operating voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V, and 4.5 V to 5.5 V ■ 1.0-V data retention ■ TTL-compatible inputs and outputs Data reads are performed by asserting the Chip Enable (CE) and Output Enable (OE) inputs LOW and providing the required address on the address lines. Read data is accessible on the I/O lines (I/O0 through I/O15). Byte accesses can be performed by asserting the required byte enable signal (BHE or BLE) to read either the upper byte or the lower byte of data from the specified address location. ■ Error indication (ERR) pin to indicate 1-bit error detection and correction All I/Os (I/O0 through I/O15) are placed in a high-impedance state during the following events: ■ Pb-free 44-pin SOJ, 44-pin TSOP II, and 48-ball VFBGA packages ■ The device is deselected (CE HIGH) ■ The control signals (OE, BLE, BHE) are de-asserted Functional Description CY7C1041G and CY7C1041GE are high-performance CMOS fast static RAM devices with embedded ECC. Both devices are offered in single chip-enable option and in multiple pin configurations. The CY7C1041GE device includes an ERR pin that signals an error-detection and correction event during a read cycle. On the CY7C1041GE devices, the detection and correction of a single-bit error in the accessed location is indicated by the assertion of the ERR output (ERR = HIGH)[1]. See the Truth Table on page 14 for a complete description of read and write modes. The logic block diagram is on page 2. Product Portfolio Product [3] Features and Options (see Pin Configurations on page 4) CY7C1041G(E)18 Single Chip Enable CY7C1041G(E)30 CY7C1041G(E) Optional ERR pins Power Dissipation Speed Operating ICC, (mA) (ns) Standby, ISB2 (mA) f = fmax 10/15 [4] [4] Typ Max Typ Max Range VCC Range (V) Industrial 1.65 V–2.2 V 15 – 40 2.2 V–3.6 V 10 38 45 4.5 V–5.5 V 10 38 45 6 8 Notes 1. This device does not support automatic write-back on error detection. 2. SER FIT Rate 2001 V Latch-up current .................................................... > 140 mA Operating Range Grade Industrial Ambient Temperature –40 C to +85 C VCC 1.65 V to 2.2 V, 2.2 V to 3.6 V, 4.5 V to 5.5 V DC Electrical Characteristics Over the operating range of –40 C to 85 C Parameter VOH VOL VIH VIL Description Output HIGH voltage Output LOW voltage Input HIGH voltage Input LOW voltage Test Conditions 1.65 V to 2.2 V VCC = Min, IOH = –0.1 mA 10 ns/15 ns Min Typ [11] Max 1.4 – – V 2.2 V to 2.7 V VCC = Min, IOH = –1.0 mA 2 – – 2.7 V to 3.0 V VCC = Min, IOH = –4.0 mA 2.2 – – 3.0 V to 3.6 V VCC = Min, IOH = –4.0 mA 2.4 – – 4.5 V to 5.5 V VCC = Min, IOH = –4.0 mA 2.4 – – 4.5 V to 5.5 V VCC = Min, IOH = –0.1 mA VCC – 0.5 [12] – – 1.65 V to 2.2 V VCC = Min, IOL = 0.1 mA – – 0.2 2.2 V to 2.7 V VCC = Min, IOL = 2 mA – – 0.4 2.7 V to 3.6 V VCC = Min, IOL = 8 mA – – 0.4 4.5 V to 5.5 V VCC = Min, IOL = 8 mA – – 0.4 1.4 – VCC + 0.2 [10] 1.65 V to 2.2 V – 2.2 V to 2.7 V – 2 – VCC + 0.3 [10] 2.7 V to 3.6 V – 2 – VCC + 0.3 [10] 4.5 V to 5.5 V – 2 1.65 V to 2.2 V – – VCC + 0.5 [10] –0.2 [10] – 0.4 [10] 2.2 V to 2.7 V – –0.3 – 0.6 2.7 V to 3.6 V – –0.3 [10] – 0.8 – [10] – 0.8 4.5 V to 5.5 V –0.5 Unit V V V IIX Input leakage current GND < VIN < VCC –1 – +1 A IOZ Output leakage current GND < VOUT < VCC, Output disabled –1 – +1 A ICC Operating supply current Max VCC, IOUT = 0 mA, f = 100 MHz CMOS levels f = 66.7 MHz – 38 45 mA – – 40 ISB1 Automatic CE power-down current – TTL inputs Max VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fMAX – – 15 mA ISB2 Automatic CE power-down current – CMOS inputs Max VCC, CE > VCC – 0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V, f = 0 – 6 8 mA Notes 10. VIL(min) = –2.0 V and VIH(max) = VCC + 2 V for pulse durations of less than 20 ns. 11. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = 1.8 V (for VCC range of 1.65 V – 2.2 V), VCC = 3 V (for VCC range of 2.2V – 3.6 V), and VCC = 5 V (for VCC range of 4.5 V – 5.5 V), TA = 25 °C. 12. This parameter is guaranteed by design and not tested. Document Number: 001-91368 Rev. *N Page 6 of 21 CY7C1041G CY7C1041GE Capacitance Parameter [13] Description CIN Input capacitance COUT I/O capacitance Test Conditions TA = 25 C, f = 1 MHz, VCC = VCC(typ) 48-ball VFBGA 44-pin SOJ 10 10 44-pin TSOP II Unit 10 pF 10 10 10 pF 48-ball VFBGA 44-pin SOJ 31.35 55.37 68.85 C/W 14.74 30.41 15.97 C/W Thermal Resistance Parameter [13] Description JA Thermal resistance (junction to ambient) JC Thermal resistance (junction to case) Test Conditions Still air, soldered on a 3 × 4.5 inch, four-layer printed circuit board 44-pin TSOP II Unit AC Test Loads and Waveforms Figure 7. AC Test Loads and Waveforms [14] High-Z Characteristics: VCC 50  Output VTH Z0 = 50  R1 Output 30 pF* * Including jig and scope (a) * Capacitive load consists of all components of the test environment  (b) All Input Pulses VHIGH GND R2 5 pF* 90% 90% 10% Rise Time: > 1 V/ns 10% Fall Time: > 1 V/ns (c) Parameters 1.8 V 3.0 V 5.0 V Unit R1 1667 317 317  R2 1538 351 351  VTH 0.9 1.5 1.5 V VHIGH 1.8 3 3 V Notes 13. Tested initially and after any design or process changes that may affect these parameters. 14. Full-device AC operation assumes a 100-µs ramp time from 0 to VCC(min) and a 100-µs wait time after VCC stabilization. Document Number: 001-91368 Rev. *N Page 7 of 21 CY7C1041G CY7C1041GE Data Retention Characteristics Over the operating range of –40 C to 85 C Parameter VDR Description Conditions Min Max Unit 1 – V – 8 mA 0 – ns VCC > 2.2 V 10 – ns VCC < 2.2 V 15 – ns VCC for data retention [15] ICCDR Data retention current tCDR[16] Chip deselect to data retention time tR[15, 16] Operation recovery time VCC = 1.2 V, CE > VCC – 0.2 V , VIN > VCC – 0.2 V, or VIN < 0.2 V Data Retention Waveform Figure 8. Data Retention Waveform [15] VCC VCC(min) DATA RETENTION MODE VDR = 1.0 V tCDR VCC(min) tR CE Notes 15. Full-device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC (min) > 100 s. 16. These parameters are guaranteed by design. Document Number: 001-91368 Rev. *N Page 8 of 21 CY7C1041G CY7C1041GE AC Switching Characteristics Over the operating range of –40 C to 85 C Parameter [17] Description 10 ns 15 ns Min Max Min Max Unit Read Cycle tRC Read cycle time 10 – 15 – ns tAA Address to data / ERR valid – 10 – 15 ns tOHA Data / ERR hold from address change 3 – 3 – ns tACE CE LOW to data / ERR valid – 10 – 15 ns tDOE OE LOW to data / ERR valid – 4.5 – 8 ns 0 – 0 – ns – 5 – 8 ns 3 – 3 – ns – 5 – 8 ns 0 – 0 – ns – 10 – 15 ns tLZOE tHZOE OE LOW to low impedance OE HIGH to HI-Z [18, 19] tLZCE CE LOW to low impedance tHZCE CE HIGH to HI-Z [18, 19] tPU [18] CE LOW to power-up [18] [19, 18] [19, 18] tPD CE HIGH to power-down tDBE Byte enable to data valid – 4.5 – 8 ns tLZBE Byte enable to low impedance [18] 0 – 0 – ns – 6 – 8 ns tHZBE Write Cycle Byte disable to HI-Z [19] [20, 21] tWC Write cycle time 10 – 15 – ns tSCE CE LOW to write end 7 – 12 – ns tAW Address setup to write end 7 – 12 – ns tHA Address hold from write end 0 – 0 – ns tSA Address setup to write start 0 – 0 – ns tPWE WE pulse width 7 – 12 – ns tSD Data setup to write end 5 – 8 – ns tHD Data hold from write end 0 – 0 – ns [18] tLZWE WE HIGH to low impedance 3 – 3 – ns tHZWE WE LOW to HI-Z [19] – 5 – 8 ns tBW Byte Enable to write end 7 – 12 – ns Notes 17. Test conditions assume a signal transition time (rise/fall) of 3 ns or less, timing reference levels of 1.5 V (for VCC > 3 V) and VCC/2 (for VCC < 3 V), and input pulse levels of 0 to 3 V (for VCC > 3 V) and 0 to VCC (for VCC < 3 V). Test conditions for the read cycle use output loading, as shown in part (a) of Figure 7 on page 7, unless specified otherwise 18. tHZOE, tHZCE, tHZWE, tHZBE, tLZOE, tLZCE, tLZWE, and tLZBE are specified with a load capacitance of 5 pF, as shown in part (b) of Figure 7 on page 7. Transition is measured 200 mV from steady state voltage. 19. These parameters are guaranteed by design and are not tested. 20. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL, and BHE or BLE = VIL. These signals must be LOW to initiate a write, and the HIGH transition of any of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates the write. 21. The minimum write cycle pulse width in Write Cycle No 2 (WE Controlled, OE LOW) should be equal to sum of tsdand tHZWE. Document Number: 001-91368 Rev. *N Page 9 of 21 CY7C1041G CY7C1041GE Switching Waveforms Figure 9. Read Cycle No. 1 of CY7C1041G (Address Transition Controlled) [22, 23] tRC ADDRESS tAA tOHA DATA I/O PREVIOUS DATAOUT VALID DATAOUT VALID Figure 10. Read Cycle No. 1 of CY7C1041GE (Address Transition Controlled) [22, 23] tRC ADDRESS tAA tOHA DATA I/O PREVIOUS DATAOUT VALID DATAOUT VALID tAA tOHA ERR PREVIOUS ERR VALID ERR VALID Notes 22. The device is continuously selected, OE = VIL, CE = VIL, BHE or BLE or both = VIL. 23. WE is HIGH for the read cycle. Document Number: 001-91368 Rev. *N Page 10 of 21 CY7C1041G CY7C1041GE Switching Waveforms (continued) Figure 11. Read Cycle No. 2 (OE Controlled) [24, 25] ADDRESS tRC CE tPD tHZCE tACE OE t HZOE tDOE tLZOE BHE/ BLE tDBE tLZBE DATA I/O HIGH IMPEDANCE t HZBE DATAOUT VALID HIGH IMPEDANCE tLZCE tPU VCC SUPPLY CURRENT ISB Notes 24. WE is HIGH for the read cycle. 25. Address valid prior to or coincident with CE LOW transition. Document Number: 001-91368 Rev. *N Page 11 of 21 CY7C1041G CY7C1041GE Switching Waveforms (continued) Figure 12. Write Cycle No. 1 (CE Controlled) [26, 27] tW C ADDRESS tS A tSC E CE tA W tPW tH A E W E tB W B H E/ BLE O E tHZOE tH D tS D D A T A I /O D A T AI N V A L ID Figure 13. Write Cycle No. 2 (WE Controlled, OE LOW) [26, 27, 28] tW C ADDRESS tSCE CE tB W BHE / BLE tS A tA W tH A tPW E WE t LZ W E t HZW E D A T A I /O tS D DATA tH D IN V A L ID Notes 26. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL, and BHE or BLE = VIL. These signals must be LOW to initiate a write, and the HIGH transition of any of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates the write. 27. Data I/O is in HI-Z state if CE = VIH, or OE = VIH, or BHE, and/or BLE = VIH. 28. The minimum write cycle pulse width should be equal to sum of tSD and tHZWE. Document Number: 001-91368 Rev. *N Page 12 of 21 CY7C1041G CY7C1041GE Switching Waveforms (continued) Figure 14. Write Cycle No. 3 (BLE or BHE Controlled) [29, 30] tWC ADDRESS t SCE CE tAW tSA tHA tBW BHE / BLE t PWE WE t HZWE tHD tSD t LZWE DATA IN VALID DATA I /O Figure 15. Write Cycle No. 4 (WE Controlled) [29, 30, 31] tWC ADDRESS tSCE CE1 CE2 tAW tHA tSA WE tPWE tBW BHE/BLE OE tHD tSD DATA I/O NOTE 32 DATA IN VALID tHZOE Notes 29. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL, and BHE or BLE = VIL. These signals must be LOW to initiate a write, and the HIGH transition of any of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates the write. 30. Data I/O is in HI-Z state if CE = VIH, or OE = VIH, or BHE, and/or BLE = VIH. 31. Data I/O is high impedance if OE = VIH. 32. During this period the I/Os are in output state. Do not apply input signals. Document Number: 001-91368 Rev. *N Page 13 of 21 CY7C1041G CY7C1041GE Truth Table CE OE WE BLE BHE H X[33] X[33] X[33] X[33] L L H L L L H L L L I/O0–I/O7 I/O8–I/O15 Mode Power HI-Z HI-Z Power down Standby (ISB) L Data out Data out Read all bits Active (ICC) L H Data out HI-Z Read lower bits only Active (ICC) H H L HI-Z Data out Read upper bits only Active (ICC) X L L L Data in Data in Write all bits Active (ICC) L X L L H Data in HI-Z Write lower bits only Active (ICC) L X L H L HI-Z Data in Write upper bits only Active (ICC) L H H X X HI-Z HI-Z Selected, outputs disabled Active (ICC) L X X H H HI-Z HI-Z Selected, outputs disabled Active (ICC) ERR Output – CY7C1041GE Output [34] 0 Mode Read operation, no single-bit error in the stored data. 1 Read operation, single-bit error detected and corrected. HI-Z Device deselected or outputs disabled or Write operation Notes 33. The input voltage levels on these pins should be either at VIH or VIL. 34. ERR is an Output pin.If not used, this pin should be left floating. Document Number: 001-91368 Rev. *N Page 14 of 21 CY7C1041G CY7C1041GE Ordering Information Speed (ns) 10 Voltage Range Ordering Code 2.2 V–3.6 V CY7C1041GE30-10ZSXI Package Type (all Pb-free) 51-85087 44-pin TSOP II, ERR output CY7C1041GE30-10ZSXIT 51-85087 44-pin TSOP II, ERR output, Tape and Reel CY7C1041G30-10ZSXI 51-85087 44-pin TSOP II CY7C1041G30-10ZSXIT 51-85087 44-pin TSOP II, Tape and Reel CY7C1041GE30-10BVXI 51-85150 48-ball VFBGA (6 × 8 × 1.0 mm), ERR output CY7C1041GE30-10BVXIT 51-85150 48-ball VFBGA (6 × 8 × 1.0 mm), ERR output, Tape and Reel CY7C1041G30-10BVXI 51-85150 48-ball VFBGA (6 × 8 × 1.0 mm) CY7C1041G30-10BVXIT 51-85150 48-ball VFBGA (6 × 8 × 1.0 mm), Tape and Reel CY7C1041G30-10BVJXI 51-85150 48-ball VFBGA (6 × 8 × 1.0 mm), JEDEC CY7C1041G30-10BVJXIT 51-85150 48-ball VFBGA (6 × 8 × 1.0 mm), JEDEC, Tape and Reel CY7C1041G30-10VXI 51-85082 44-pin SOJ (400 Mils) CY7C1041G30-10VXIT 51-85082 44-pin SOJ (400 Mils), Tape and Reel CY7C1041GE30-10VXI 51-85082 44-pin SOJ (400 Mils), ERR output CY7C1041GE30-10VXIT 51-85082 44-pin SOJ (400 Mils), ERR output, Tape and Reel 4.5 V–5.5 V CY7C1041G-10ZSXI 15 Package Diagram 51-85087 44-pin TSOP II, Tape and Reel CY7C1041GE-10ZSXI 51-85087 44-pin TSOP II, ERR output CY7C1041GE-10ZSXIT 51-85087 44-pin TSOP II, ERR output, Tape and Reel CY7C1041GE-10VXI 51-85082 44-pin SOJ (400 Mils), ERR output CY7C1041GE-10VXIT 51-85082 44-pin SOJ (400 Mils), ERR output, Tape and Reel CY7C1041G-10VXI 51-85082 44-pin SOJ (400 Mils) CY7C1041G-10VXIT 51-85082 44-pin SOJ (400 Mils), Tape and Reel 51-85087 44-pin TSOP II CY7C1041G18-15ZSXIT 51-85087 44-pin TSOP II, Tape and Reel CY7C1041G18-15VXI 51-85082 44-pin SOJ (400 Mils) CY7C1041G18-15VXIT 51-85082 44-pin SOJ (400 Mils), Tape and Reel CY7C1041G18-15BVXI 51-85150 48-ball VFBGA (6 × 8 × 1.0 mm) CY7C1041G18-15BVXT 51-85150 48-ball VFBGA (6 × 8 × 1.0 mm), Tape and Reel Document Number: 001-91368 Rev. *N Industrial 51-85087 44-pin TSOP II CY7C1041G-10ZSXIT 1.65 V–2.2 V CY7C1041G18-15ZSXI Operating Range Page 15 of 21 CY7C1041G CY7C1041GE Ordering Code Definitions CY 7 C 1 04 1 G E XX - XX XX X I X X = blank or T blank = Bulk; T = Tape and Reel Temperature Range: I = Industrial Pb-free Package Type: XX = ZS or BV or BVJ or V ZS = 44-pin TSOP II; BV = 48-ball VFBGA; BVJ = 48-ball VFBGA-JEDEC Compliant; V = 44-pin Molded SOJ Speed: XX = 10 ns or 15 ns Voltage Range: XX = 30 or blank or 18 30 = 2.2 V–3.6 V; blank = 4.5 V–5.5 V; 18 = 1.65 V–2.2 V E = ERR output Single bit error indication Revision Code “G”: Process Technology = 65 nm Data Width: 1 = × 16-bits Density: 04 = 4-Mbit Family Code: 1 = Fast Asynchronous SRAM family Technology Code: C = CMOS Marketing Code: 7 = SRAM Company ID: CY = Cypress Document Number: 001-91368 Rev. *N Page 16 of 21 CY7C1041G CY7C1041GE Package Diagrams Figure 16. 44-pin TSOP II (Z44) Package Outline, 51-85087 51-85087 *E Figure 17. 44-pin SOJ (400 Mils) Package Outline, 51-85082 51-85082 *E Document Number: 001-91368 Rev. *N Page 17 of 21 CY7C1041G CY7C1041GE Package Diagrams (continued) Figure 18. 48-ball VFBGA (6 × 8 × 1.0 mm) BV48/BZ48 Package Outline, 51-85150 51-85150 *H Document Number: 001-91368 Rev. *N Page 18 of 21 CY7C1041G CY7C1041GE Acronyms Acronym Document Conventions Description Units of Measure BHE byte high enable BLE byte low enable °C Degrees Celsius CE chip enable MHz megahertz CMOS complementary metal oxide semiconductor A microamperes I/O input/output s microseconds OE output enable mA milliamperes SRAM static random access memory mm millimeters TSOP thin small outline package ns nanoseconds TTL transistor-transistor logic  ohms VFBGA very fine-pitch ball grid array % percent WE write enable pF picofarads V volts W watts Document Number: 001-91368 Rev. *N Symbol Unit of Measure Page 19 of 21 CY7C1041G CY7C1041GE Document History Page Document Title: CY7C1041G/CY7C1041GE, 4-Mbit (256K words × 16-bit) Static RAM with Error-Correcting Code (ECC) Document Number: 001-91368 Rev. ECN No. Orig. of Change Submission Date *F 4867081 NILE 07/31/2015 Changed status from Preliminary to Final. *G 4876251 NILE 08/07/2015 Updated Ordering Information: Updated part numbers. *H 4968879 NILE 10/16/2015 Fixed typo in bookmarks. *I 5019226 VINI 11/18/2015 Updated Ordering Information: Updated part numbers. Description of Change *J 5122043 NILE 02/02/2016 Updated Truth Table. *K 5223335 NILE 08/30/2016 Updated DC Electrical Characteristics: Removed values of VOH parameter corresponding to “2.7 V to 3.6 V” range. Added values of VOH parameter corresponding to “2.7 V to 3.0 V” and “3.0 V to 3.6 V” ranges. Updated Note 10 (Replaced “2 ns” with “20 ns”). Updated Ordering Information: Updated part numbers. Updated to new template. *L 5655218 NILE 03/09/2017 Updated Logic Block Diagram – CY7C1041G (Updated diagram to change the devices from Dual Chip enabled to Single Chip enabled). Updated Logic Block Diagram – CY7C1041GE (Updated diagram to change the devices from Dual Chip enabled to Single Chip enabled). Updated to new template. *M 5731242 GNKK 05/09/2017 Updated logo and copyright. Completing Sunset Review. *N 6245720 NILE 07/13/2018 Updated Features: Added Note 2 and referred the same note in “Embedded ECC for single-bit error correction”. Updated to new template. Completing Sunset Review. Document Number: 001-91368 Rev. *N Page 20 of 21 CY7C1041G CY7C1041GE Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. 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Document Number: 001-91368 Rev. *N Revised July 13, 2018 Page 21 of 21