CY7C1041GN
4-Mbit (256K words × 16 bit) Static RAM
4-Mbit (256K words × 16 bit) Static RAM
Features
Data writes are performed by asserting the Chip Enable (CE) and
Write Enable (WE) inputs LOW, while providing the data on I/O0
through I/O15 and address on A0 through A17 pins. The Byte High
Enable (BHE) and Byte Low Enable (BLE) inputs control write
operations to the upper and lower bytes of the specified memory
location. BHE controls I/O8 through I/O15 and BLE controls I/O0
through I/O7.
■
High speed
❐ tAA = 10 ns / 15 ns
■
Low active and standby currents
❐ Active current: ICC = 38-mA typical
❐ Standby current: ISB2 = 6-mA typical
■
Operating voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V, and
4.5 V to 5.5 V
■
1.0-V data retention
■
TTL-compatible inputs and outputs
■
Pb-free 44-pin SOJ, 44-pin TSOP II, and 48-ball VFBGA
packages
Functional Description
CY7C1041GN is high-performance CMOS fast static RAM
Organized as 256K words by 16-bits.
Data reads are performed by asserting the Chip Enable (CE) and
Output Enable (OE) inputs LOW and providing the required
address on the address lines. Read data is accessible on the I/O
lines (I/O0 through I/O15). Byte accesses can be performed by
asserting the required byte enable signal (BHE or BLE) to read
either the upper byte or the lower byte of data from the specified
address location.
All I/Os (I/O0 through I/O15) are placed in a high-impedance state
during the following events:
■
The device is deselected (CE HIGH)
■
The control signals (OE, BLE, BHE) are de-asserted
The logic block diagram is on page 2.
Product Portfolio
Product
Range
VCC Range (V)
Speed
(ns)
10/15
CY7C1041GN18
CY7C1041GN30
1.65 V–2.2 V
Industrial
CY7C1041GN
15
Power Dissipation
Operating ICC, (mA)
f = fmax
Typ[1]
Max
–
40
2.2 V–3.6 V
10
38
45
4.5 V–5.5 V
10
38
45
Standby, ISB2 (mA)
Typ[1]
Max
6
8
Notes
1. Typical values are included only for reference and are not guaranteed or tested. Typical values are measured at VCC = 1.8 V (for a VCC range of 1.65 V–2.2 V),
VCC = 3 V (for a VCC range of 2.2 V–3.6 V), and VCC = 5 V (for a VCC range of 4.5 V–5.5 V), TA = 25 °C.
Cypress Semiconductor Corporation
Document Number: 001-95413 Rev. *D
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised September 9, 2016
CY7C1041GN
Logic Block Diagram – CY7C1041GN
MEMORY
ARRAY
SENSE
AMPLIFIERS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
ROW DECODER
INPUT BUFFER
I/O 0‐I/O 7
I/O 8‐I/O 15
A10
A11
A12
A13
A14
A15
A16
A17
COLUMN DECODER
BHE
WE
OE
CE1
BLE
Document Number: 001-95413 Rev. *D
Page 2 of 18
CY7C1041GN
Contents
Pin Configurations ........................................................... 4
Maximum Ratings ............................................................. 5
Operating Range ............................................................... 5
DC Electrical Characteristics .......................................... 5
Capacitance ...................................................................... 6
Thermal Resistance .......................................................... 6
AC Test Loads and Waveforms ....................................... 6
Data Retention Characteristics ....................................... 7
Data Retention Waveform ................................................ 7
AC Switching Characteristics ......................................... 8
Switching Waveforms ...................................................... 9
Truth Table ...................................................................... 12
Document Number: 001-95413 Rev. *D
Ordering Information ...................................................... 13
Ordering Code Definitions ......................................... 13
Package Diagrams .......................................................... 14
Acronyms ........................................................................ 16
Document Conventions ................................................. 16
Units of Measure ....................................................... 16
Document History Page ................................................. 17
Sales, Solutions, and Legal Information ...................... 18
Worldwide Sales and Design Support ....................... 18
Products .................................................................... 18
PSoC® Solutions ...................................................... 18
Cypress Developer Community ................................. 18
Technical Support ..................................................... 18
Page 3 of 18
CY7C1041GN
Pin Configurations
Figure 1. 48-ball VFBGA (6 × 8 × 1.0 mm) pinout,
Package/Grade ID: BVXI[2, 3]
1
2
BLE
OE
I/O 0
3
4
5
6
A0
A1
A2
NC
BHE
A3
A4
CE
I/O 1
I/O2
A5
A6
VSS
I/O3
A17
VCC
I/O4
I/O 6
Figure 2. 48-ball VFBGA (6 × 8 × 1.0 mm) pinout,
Package/Grade ID: BVJXI[2]
1
2
A
BLE
OE
I/O8
B
I/O8
I/O10
I/O9
C
A7
I/O11
VCC
NC
A 16
I/O12
I/O5
A14
A 15
I/O 7
NC
A12
NC
A8
A9
3
4
5
6
A0
A1
A2
NC
A
BHE
A3
A4
CE
I/O0
B
I/O9
I/O10
A5
A6
I/O1
I/O2
C
D
VSS
I/O11
A17
A7
I/O3
VCC
D
VSS
E
VCC
I/O12
NC
A16
I/O4
VSS
E
I/O13
I/O14
F
I/O14
I/O13
A14
A15
I/O5
I/O6
F
A 13
WE
I/O15
G
I/O15
NC
A12
A13
WE
I/O7
G
A 10
A 11
NC
H
NC
A8
A9
A10
A11
NC
H
Figure 3. 44-pin TSOP II / 44-pin SOJ pinout[2]
A0
A1
A2
A3
A4
/CE
I/O0
I/O1
I/O2
I/O3
VCC
VSS
I/O4
I/O5
I/O6
I/O7
/WE
A5
A6
A7
A8
A9
1
44
2
43
3
42
4
41
5
40
6
39
7
38
8
37
9
44- pin TSOP II36
10
35
11
34
12
33
13
32
14
31
15
30
16
29
17
28
18
27
19
26
20
25
21
24
22
23
A17
A16
A15
/OE
/ BHE
/ BLE
I/O15
I/O14
I/O13
I/O12
VSS
VCC
I/O11
I/O10
I/O9
I/O8
NC
A14
A13
A12
A11
A10
Notes
2. NC pins are not connected internally to the die.
3. Package type BVJXI is JEDEC compliant compared to package type BVXI. The difference between the two is that the higher and lower byte I/Os (I/O[7:0] and I/O[15:8]
balls are swapped.
Document Number: 001-95413 Rev. *D
Page 4 of 18
CY7C1041GN
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage temperature ................................ –65 C to +150 C
Ambient temperature
with power applied ................................... –55 C to +125 C
Supply voltage
on VCC relative to GND[4] ................... –0.5 V to VCC + 0.5 V
Current into outputs (in LOW state) ............................ 20 mA
Static discharge voltage
(MIL-STD-883, Method 3015) ................................. > 2001 V
Latch-up current .................................................... > 140 mA
Operating Range
DC voltage applied to outputs
in HI-Z State[4] .................................... –0.5 V to VCC + 0.5 V
DC input voltage
[4]
Grade
Industrial
Ambient Temperature
VCC
–40 C to +85 C
1.65 V to 2.2 V,
2.2 V to 3.6 V,
4.5 V to 5.5 V
.............................. –0.5 V to VCC + 0.5 V
DC Electrical Characteristics
Over the operating range of –40 C to 85 C
Parameter
VOH
VOL
VIH
VIL
Description
Output HIGH
voltage
Output LOW
voltage
Input HIGH
voltage
Input LOW voltage
Test Conditions
10 ns / 15 ns
Min
Typ[5]
Max
1.65 V to 2.2 V
VCC = Min, IOH = –0.1 mA
1.4
–
–
2.2 V to 2.7 V
VCC = Min, IOH = –1.0 mA
2
–
–
2.7 V to 3.0 V
VCC = Min, IOH = –4.0 mA
2.2
–
–
3.0 V to 3.6 V
VCC = Min, IOH = –4.0 mA
2.4
–
–
4.5 V to 5.5 V
VCC = Min, IOH = –4.0 mA
2.4
–
–
4.5 V to 5.5 V
VCC = Min, IOH = –0.1 mA
VCC – 0.5[6]
–
–
1.65 V to 2.2 V
VCC = Min, IOL = 0.1 mA
–
–
0.2
2.2 V to 2.7 V
VCC = Min, IOL = 2 mA
–
–
0.4
2.7 V to 3.6 V
VCC = Min, IOL = 8 mA
–
–
0.4
4.5 V to 5.5 V
VCC = Min, IOL = 8 mA
–
–
0.4
1.65 V to 2.2 V
–
1.4
–
VCC + 0.2[4]
2.2 V to 2.7 V
–
2
–
VCC + 0.3[4]
2.7 V to 3.6 V
–
2
–
VCC + 0.3[4]
4.5 V to 5.5 V
–
2
–
VCC + 0.5[4]
1.65 V to 2.2 V
–
–0.2[4]
–
0.4
2.2 V to 2.7 V
–
–0.3[4]
–
0.6
2.7 V to 3.6 V
–
[4]
–0.3
–
0.8
4.5 V to 5.5 V
–
–0.5[4]
–
0.8
Unit
V
V
V
V
IIX
Input leakage current
GND < VIN < VCC
–1
–
+1
A
IOZ
Output leakage current
GND < VOUT < VCC, Output disabled
–1
–
+1
A
ICC
Operating supply current
Max VCC, IOUT = 0 mA,
CMOS levels
f = 100 MHz
–
38
45
f = 66.7 MHz
–
–
40
ISB1
Automatic CE power-down current – Max VCC, CE > VIH,
TTL inputs
VIN > VIH or VIN < VIL, f = fMAX
–
–
15
mA
ISB2
Automatic CE power-down current – Max VCC, CE > VCC – 0.2 V,
CMOS inputs
VIN > VCC – 0.2 V or VIN < 0.2 V, f = 0
–
6
8
mA
mA
Notes
4. VIL(min) = –2.0 V and VIH(max) = VCC + 2 V for pulse durations of less than 20 ns.
5. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = 1.8 V (for VCC range of 1.65 V–2.2 V), VCC = 3 V
(for VCC range of 2.2 V–3.6 V), and VCC = 5 V (for VCC range of 4.5 V–5.5 V), TA = 25 °C.
6. This parameter is guaranteed by design and not tested.
Document Number: 001-95413 Rev. *D
Page 5 of 18
CY7C1041GN
Capacitance
Parameter[7]
Description
CIN
Input capacitance
COUT
I/O capacitance
Test Conditions
TA = 25 C, f = 1 MHz,
VCC = VCC(typ)
48-ball VFBGA
44-pin SOJ
44-pin TSOP II Unit
10
10
10
pF
10
10
10
pF
48-ball VFBGA
44-pin SOJ
31.35
55.37
68.85
C/W
14.74
30.41
15.97
C/W
Thermal Resistance
Parameter[7]
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
Test Conditions
Still air, soldered on a
3 × 4.5 inch, four-layer
printed circuit board
44-pin TSOP II Unit
AC Test Loads and Waveforms
Figure 4. AC Test Loads and Waveforms[8]
High-Z Characteristics:
VCC
50
Output
VTH
Z0 = 50
R1
Output
30 pF*
* Including
jig and
scope
(a)
* Capacitive load consists
of all components of the
test environment
(b)
All Input Pulses
VHIGH
GND
R2
5 pF*
90%
90%
10%
Rise Time:
> 1 V/ns
10%
Fall Time:
> 1 V/ns
(c)
Parameters
1.8 V
3.0 V
5.0 V
Unit
R1
1667
317
317
R2
1538
351
351
VTH
0.9
1.5
1.5
V
VHIGH
1.8
3
3
V
Notes
7. Tested initially and after any design or process changes that may affect these parameters.
8. Full-device AC operation assumes a 100-µs ramp time from 0 to VCC(min) and a 100-µs wait time after VCC stabilization.
Document Number: 001-95413 Rev. *D
Page 6 of 18
CY7C1041GN
Data Retention Characteristics
Over the operating range of –40 C to 85 C
Parameter
VDR
Description
Conditions
Min
Max
Unit
1
–
V
–
8
mA
0
–
ns
VCC > 2.2 V
10
–
ns
VCC < 2.2 V
15
–
ns
VCC for data retention
[9]
VCC = 1.2 V, CE > VCC – 0.2 V ,
VIN > VCC – 0.2 V, or VIN < 0.2 V
ICCDR
Data retention current
tCDR[10]
Chip deselect to data retention
time
tR[9, 10]
Operation recovery time
Data Retention Waveform
Figure 5. Data Retention Waveform[9]
VCC
VCC(min)
DATA RETENTION MODE
VDR = 1.0 V
tCDR
VCC(min)
tR
CE
Notes
9. Full-device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC (min) > 100 s.
10. These parameters are guaranteed by design.
Document Number: 001-95413 Rev. *D
Page 7 of 18
CY7C1041GN
AC Switching Characteristics
Over the operating range of –40 C to 85 C
Parameter[11]
Description
10 ns
Min
15 ns
Max
Min
Max
Unit
Read Cycle
tRC
Read cycle time
10
–
15
–
ns
tAA
Address to data
–
10
–
15
ns
tOHA
Data hold from address change
3
–
3
–
ns
–
10
–
15
ns
[12]
tACE
CE LOW to data
tDOE
OE LOW to data
–
4.5
–
8
ns
tLZOE
OE LOW to low impedance[13, 14]
0
–
0
–
ns
–
5
–
8
ns
3
–
3
–
ns
–
5
–
8
ns
0
–
0
–
ns
–
10
–
15
ns
–
4.5
–
8
ns
0
–
0
–
ns
–
6
–
8
ns
10
–
15
–
ns
tHZOE
tLZCE
OE HIGH to
HI-Z[13, 14]
CE LOW to low
impedance[12, 13, 14]
HI-Z[12, 13, 14]
tHZCE
CE HIGH to
tPU
CE LOW to power-up[12, 14, 15]
power-down[12, 14, 15]
tPD
CE HIGH to
tDBE
Byte enable to data valid
impedance[14]
tLZBE
Byte enable to low
tHZBE
Byte disable to HI-Z[14]
Write
tWC
Cycle[15, 16]
Write cycle time
[12]
tSCE
CE LOW to write end
7
–
12
–
ns
tAW
Address setup to write end
7
–
12
–
ns
tHA
Address hold from write end
0
–
0
–
ns
tSA
Address setup to write start
0
–
0
–
ns
tPWE
WE pulse width
7
–
12
–
ns
tSD
Data setup to write end
5
–
8
–
ns
tHD
Data hold from write end
0
–
0
–
ns
3
–
3
–
ns
–
5
–
8
ns
7
–
12
–
ns
tLZWE
WE HIGH to low impedance
[13, 14]
tHZWE
WE LOW to HI-Z
tBW
Byte Enable to write end
[13, 14]
Notes
11. Test conditions assume a signal transition time (rise/fall) of 3 ns or less, timing reference levels of 1.5 V (for VCC > 3 V) and VCC/2 (for VCC < 3 V), and input pulse
levels of 0 to 3 V (for VCC > 3 V) and 0 to VCC (for VCC < 3 V). Test conditions for the read cycle use output loading, as shown in part (a) of Figure 4 on page 6, unless specified otherwise.
12. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW,
CE is HIGH.
13. tHZOE, tHZCE, tHZWE, tHZBE, tLZOE, tLZCE, tLZWE, and tLZBE are specified with a load capacitance of 5 pF, as shown in part (b) of Figure 4 on page 6. Transition is measured 200 mV from
steady state voltage.
14. These parameters are guaranteed by design and are not tested.
15. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL, and BHE or BLE = VIL. These signals must be LOW to initiate a write, and the
HIGH transition of any of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates
the write.
16. The minimum write cycle pulse width in Write Cycle No. 2 (WE Controlled, OE LOW) should be equal to sum of tSD and tHZWE.
Document Number: 001-95413 Rev. *D
Page 8 of 18
CY7C1041GN
Switching Waveforms
Figure 6. Read Cycle No. 1 (Address Transition Controlled)[17, 18]
tRC
ADDRESS
tAA
tOHA
DATA I/O
PREVIOUS DATAOUT
VALID
DATAOUT VALID
Figure 7. Read Cycle No. 2 (OE Controlled)[18, 19]
ADDRESS
tRC
CE
tPD
tHZCE
tACE
OE
t HZOE
tDOE
tLZOE
BHE/
BLE
tDBE
tLZBE
DATA I/O
HIGH IMPEDANCE
t HZBE
DATAOUT VALID
HIGH
IMPEDANCE
tLZCE
tPU
VCC
SUPPLY
CURRENT
ISB
Notes
17. The device is continuously selected, OE = VIL, CE = VIL, BHE or BLE or both = VIL.
18. WE is HIGH for the read cycle.
19. Address valid prior to or coincident with CE LOW transition.
Document Number: 001-95413 Rev. *D
Page 9 of 18
CY7C1041GN
Switching Waveforms (continued)
Figure 8. Write Cycle No. 1 (CE Controlled)[20, 21]
tW
C
ADDRESS
tS A
tSC E
CE
tA W
tPW
tH A
E
W E
tB W
B H E/
BLE
O E
tHZOE
tH D
tS D
D A T A I /O
D A T AI N
V A L ID
Figure 9. Write Cycle No. 2 (WE Controlled, OE LOW)[20, 21, 22]
tW C
ADDRESS
tSCE
CE
tB W
BHE /
BLE
tS A
tA W
tH A
tPW E
WE
t LZ W E
t HZW E
D A T A I /O
tS D
DATA
tH D
IN
V A L ID
Notes
20. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL, and BHE or BLE = VIL. These signals must be LOW to initiate a write, and the
HIGH transition of any of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates
the write.
21. Data I/O is in HI-Z state if CE = VIH, or OE = VIH, or BHE, and/or BLE = VIH.
22. The minimum write cycle pulse width should be equal to sum of tSD and tHZWE.
Document Number: 001-95413 Rev. *D
Page 10 of 18
CY7C1041GN
Switching Waveforms (continued)
Figure 10. Write Cycle No. 3 (BLE or BHE Controlled)[23, 24]
tWC
ADDRESS
t SCE
CE
tAW
tSA
tHA
tBW
BHE /
BLE
t PWE
WE
t HZWE
tHD
tSD
t LZWE
DATA IN VALID
DATA I /O
Figure 11. Write Cycle No. 4 (WE Controlled)[23, 24, 25]
tWC
ADDRESS
tSCE
CE1
CE2
tAW
tHA
tSA
WE
tPWE
tBW
BHE/BLE
OE
tHD
tSD
DATA I/O
NOTE 26
DATA IN VALID
tHZOE
Notes
23. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL, and BHE or BLE = VIL. These signals must be LOW to initiate a write, and the
HIGH transition of any of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates
the write.
24. Data I/O is in HI-Z state if CE = VIH, or OE = VIH, or BHE, and/or BLE = VIH.
25. Data I/O is high impedance if OE = VIH.
26. During this period the I/Os are in output state. Do not apply input signals.
Document Number: 001-95413 Rev. *D
Page 11 of 18
CY7C1041GN
Truth Table
CE
OE
WE
BLE
BHE
I/O0–I/O7
I/O8–I/O15
H
X[27]
X[27]
X[27]
X[27]
Mode
Power
HI-Z
HI-Z
Power down
Standby (ISB)
L
L
H
L
L
Data out
Data out
Read all bits
Active (ICC)
L
L
H
L
H
Data out
HI-Z
Read lower bits only
Active (ICC)
L
L
H
H
L
HI-Z
Data out
Read upper bits only
Active (ICC)
L
X
L
L
L
Data in
Data in
Write all bits
Active (ICC)
L
X
L
L
H
Data in
HI-Z
Write lower bits only
Active (ICC)
L
X
L
H
L
HI-Z
Data in
Write upper bits only
Active (ICC)
L
H
H
X
X
HI-Z
HI-Z
Selected, outputs disabled
Active (ICC)
Notes
27. The input voltage levels on these pins should be either at VIH or VIL.
Document Number: 001-95413 Rev. *D
Page 12 of 18
CY7C1041GN
Ordering Information
Speed
(ns)
Voltage
Range
2.2 V–3.6 V
10
4.5 V–5.5 V
Package
Diagram
Ordering Code
Package Type
(all Pb-free)
Operating
Range
CY7C1041GN30-10ZSXI
51-85087 44-pin TSOP II
CY7C1041GN30-10ZSXI
51-85087 44-pin TSOP II, Tape & Reel
CY7C1041GN30-10VXI
51-85082 44-pin SOJ
CY7C1041GN30-10VXIT
51-85082 44-pin SOJ, Tape & Reel
CY7C1041GN30-10BVXI
51-85150 48-ball VFBGA (6 × 8 × 1.0 mm)
CY7C1041GN30-10BVXIT
51-85150 48-ball VFBGA (6 × 8 × 1.0 mm), Tape & Reel
CY7C1041GN30-10BVJXI
51-85150 48-ball VFBGA (6 × 8 × 1.0 mm), JEDEC Compatible
CY7C1041GN30-10BVJXIT
51-85150 48-ball VFBGA (6 × 8 × 1.0 mm), JEDEC Compatible, Tape & Reel
CY7C1041GN-10ZSXI
51-85087 44-pin TSOP II
CY7C1041GN-10ZSXIT
51-85087 44-pin TSOP II, Tape & Reel
CY7C1041GN-10VXI
51-85082 44-pin SOJ
CY7C1041GN-10VXIT
51-85082 44-pin SOJ, Tape & Reel
Industrial
Ordering Code Definitions
CY 7 C 1 04 1 GN XX - XX
XX
X
I
X
X: T = Tape & Reel; Blank = Bulk
Temperature Range: I = Industrial
Pb-free
Package Type: XX = ZS or BV or BVJ
ZS = 44-pin TSOP II; V = 44-pin SOJ; BV = 48-ball VFBGA;
BVJ = 48-ball VFBGA JEDEC Compatible
Speed: XX = 10 ns
Voltage Range:
30 = 2.2 V–3.6 V
Process Technology: Revision Code “GN” = 65 nm
Data Width: 1 = × 16-bits
Density: 04 = 4-Mbit
Family Code: 1 = Fast Asynchronous SRAM family
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 001-95413 Rev. *D
Page 13 of 18
CY7C1041GN
Package Diagrams
Figure 12. 44-pin TSOP II (Z44) Package Outline, 51-85087
51-85087 *E
Figure 13. 44-pin SOJ (400 Mils) Package Outline, 51-85082
51-85082 *E
Document Number: 001-95413 Rev. *D
Page 14 of 18
CY7C1041GN
Package Diagrams (continued)
Figure 14. 48-ball VFBGA (6 × 8 × 1.0 mm) BV48/BZ48 Package Outline, 51-85150
51-85150 *H
Document Number: 001-95413 Rev. *D
Page 15 of 18
CY7C1041GN
Acronyms
Acronym
Document Conventions
Description
Units of Measure
BHE
byte high enable
BLE
byte low enable
°C
Degrees Celsius
CE
chip enable
MHz
megahertz
CMOS
complementary metal oxide semiconductor
A
microamperes
I/O
input/output
s
microseconds
OE
output enable
mA
milliamperes
SRAM
static random-access memory
mm
millimeters
TSOP
thin small outline package
ns
nanoseconds
TTL
transistor-transistor logic
ohms
VFBGA
very fine-pitch ball grid array
%
percent
WE
write enable
pF
picofarads
V
volts
W
watts
Document Number: 001-95413 Rev. *D
Symbol
Unit of Measure
Page 16 of 18
CY7C1041GN
Document History Page
Document Title: CY7C1041GN, 4-Mbit (256K words × 16 bit) Static RAM
Document Number: 001-95413
Rev.
ECN No.
Orig. of
Change
Submission
Date
**
5074414
NILE
01/06/2016
New data sheet.
*A
5082573
NILE
01/12/2016
Updated Logic Block Diagram – CY7C1041GN.
Updated Ordering Information:
Updated part numbers.
*B
5120171
VINI
02/01/2016
Updated Logic Block Diagram – CY7C1041GN.
*C
5322961
VINI
06/24/2016
Updated Ordering Information:
Updated part numbers.
Updated to new template.
09/09/2016
Updated Ordering Information: Updated part numbers. Added Tape & Reel
ordering codes.
Updated DC Electrical Characteristics: Enhanced VOH for voltage range 3.0V
to 3.6V from 2.2V to 2.4V. Enhanced VIH for voltage range 4.5V to 5.5V from
2.2V to 2.0V.
Updated Note 4.
Updated Copyright and Disclaimer.
*D
5431651
NILE
Document Number: 001-95413 Rev. *D
Description of Change
Page 17 of 18
CY7C1041GN
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
ARM® Cortex® Microcontrollers
Automotive
cypress.com/arm
cypress.com/automotive
Clocks & Buffers
Interface
cypress.com/clocks
cypress.com/interface
Internet of Things
Lighting & Power Control
Memory
cypress.com/iot
cypress.com/powerpsoc
Cypress Developer Community
Forums | Projects | Video | Blogs | Training | Components
Technical Support
cypress.com/support
cypress.com/memory
PSoC
cypress.com/psoc
Touch Sensing
cypress.com/touch
USB Controllers
Wireless/RF
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document, including
any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide.
Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual
property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby
grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and
reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either
directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as provided
by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the
Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 001-95413 Rev. *D
Revised September 9, 2016
Page 18 of 18
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