CY7C1046BV33-15VC

046BV33 PRELIMINARY CY7C1046BV33 1M x 4 Static RAM Features • High speed — tAA = 10 ns • Low active power for 10 ns speed — 540 mW (max.) • Low CMOS standby power (L version) — 1.8 mW (max.) • 2.0V Data Retention (400 µW at 2.0V retention) • Automatic power-down when deselected • TTL-compatible inputs and outputs • Easy memory expansion with CE and OE features expansion is provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE), and three-state drivers. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the four I/O pins (I/O0 through I/O3) is then written into the location specified on the address pins (A0 through A19). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The four input/output pins (I/O0 through I/O3) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE LOW, and WE LOW). The CY7C1046BV33 is available in a standard 400-mil-wide 32-pin SOJ package with center power and ground (revolutionary) pinout. Functional Description The CY7C1046BV33 is a high-performance CMOS static RAM organized as 1,048,576 words by 4 bits. Easy memory Logic Block Diagram Pin Configuration SOJ Top View A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 INPUT BUFFER I/O0 SENSE AMPS 1M x 4 ARRAY I/O1 I/O2 I/O3 CE WE COLUMN DECODER POWER DOWN A0 A1 A2 A3 A4 CE I/O0 VCC GND I/O1 WE A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A19 A18 A17 A16 A15 OE I/O3 GND VCC I/O2 A14 A13 A12 A11 A10 NC ROW DECODER A 11 A 12 A 13 A14 A15 A16 A17 A18 A19 OE 1046BV33–1 1046BV33–2 Selection Guide 7C1046BV33-10 7C1046BV33-12 Maximum Access Time (ns) Maximum Operating Current (mA) Maximum CMOS Standby Current (mA) Shaded areas contain advance information. 7C1046BV33-15 15 130 8 0.5 10 150 Com’l L version 8 0.5 12 140 8 0.5 Cypress Semiconductor Corporation Document #: 38-05170 Rev. ** • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised September 21, 2001 PRELIMINARY Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage on VCC to Relative GND[1] .... –0.5V to +4.6V DC Voltage Applied to Outputs in High Z State[1] .................................... –0.5V to VCC + 0.5V DC Input Voltage[1] ................................ –0.5V to VCC + 0.5V CY7C1046BV33 Current into Outputs (LOW) ........................................ 20 mA Static Discharge Voltage ........................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current..................................................... >200 mA Operating Range Range Commercial Ambient Temperature[2] 0°C to +70°C VCC 3.0V - 3.6V Electrical Characteristics Over the Operating Range 7C1046BV33-10 7C1046BV33-12 7C1046BV33-15 Parameter VOH VOL VIH VIL IIX IOZ ICC ISB1 Description Test Conditions Min. 2.4 0.4 2.2 –0.5 GND < VI < VCC GND < VOUT < VCC, Output Disabled VCC = Max., f = fMAX = 1/tRC –1 –1 VCC + 0.5 0.8 +1 +1 150 20 2.2 –0.5 –1 –1 Max. Min. 2.4 0.4 VCC + 0.5 0.8 +1 +1 140 20 2.2 –0.5 –1 –1 Max. Min. 2.4 0.4 VCC + 0.5 0.8 +1 +1 130 20 Max. Unit V V V V µA µA mA mA Output HIGH Voltage VCC = Min., IOH = –4.0 mA Output LOW Voltage VCC = Min., IOL = 8.0 mA Input HIGH Voltage Input LOW Voltage[1] Input Load Current Output Leakage Current VCC Operating Supply Current Automatic CE Max. VCC, CE > VIH Power-Down Current VIN > VIH or VIN < VIL, f = fMAX — TTL Inputs Automatic CE Max. VCC, Com’l Power-Down Current CE > VCC – 0.3V, L version VIN > VCC – 0.3V, — CMOS Inputs or VIN < 0.3V, f=0 ISB2 8 0.5 8 0.5 8 0.5 mA Shaded areas contain advance information. Capacitance[3] Parameter CIN COUT Description Input Capacitance I/O Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 3.3V Max. 6 6 Unit pF pF Notes: 1. VIL (min.) = –2.0V for pulse durations of less than 20 ns. 2. TA is the “Instant On” case temperature. 3. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05170 Rev. ** Page 2 of 8 PRELIMINARY AC Test Loads and Waveforms R1 317 Ω R1 317 Ω CY7C1046BV33 ALL INPUT PULSES 3.3V 90% 90% 10% GND 10% 3.3V OUTPUT 30 pF 3.3V OUTPUT R2 351Ω 5 pF R2 351Ω INCLUDING JIG AND SCOPE (a) INCLUDING JIG AND SCOPE (b) Rise Time: 1 V/ns 1046BV33–3 Fall Time: 1 V/ns 1046BV33–4 Equivalent to: THÉVENIN EQUIVALENT 167Ω 1.73V OUTPUT Switching Characteristics[4] Over the Operating Range 7C1046BV33-10 Parameter READ CYCLE tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z[6] OE HIGH to High Z CE LOW to Low Z [5, 6] [6] 7C1046BV33-12 Min. 12 Max. 7C1046BV33-15 Min. 15 Max. Unit ns 15 3 15 7 0 7 3 7 0 15 15 12 12 0 0 12 8 0 3 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 7 ns Description Min. 10 Max. 10 3 10 4 0 5 3 5 0 10 10 7 7 0 0 7 5 0 3 5 12 10 10 0 0 10 7 0 3 0 3 0 3 12 12 6 6 6 12 CE HIGH to High Z[5, 6] CE LOW to Power-Up CE HIGH to Power-Down [7, 8] WRITE CYCLE Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low Z[6] WE LOW to High Z [5, 6] 6 Shaded areas contain advance information. Notes: 4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 5. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage. 6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 7. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 8. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document #: 38-05170 Rev. ** Page 3 of 8 PRELIMINARY s CY7C1046BV33 Data Retention Characteristics Over the Operating Range Parameter VDR ICCDR tCDR tR[9] [3] Description VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time Com’l Conditions[10] VCC = VDR = 2.0V, CE > VCC – 0.3V VIN > VCC – 0.3V or VIN < 0.3V Min. 2.0 Max 200 Unit V µA ns µs 0 10 Data Retention Waveform DATA RETENTION MODE VCC 3.0V tCDR CE 1046BV33–5 VDR > 2V 3.0V tR Switching Waveforms Read Cycle No. 1[11, 12] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID 1046BV33–6 Read Cycle No. 2 (OE Controlled)[12, 13] ADDRESS tRC CE tACE OE tDOE tLZOE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% tHZOE tHZCE DATA VALID tPD 50% 1046BV33-7 HIGH IMPEDANCE DATA OUT ICC ISB Notes: 9. tr < 3 ns for the -10, -12, and -15 speeds. 10. No input may exceed VCC + 0.5V. 11. Device is continuously selected. OE, CE = VIL. 12. WE is HIGH for read cycle. 13. Address valid prior to or coincident with CE transition LOW. Document #: 38-05170 Rev. ** Page 4 of 8 PRELIMINARY Switching Waveforms (continued) Write Cycle No. 1 (CE Controlled)[14, 15] tWC ADDRESS tSCE CE tSA tSCE tAW tPWE WE tSD DATA I/O DATA VALID tHD tHA CY7C1046BV33 1046BV33–8 Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[14, 15] tWC ADDRESS tSCE CE tAW tSA WE tPWE tHA OE tSD DATA I/O NOTE 16 tHZOE 1046BV33–9 tHD DATAIN VALID Notes: 14. Data I/O is high impedance if OE = VIH. 15. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. 16. During this period the I/Os are in the output state and input signals should not be applied. Document #: 38-05170 Rev. ** Page 5 of 8 PRELIMINARY Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled, OE LOW)[15] tWC ADDRESS tSCE CE CY7C1046BV33 tAW tSA WE tSD DATA I/O NOTE 16 tHZWE DATA VALID tPWE tHA tHD tLZWE 1046BV33–10 Truth Table CE H L L L OE X L X H WE X H L H I/O0 - I/O7 High Z Data Out Data In High Z Power-Down Read Write Selected, Outputs Disabled Mode Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Ordering Information Speed (ns) 10 12 15 10 12 15 Ordering Code CY7C1046BV33-10VC CY7C1046BV33-12VC CY7C1046BV33-15VC CY7C1046BV33L-10VC CY7C1046BV33L-12VC CY7C1046BV33L-15VC Package Name V33 V33 V33 V33 V33 V33 Package Type 32-Lead (400-Mil) Molded SOJ 32-Lead (400-Mil) Molded SOJ 32-Lead (400-Mil) Molded SOJ 32-Lead (400-Mil) Molded SOJ 32-Lead (400-Mil) Molded SOJ 32-Lead (400-Mil) Molded SOJ Operating Range Commercial Shaded areas contain pre-release information. Document #: 38-05170 Rev. ** Page 6 of 8 PRELIMINARY CY7C1046BV33 Package Diagram 32-Lead (400-Mil) Molded SOJ V33 51-85033-A Document #: 38-05170 Rev. ** Page 7 of 8 © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. PRELIMINARY Document Title: CY7C1046BV33 1M x 4 Static RAM Document Number: 38-05170 REV. ** ECN NO. 110210 Issue Date 12/02/01 Orig. of Change SZV Description of Change Change from Spec number: 38-00949 to 38-05170 CY7C1046BV33 Document #: 38-05170 Rev. ** Page 8 of 8