CY7C1049BNL-17VCT

1CY7C1049BN CY7C1049BN 512 K × 8 Static RAM Features Functional Description ■ High speed ❐ tAA = 17 ns ■ Low active power ❐ 1073 mW (max.) ■ Low CMOS standby power ❐ 2.75 mW (max.) ■ 2.0 V data retention (400 W at 2.0 V retention) The CY7C1049BN is a high-performance CMOS static RAM organized as 524,288 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE), and three-state drivers. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A18). ■ Automatic power-down when deselected ■ TTL-compatible inputs and outputs ■ Easy memory expansion with CE and OE features Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE LOW, and WE LOW). The CY7C1049BN is available in a standard 400-mil-wide 36-pin SOJ package with center power and ground (revolutionary) pinout. Logic Block Diagram I/O0 INPUT BUFFER I/O1 I/O2 SENSE AMPS ROW DECODER A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 512K x 8 ARRAY I/O3 I/O4 I/O5 I/O6 POWER DOWN COLUMN DECODER CE I/O7 A 11 A 12 A 13 A14 A15 A16 A17 A18 WE OE Selection Guide CY7C1049BNL-17 Maximum Access Time (ns) 17 Maximum Operating Current (mA) 195 Maximum CMOS Standby Current (mA) 0.5 Cypress Semiconductor Corporation Document #: 001-76449 Rev. ** • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised March 1, 2012 CY7C1049BN Contents Pinouts .............................................................................. 3 Maximum Ratings ............................................................. 3 Operating Range ............................................................... 3 Electrical Characteristics ................................................. 3 Capacitance ...................................................................... 4 AC Test Loads and Waveforms ....................................... 4 Switching Characteristics ................................................ 5 Data Retention Characteristics ....................................... 6 Data Retention Waveform ................................................ 6 Switching Waveforms ...................................................... 7 Truth Table ........................................................................ 9 Document #: 001-76449 Rev. ** Ordering Information ........................................................ 9 Ordering Code Definitions ......................................... 10 Package Diagram ............................................................ 10 Acronyms ........................................................................ 11 Document Conventions ................................................. 11 Units of Measure ....................................................... 11 Document History Page ................................................. 12 Sales, Solutions, and Legal Information ...................... 12 Worldwide Sales and Design Support ....................... 12 Products .................................................................... 12 PSoC Solutions ......................................................... 12 Page 2 of 12 CY7C1049BN Pinouts SOJ Top View A0 A1 A2 A3 A4 CE I/O0 I/O1 VCC GND I/O2 I/O3 WE A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Maximum Ratings 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 NC A18 A17 A16 A15 OE I/O7 I/O6 GND VCC I/O5 I/O4 A14 A13 A12 A11 A10 NC Current into Outputs (LOW)......................................... 20 mA Exceeding maximum ratings may shorten the useful life of the device. These user guidelines are not tested. Static Discharge Voltage........................................... >2001 V (per MIL-STD-883, Method 3015) Storage Temperature ............................... –65 C to +150 C Latch-Up Current ..................................................... >200 mA Ambient Temperature with Power Applied .......................................... –55 C to +125 C Operating Range Supply Voltage on VCC to Relative GND[1] ...–0.5 V to +7.0 V Range DC Voltage Applied to Outputs in High Z State[1] .................................. –0.5 V to VCC + 0.5 V Commercial L Ambient Temperature VCC 0 C to +70 C 4.5 V–5.5 V DC Input Voltage[1] .............................. –0.5 V to VCC + 0.5 V Electrical Characteristics Over the Operating Range Parameter Description Test Conditions 7C1049B-17 Min. Max. 2.4 Unit VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA V VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA 0.4 V VIH Input HIGH Voltage 2.2 VCC+0.3 V VIL Input LOW Voltage[1] –0.3 0.3 V IIX Input Load Current GND < VI < VCC –1 +1 A IOZ Output Leakage Current GND < VOUT < VCC, Output Disabled –1 +1 A ICC VCC Operating Supply Current VCC = Max., f = fMAX = 1/tRC 195 mA ISB1 Automatic CE Power-Down Current —TTL Inputs Max. VCC, CE > VIH VIN > VIH or VIN < VIL, f = fMAX 40 mA ISB2 Automatic CE Power-Down Current —CMOS Inputs Max. VCC, CE > VCC – 0.3V, VIN > VCC – 0.3V, or VIN < 0.3V, f = 0 Com’l 0.5 mA Note 1. Minimum voltage is–2.0V for pulse durations of less than 20 ns. Document #: 001-76449 Rev. ** Page 3 of 12 CY7C1049BN Capacitance[2] Parameter Description CIN Input Capacitance COUT I/O Capacitance Test Conditions Max. TA = 25 C, f = 1 MHz, VCC = 5.0 V Unit 8 pF 8 pF AC Test Loads and Waveforms R1 481 5V OUTPUT ALL INPUT PULSES R1 481 5V 3.0V 90% OUTPUT 30 pF R2 255 INCLUDING JIG AND SCOPE (a) 5 pF R2 255 INCLUDING JIG AND SCOPE (b) GND 3 ns 10% 90% 10%  3 ns THÉVENIN EQUIVALENT 167 1.73V OUTPUT Equivalent to: Note 2. Tested initially and after any design or process changes that may affect these parameters. Document #: 001-76449 Rev. ** Page 4 of 12 CY7C1049BN Switching Characteristics[3] Over the Operating Range Parameter Description CY7C1049BNL-17 Min. Max. Unit Read Cycle tpower VCC(typical) to the First Access[4] 1 – ms tRC Read Cycle Time 17 – ns tAA Address to Data Valid – 17 ns tOHA Data Hold from Address Change 3 – ns tACE CE LOW to Data Valid – 17 ns tDOE OE LOW to Data Valid – 8 ns [6] tLZOE OE LOW to Low Z 0 – ns tHZOE OE HIGH to High Z[5, 6] – 7 ns 3 – ns – 7 ns tLZCE CE LOW to Low Z[6] Z[5, 6] tHZCE CE HIGH to High tPU CE LOW to Power-Up 0 – ns tPD CE HIGH to Power-Down – 17 ns tWC Write Cycle Time 17 – ns tSCE CE LOW to Write End 12 – ns tAW Address Set-Up to Write End 12 – ns tHA Address Hold from Write End 0 – ns tSA Address Set-Up to Write Start 0 – ns tPWE WE Pulse Width 12 – ns tSD Data Set-Up to Write End 8 – ns tHD Data Hold from Write End 0 – ns 3 – ns – 8 ns Write tLZWE tHZWE Cycle[7, 8] WE HIGH to Low Z[6] [5, 6] WE LOW to High Z Notes 3. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 4. This part has a voltage regulator which steps down the voltage from 5V to 3.3V internally. tpower time has to be provided initially before a read/write operation is started. 5. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured 500 mV from steady-state voltage. 6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 7. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 8. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document #: 001-76449 Rev. ** Page 5 of 12 CY7C1049BN Data Retention Characteristics Over the Operating Range Parameter [2] Com’l Chip Deselect to Data Retention Time [9] Max 2.0 Data Retention Current ICCDR tR Min. VCC for Data Retention VDR tCDR Conditions[10] Description Operation Recovery Time L VCC = VDR = 3.0 V, CE > VCC – 0.3 V VIN > VCC – 0.3 V or VIN < 0.3 V Unit V 200 A 0 ns tRC ns Data Retention Waveform DATA RETENTION MODE VCC 3.0 V tCDR VDR > 2 V 3.0 V tR CE Notes 9. tr < 3 ns for the -12 and -15 speeds. tr < 5 ns for the -20 and slower speeds. 10. No input may exceed VCC + 0.5V. Document #: 001-76449 Rev. ** Page 6 of 12 CY7C1049BN Switching Waveforms Figure 1. Read Cycle No. 1[11, 12] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Figure 2. Read Cycle No. 2 (OE Controlled)[12, 13] ADDRESS tRC CE tACE OE tHZOE tDOE DATA OUT tLZOE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tHZCE HIGH IMPEDANCE DATA VALID tPD tPU 50% ICC 50% ISB Notes 11. Device is continuously selected. OE, CE = VIL. 12. WE is HIGH for read cycle. 13. Address valid prior to or coincident with CE transition LOW. Document #: 001-76449 Rev. ** Page 7 of 12 CY7C1049BN Switching Waveforms (continued) Figure 3. Write Cycle No. 1 (CE Controlled)[14, 15] tWC ADDRESS tSCE CE tSA tSCE tAW tHA tPWE WE tSD DATA I/O tHD DATA VALID Figure 4. Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[14, 15] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE OE tSD DATA I/O tHD DATAIN VALID NOTE 16 tHZOE Notes 14. Data I/O is high impedance if OE = VIH. 15. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. 16. During this period the I/Os are in the output state and input signals should not be applied. Document #: 001-76449 Rev. ** Page 8 of 12 CY7C1049BN Switching Waveforms (continued) Figure 5. Write Cycle No. 3 (WE Controlled, OE LOW)[15] tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE tSD NOTE 16 DATA I/O tHD DATA VALID tLZWE tHZWE Truth Table CE WE OE Inputs/Outputs Mode Power H X X High Z Power-down Standby (ISB) L H L Data Out Read Active (ICC) L L X Data In Write Active (ICC) L H H High Z Selected, Output disabled Active (ICC) Ordering Information The following table contains only the parts that are currently available. If you do not see what you are looking for, contact your local sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products. Speed (ns) 17 Ordering Code Package Diagram Package Type CY7C1049BNL-17VC 51-85090 36-pin (400-Mil) Molded SOJ Document #: 001-76449 Rev. ** Operating Range Commercial L Page 9 of 12 CY7C1049BN Ordering Code Definitions CY 7 C 1 - 04 9 BN L 17 V C Commerical Molded SOJ Speed: 17 ns Low power 180 nm technology Data width x 8-bits 4-Mbit density Fast asynchronous SRAM family Technology code: CMOS SRAM Company Code: CY = Cypress Package Diagram 51-85090 *F Document #: 001-76449 Rev. ** Page 10 of 12 CY7C1049BN Acronyms Table 1. Acronyms Used in this Document Acronym Description CE chip enable CMOS complementary metal oxide semiconductor I/O input/output OE output enable SRAM static random access memory WE write enable Document Conventions Units of Measure Table 2. Units of Measure Symbol Unit of Measure ns nanosecond V volt µA microampere mA milliampere mV millivolt mW milliwatt MHz megahertz pF picofarad °C degree Celsius W watt Document #: 001-76449 Rev. ** Page 11 of 12 CY7C1049BN Document History Page Document Title: CY7C1049BN 512 K × 8 Static RAM Document Number: 001-76449 Revision ECN Orig. of Change Submission Date ** 3539227 TAVA 03/01/2012 Description of Change New datasheet Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive cypress.com/go/clocks psoc.cypress.com/solutions cypress.com/go/interface PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/powerpsoc cypress.com/go/plc Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2012. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. 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Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 001-76449 Rev. ** Revised March 1, 2012 All products and company names mentioned in this document may be the trademarks of their respective holders. Page 12 of 12