CY7C1049BV33-12VC

049BV33 CY7C1049BV33 512K x 8 Static RAM Features • High speed — tAA = 15 ns • Low active power — 504 mW (max.) • Low CMOS standby power (Commercial L version) — 1.8 mW (max.) • 2.0V Data Retention (660 µW at 2.0V retention) • Automatic power-down when deselected • TTL-compatible inputs and outputs • Easy memory expansion with CE and OE features expansion is provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE), and three-state drivers. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A18). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE LOW, and WE LOW). The CY7C1049BV33 is available in a standard 400-mil-wide 36-pin SOJ and 44-pin TSOPII packages with center power and ground (revolutionary) pinout. Functional Description[1] The CY7C1049BV33 is a high-performance CMOS Static RAM organized as 524,288 words by 8 bits. Easy memory Logic Block Diagram Pin Configuration SOJ Top View TSOP II Top View NC A18 A17 A16 A15 OE I/O7 I/O6 GND VCC I/O5 I/O4 A14 A13 A12 A11 A10 NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 I/O0 INPUT BUFFER A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 I/O1 ROW DECODER I/O2 SENSE AMPS 512K x 8 ARRAY I/O3 I/O4 I/O5 CE WE OE COLUMN DECODER POWER DOWN I/O6 I/O7 Selection Guide -12 Maximum Access Time (ns) Maximum Operating Current (mA) Comm’l Ind’l Maximum CMOS Standby Current (mA) Com’l/Ind’l Com’l L 12 200 220 8 0.5 -15 15 180 200 8 0.5 -17 17 170 180 8 0.5 -20 20 160 170 8 0.5 -25 25 150 170 8 0.5 Note: 1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05139 Rev. *A A 11 A 12 A 13 A14 A15 A16 A17 A18 A0 A1 A2 A3 A4 CE I/O0 I/O1 VCC GND I/O2 I/O3 WE A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 NC NC NC A0 A1 A2 A3 A4 CE I/O0 I/O1 VCC VSS I/O2 I/O3 WE A5 A6 A7 A8 A9 NC NC A18 A17 A16 A15 OE I/O7 I/O6 VSS VCC I/O5 I/O4 A14 A13 A12 A11 A10 NC NC NC • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised September 13, 2002 CY7C1049BV33 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage on VCC to Relative GND[2].....–0.5V to +4.6V DC Voltage Applied to Outputs[2] in High Z State ....................................... –0.5V to VCC + 0.5V DC Input Voltage[2] ................................ –0.5V to VCC + 0.5V Current into Outputs (LOW) ........................................ 20 mA Operating Range Range Commercial Industrial Ambient Temperature 0°C to +70°C –40°C to +85°C VCC 3.3V ± 0.3V DC Electrical Characteristics Over the Operating Range Parameter VOH VOL VIH VIL IIX IOZ ICC ISB1 -12 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[2] Input Load Current Output Leakage Current VCC Operating Supply Current Automatic CE Power-Down Current — TTL Inputs Automatic CE Power-Down Current — CMOS Inputs GND < VI < VCC GND < VOUT < VCC, Output Disabled VCC = Max., f = fMAX = 1/tRC Max. VCC, CE > VIH VIN > VIH or VIN < VIL, f = fMAX Max. VCC, CE > VCC – 0.3V, VIN > VCC – 0.3V, or VIN < 0.3V, f = 0 Com’l/Ind’l Com’l L Comm’l Ind’l Test Conditions VCC = Min., IOH = –4.0 mA VCC = Min., IOL = 8.0 mA 2.2 –0.5 –1 –1 Min. 2.4 0.4 VCC + 0.5 0.8 +1 +1 200 220 30 2.2 –0.5 –1 –1 Max. Min. 2.4 0.4 VCC + 0.5 0.8 +1 +1 180 200 30 2.2 –0.5 –1 –1 -15 Max. Min. 2.4 0.4 VCC + 0.5 0.8 +1 +1 170 180 30 -17 Max. Unit V V V V µA µA mA mA mA ISB2 8 0.5 8 0.5 8 0.5 mA mA Note: 2. VIL (min.) = –2.0V for pulse durations of less than 20 ns. Document #: 38-05139 Rev. *A Page 2 of 10 CY7C1049BV33 DC Electrical Characteristics Over the Operating Range (continued) -20 Parameter VOH VOL VIH VIL IIX IOZ ICC ISB1 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current Output Leakage Current VCC Operating Supply Current Automatic CE Power-Down Current — TTL Inputs Automatic CE Power-Down Current — CMOS Inputs [2] -25 Max. Min. 2.4 0.4 0.4 2.2 –0.5 –1 –1 VCC + 0.5 0.8 +1 +1 150 170 30 Max. Unit V V V V µA µA mA mA mA Test Conditions VCC = Min., IOH = –4.0 mA VCC = Min., IOL = 8.0 mA Min. 2.4 2.2 –0.5 GND < VI < VCC GND < VOUT < VCC, Output Disabled VCC = Max., f = fMAX = 1/tRC Max. VCC, CE > VIH VIN > VIH or VIN < VIL, f = fMAX Max. VCC, CE > VCC – 0.3V, VIN > VCC – 0.3V, or VIN < 0.3V, f = 0 Com’l/Ind’l Com’l L Com’l Ind’l –1 –1 VCC + 0.5 0.8 +1 +1 160 170 30 ISB2 8 0.5 8 0.5 mA mA Capacitance[3] Parameter CIN COUT Description Input Capacitance I/O Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 3.3V Max. 8 8 Unit pF pF AC Test Loads and Waveforms 3.3V OUTPUT 30 pF INCLUDING JIG AND SCOPE (a) R2 351Ω R1 317 Ω THÉVENIN EQUIVALENT 167 Ω OUTPUT ALL INPUT PULSES 3.3V 1.73V GND RiseTime:1 V/ns 90% 10% 90% 10% Fall time: 1 V/ns (b) Note: 3. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05139 Rev. *A Page 3 of 10 CY7C1049BV33 AC Switching Characteristics[4] Over the Operating Range -12 Parameter Read Cycle tpower tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE VCC(typical) to the First Access[5] Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z OE HIGH to High Z[6, 7] CE LOW to Low Z[7] Z[6, 7] 0 12 12 10 10 0 0 10 7 0 3 6 15 12 12 0 0 12 8 0 3 7 3 6 0 15 17 13 13 0 0 13 9 0 3 8 CE HIGH to High 0 6 3 7 0 17 3 12 6 0 7 3 8 1 12 12 3 15 7 0 8 1 15 15 3 17 8 1 17 17 µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description Min. Max. Min. -15 Max. Min. -17 Max. Unit CE LOW to Power-Up CE HIGH to Power-Down Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low WE LOW to High Z[7] Z[6, 7] Write Cycle[8, 9] Notes: 4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 5. This part has a voltage regulator which steps down the voltage from 5V to 3.3V internally. T.power time has to be provided initially before a read/write operation is started. 6. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 500 mV from steady-state voltage. 7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 8. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 9. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document #: 38-05139 Rev. *A Page 4 of 10 CY7C1049BV33 AC Switching Characteristics[4] Over the Operating Range (continued) -20 Parameter Read Cycle tpower tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD Write tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE Cycle[9] Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low Z[7] WE LOW to High Z[6, 7] 20 13 13 0 0 13 9 0 3 8 25 15 15 0 0 15 10 0 3 10 ns ns ns ns ns ns ns ns ns ns VCC(typical) to the First Access[6] Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z OE HIGH to High Z[6, 7] CE LOW to Low Z[7] Z[6, 7] 0 20 3 8 0 25 CE HIGH to High 0 8 3 10 3 20 8 0 10 1 20 20 3 25 10 1 25 25 µs ns ns ns ns ns ns ns ns ns ns ns Description Min. Max. Min. -25 Max. Unit CE LOW to Power-Up CE HIGH to Power-Down Data Retention Characteristics Over the Operating Range (For L version only) Parameter VDR ICCDR tCDR [3] Description VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time Conditions[10] VCC = VDR = 2.0V, CE > VCC – 0.3V VIN > VCC – 0.3V or VIN < 0.3V Min. 2.0 Max 330 Unit V µA ns ns 0 tRC tR[11] Notes: 10. No input may exceed VCC + 0.5V 11. .tr < 3 ns for the -12 and -15 speeds. tr < 5 ns for the -20 ns and slower speeds. Document #: 38-05139 Rev. *A Page 5 of 10 CY7C1049BV33 Data Retention Waveform DATA RETENTION MODE VCC CE 3.0V tCDR VDR > 2V 3.0V tR Switching Waveforms Read Cycle No. 1[12, 13] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Read Cycle No. 2 (OE Controlled)[13, 14] ADDRESS tRC CE tACE OE tDOE tLZOE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% tHZOE tHZCE DATA VALID tPD 50% ISB ICC HIGH IMPEDANCE DATA OUT Notes: 12. Device is continuously selected. OE, CE = VIL. 13. WE is HIGH for read cycle. 14. Address valid prior to or coincident with CE transition LOW. Document #: 38-05139 Rev. *A Page 6 of 10 CY7C1049BV33 Switching Waveforms (continued) Write Cycle No. 1(WE Controlled, OE HIGH During Write)[15, 16] tWC ADDRESS tSCE CE tAW tSA WE tPWE tHA OE tSD DATA I/O NOTE 17 tHZOE DATAIN VALID tHD Write Cycle No. 2 (WE Controlled, OE LOW)[16] tWC ADDRESS tSCE CE tAW tSA WE tSD DATA I/O NOTE 17 tHZWE DATA VALID tPWE tHA tHD tLZWE Truth Table CE H L L L OE X L X H WE X H L H I/O0 – I/O7 High Z Data Out Data In High Z Power-Down Read Write Selected, Outputs Disabled Mode Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Notes: 15. Data I/O is high-impedance if OE = VIH. 16. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. 17. During this period the I/Os are in the output state and input signals should not be applied. Document #: 38-05139 Rev. *A Page 7 of 10 CY7C1049BV33 Ordering Information Speed (ns) 12 Ordering Code CY7C1049BV33-12VC CY7C1049BV33-12ZC CY7C1049BV33L-12VC CY7C1049BV33-12VI 15 CY7C1049BV33-15VC CY7C1049BV33L-15VC CY7C1049BV33-15ZC CY7C1049BV33L-15ZC CY7C1049BV33-15VI CY7C1049BV33-15ZI 17 CY7C1049BV33-17VC CY7C1049BV33L-17VC CY7C1049BV33-17ZC CY7C1049BV33L-17ZC CY7C1049BV33-17VI CY7C1049BV33L-17VI CY7C1049BV33-17ZI 20 CY7C1049BV33-20VC CY7C1049BV33L-20VC CY7C1049BV33-20ZC CY7C1049BV33L-20ZC CY7C1049BV33-20VI CY7C1049BV33-20ZI 25 CY7C1049BV33-25VC CY7C1049BV33L-25VC CY7C1049BV33-25ZC CY7C1049BV33L-25ZC CY7C1049BV33-25VI Package Name V36 Z44 V36 V36 V36 V36 Z44 Z44 V36 Z44 V36 V36 Z44 Z44 V36 V36 Z44 V36 V36 Z44 Z44 V36 Z44 V36 V36 Z44 Z44 v36 Package Type 36-Lead (400-Mil) Molded SOJ 44-Pin TSOP II Z44 36-Lead (400-Mil) Molded SOJ 36-Lead (400-Mil) Molded SOJ 36-Lead (400-Mil) Molded SOJ 36-Lead (400-Mil) Molded SOJ 44-Pin TSOP II Z44 44-Pin TSOP II Z44 36-Lead (400-Mil) Molded SOJ 44-Pin TSOP II Z44 36-Lead (400-Mil) Molded SOJ 36-Lead (400-Mil) Molded SOJ 44-Pin TSOP II Z44 44-Pin TSOP II Z44 36-Lead (400-Mil) Molded SOJ 36-Lead (400-Mil) Molded SOJ 44-Pin TSOP II Z44 36-Lead (400-Mil) Molded SOJ 36-Lead (400-Mil) Molded SOJ 44-Pin TSOP II Z44 44-Pin TSOP II Z44 36-Lead (400-Mil) Molded SOJ 44-Pin TSOP II Z44 36-Lead (400-Mil) Molded SOJ 36-Lead (400-Mil) Molded SOJ 44-Pin TSOP II Z44 44-Pin TSOP II Z44 36-Lead (400-Mil) Molded SOJ Industrial Commercial Industrial Commercial Industrial Commercial Industrial Industrial Commercial Operating Range Commercial Document #: 38-05139 Rev. *A Page 8 of 10 CY7C1049BV33 Package Diagrams 36-Lead (400-Mil) Molded SOJ V36 51-85090-*B 44-Pin TSOP II Z44 51-85087-*A All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05139 Rev. *A Page 9 of 10 © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C1049BV33 Document History Page Document Title: CY7C1049BV33 512K x 8 Static RAM Document Number: 38-05139 REV. ** *A ECN NO. 113091 116475 Issue Date 02/13/02 09/16/02 Orig. of Change DSG CEA Description of Change Change from Spec number: 38-00931 to 38-05139 Add applications foot note to data sheet, page 1 Document #: 38-05139 Rev. *A Page 10 of 10