CY7C1049DV33-10VXI

CY7C1049DV33 4-Mbit (512K x 8) Static RAM Features ■ ■ Functional Description The CY7C1049DV33 is a high performance CMOS Static RAM organized as 512K words by 8-bits. Easy memory expansion is provided by an Active LOW Chip Enable (CE), an Active LOW Output Enable (OE), and tri-state drivers. You can write to the device by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight IO pins (IO0 through IO7) is then written into the location specified on the address pins (A0 through A18). You can read from the device by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins appear on the IO pins. The eight input or output pins (IO0 through IO7) are placed in a high impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE LOW, and WE LOW). The CY7C1049DV33 is available in standard 400 Mil wide 36 -pin SOJ package and 44-pin TSOP II package with center power and ground (revolutionary) pinout. Refer to the Cypress application note AN1064, SRAM System Guidelines for best practice recommendations. Pin and function compatible with CY7C1049CV33 High speed ❐ tAA = 10 ns Low active power ❐ ICC = 90 mA @ 10 ns (Industrial) Low CMOS standby power ❐ ISB2 = 10 mA 2.0V data retention Automatic power down when deselected TTL compatible inputs and outputs Easy memory expansion with CE and OE features Available in Pb-free 36-pin (400 Mil) Molded SOJ and 44-pin TSOP II packages ■ ■ ■ ■ ■ ■ ■ Logic Block Diagram INPUT BUFFER A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 CE WE OE IO0 IO1 ROW DECODER 512K x 8 ARRAY SENSE AMPS IO2 IO3 IO4 IO5 IO6 COLUMN DECODER POWER DOWN IO7 A11 A12 A13 A14 A15 A16 A17 A18 Cypress Semiconductor Corporation Document Number: 38-05475 Rev. *D • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised July 23, 2007 CY7C1049DV33 Pin Configuration 44-Pin TSOP II Top View NC NC A0 A1 A2 A3 A4 CE IO0 IO1 VCC VSS IO2 IO3 WE A5 A6 A7 A8 A9 NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 NC NC NC A18 A17 A16 A15 OE IO7 IO6 VSS VCC IO5 IO4 A14 A13 A12 A11 A10 NC NC NC 36-Pin SOJ Top View A0 A1 A2 A3 A4 CE IO0 IO1 VCC GND IO2 IO3 WE A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 NC A18 A17 A16 A15 OE IO7 IO6 GND VCC IO5 IO4 A14 A13 A12 A11 A10 NC Selection Guide -10 (Industrial) Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 10 90 10 -12 (Automotive)[1] 12 95 15 Unit ns mA mA Note 1. Automotive product information is preliminary. Document Number: 38-05475 Rev. *D Page 2 of 10 CY7C1049DV33 Maximum Ratings Exceeding the maximum ratings may impair the useful life of the device. User guidelines are not tested. Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied ............................................ –55°C to +125°C Supply Voltage on VCC to Relative GND[2] .....–0.3V to +4.6V DC Voltage Applied to Outputs in High Z State[2] .................................... –0.3V to VCC + 0.3V DC Input Voltage[2] ................................ –0.3V to VCC + 0.3V Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage............. ...............................>2001V (MIL-STD-883, Method 3015) Latch up Current...................................................... >200 mA Operating Range Range Industrial Automotive Ambient Temperature –40°C to +85°C –40°C to +125°C VCC 3.3V ± 0.3V 3.3V ± 0.3V Speed 10 ns 12 ns Electrical Characteristics Over the Operating Range -10 (Industrial) Parameter VOH VOL VIH[2] VIL[2] IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[2] GND < VI < VCC GND < VOUT < VCC, Output Disabled VCC = Max, f = fMAX = 1/tRC 100 MHz 83 MHz 66 MHz 40 MHz ISB1 Automatic CE Power down Current —TTL Inputs Automatic CE Power down Current —CMOS Inputs Max VCC, CE > VIH; VIN > VIH or VIN < VIL, f = fMAX Max VCC, CE > VCC – 0.3V, VIN > VCC – 0.3V, or VIN < 0.3V, f = 0 Test Conditions VCC = Min, IOH = –4.0 mA VCC = Min, IOL = 8.0 mA 2.0 –0.3 –1 –1 Min 2.4 0.4 VCC + 0.3 0.8 +1 +1 90 80 70 60 20 2.0 –0.3 –1 –1 Max -12 (Automotive) Min 2.4 0.4 VCC + 0.3 0.8 +1 +1 95 85 75 25 Max Unit V V V V µA µA mA mA mA mA mA Input Leakage Current Output Leakage Current VCC Operating Supply Current ISB2 10 15 mA Capacitance Tested initially and after any design or process changes that may affect these parameters. Parameter CIN COUT Description Input Capacitance IO Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 3.3V Max 8 8 Unit pF pF Note 2. VIL (min.) = –2.0V and VIH(max) = VCC + 2V for pulse durations of less than 20 ns. Document Number: 38-05475 Rev. *D Page 3 of 10 CY7C1049DV33 Thermal Resistance Tested initially and after any design or process changes that may affect these parameters. Parameter ΘJA ΘJC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Still Air, soldered on a 3 × 4.5 inch, two layer printed circuit board SOJ Package 57.91 36.73 TSOP II Package 50.66 17.17 Unit °C/W °C/W AC Test Loads and Waveforms Figure 1. AC Test Loads and Waveforms [4] 10 ns device OUTPUT 50Ω * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT High Z characteristics: 3.3V OUTPUT 5 pF R2 351Ω 1.5V Z = 50Ω 3.0V ALL INPUT PULSES 90% 10% 90% 10% 30 pF* GND (a) R 317 Ω Rise Time: 1 V/ns (b) Fall Time: 1 V/ns (c) Data Retention Characteristics Over the Operating Range Parameter VDR ICCDR tCDR tR [6] [3] Description VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time Conditions [5] VCC = VDR = 2.0V, CE > VCC – 0.3V VIN > VCC – 0.3V or VIN < 0.3V Ind’l Auto Min 2.0 Max 10 15 Unit V mA mA ns ns 0 tRC Figure 2. Data Retention Waveform DATA RETENTION MODE VCC CE 3.0V tCDR VDR > 2V 3.0V tR Note 3. Tested initially and after any design or process changes that may affect these parameters. 4. AC characteristics (except High Z) are tested using the load conditions shown in Figure 1. High Z characteristics are tested for all speeds using the test load shown in Figure (c). 5. No input may exceed VCC + 0.3V. 6. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 50 µs or stable at VCC(min.) > 50 µs. Document Number: 38-05475 Rev. *D Page 4 of 10 CY7C1049DV33 AC Switching Characteristics Over the Operating Range [7] -10 (Industrial) Parameter Read Cycle tpower[8] tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD VCC(typical) to the first access Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z OE HIGH to High CE LOW to Low Z[9, 10] 3 5 0 10 10 7 7 0 0 7 5 0 3 5 12 8 8 0 0 8 6 0 3 6 0 12 Z[10] 0 5 3 6 3 10 5 0 6 100 10 10 3 12 6 100 12 12 µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description Min Max -12 (Automotive) Min Max Unit CE HIGH to High-Z[9, 10] CE LOW to Power up CE HIGH to Power down Write Cycle Time CE LOW to Write End Address Set up to Write End Address Hold from Write End Address Set up to Write Start WE Pulse Width Data Set up to Write End Data Hold from Write End WE HIGH to Low WE LOW to High Z[10] Z[9, 10] Write Cycle[11, 12] tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE Notes 7. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30 pF load capacitance. 8. tPOWER gives the minimum amount of time that the power supply must be at stable, typical VCC values until the first memory access is performed. 9. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads. Transition is measured when the outputs enter a high impedance state. 10. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 11. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of these signals can terminate the write. The input data set up and hold timing must be referred to the leading edge of the signal that terminates the write. 12. The minimum write cycle time for Write Cycle No. 2 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document Number: 38-05475 Rev. *D Page 5 of 10 CY7C1049DV33 Switching Waveforms Figure 3. Read Cycle No. 1[13, 14] tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID Figure 4. Read Cycle No. 2 (OE Controlled)[14, 15] ADDRESS tRC CE tACE OE tDOE DATA OUT VCC SUPPLY CURRENT tLZOE HIGH IMPEDANCE tLZCE tPU 50% DATA VALID tPD 50% tHZOE tHZCE HIGH IMPEDANCE ICC ISB Figure 5. Write Cycle No. 1 (WE Controlled, OE HIGH During tWC ADDRESS tSCE CE tAW tSA WE tPWE Write)[16, 17] tHA OE tSD DATA I/O NOTE 17 tHZOE Notes 13. Device is continuously selected. OE, CE = VIL. 14. WE is HIGH for read cycle. 15. Address valid prior to or coincident with CE transition LOW. 16. Data IO is high impedance if OE = VIH. 17. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state. tHD DATAIN VALID Document Number: 38-05475 Rev. *D Page 6 of 10 CY7C1049DV33 Switching Waveforms (continued) Figure 6. Write Cycle No. 2 (WE Controlled, OE LOW)[17] tWC ADDRESS tSCE CE tAW tSA WE tSD DATA I/O NOTE 18 tHZWE DATA VALID tPWE tHA tHD tLZWE Figure 7. Write Cycle No. 3 (CE Controlled)[16, 17] tWC ADDRESS tSCE CE tSA tAW tPWE WE tSD DATA I/O DATA VALID tHD tSCE tHA Note 18. During this period the IOs are in the output state and input signals must not be applied. Document Number: 38-05475 Rev. *D Page 7 of 10 CY7C1049DV33 Truth Table CE H L L L OE X L X H WE X H L H IO0–IO7 High Z Data Out Data In High Z Power down Read Write Selected, Outputs Disabled Mode Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Ordering Information Speed (ns) 10 12 Ordering Code CY7C1049DV33-10VXI CY7C1049DV33-10ZSXI CY7C1049DV33-12VXE CY7C1049DV33-12ZSXE Package Name Package Type Operating Range Industrial Automotive 51-85090 36-pin (400-Mil) Molded SOJ (Pb-free) 51-85087 44-pin TSOP II (Pb-free) 51-85090 36-pin (400-Mil) Molded SOJ (Pb-free) 51-85087 44-pin TSOP II (Pb-free) Contact your local Cypress sales representative for availability of these parts. Package Diagrams Figure 8. 36-Pin (400-Mil) Molded SOJ (51-85090) 5 1-85 090 -*C Document Number: 38-05475 Rev. *D Page 8 of 10 CY7C1049DV33 Package Diagrams (continued) Figure 9. 44-Pin Thin Small Outline Package Type II (51-85087) 51-85087-*A Document Number: 38-05475 Rev. *D Page 9 of 10 CY7C1049DV33 Document History Page Document Title: CY7C1049DV33, 4-Mbit (512K x 8) Static RAM Document Number: 38-05475 REV. ** *A *B ECN NO. 201560 233729 351096 Issue Date See ECN See ECN See ECN Orig. of Change SWI SYT PCI Description of Change Advance Datasheet for C9 IPP 1.AC, DC parameters are modified as per EROS (Specification # 01-2165) 2.Pb-free offering in the Ordering Information Table Changed from Advance to Preliminary Removed 20 ns Speed bin Corrected DC voltage (min) value in maximum ratings section from - 0.5 to - 0.3V Redefined ICC values for Com’l and Ind’l temperature ranges ICC (Com’l): Changed from 100, 80, and 67 mA to 90, 80 and, 75 mA for 8, 10, and 12ns speed bins respectively ICC (Ind’l): Changed from 80 and 67 mA to 90 and 85 mA for 10 and 12ns speed bins respectively Added VIH(max) specification in Note# 2 Changed reference voltage level for measurement of High Z parameters from ±500 mV to ±200 mV Added Data Retention Characteristics, Waveform, and footnotes 11 and 12 Changed Package Diagram name from 44-pin TSOP II Z44 to 44-pin TSOP II ZS44 Changed part names from Z to ZS in the Ordering Information Table Added 8 ns parts in the Ordering Information Table Added Pb-free Ordering Information Shaded Ordering Information Table Converted from Preliminary to Final Removed -8 speed bin Removed Commercial Operating Range product information Added Automotive Operating Range product information Updated Thermal Resistance table Updated footnote #8 on High Z parameter measurement Replaced Package Name column with Package Diagram in the Ordering Information table *C 446328 See ECN NXR *D 1274726 See ECN VKN/AESA Corrected typo in the 44-Pin TSOP II pinout © Cypress Semiconductor Corporation, 2004-2007. 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Document Number: 38-05475 Rev. *D Revised July 23, 2007 Page 10 of 10 All products and company names mentioned in this document may be the trademarks of their respective holders.