CY7C1049D_11

CY7C1049D 4-Mbit (512 K × 8) Static RAM Features ■ ■ Functional Description[1] The CY7C1049D is a high-performance CMOS static RAM organized as 512K words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE), and tri-state drivers. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A18). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE LOW, and WE LOW). The CY7C1049D is available in a standard 400-mil-wide 36-pin SOJ package with center power and ground (revolutionary) pinout. Pin- and function-compatible with CY7C1049B High speed ❐ tAA = 10 ns Low active power ❐ ICC = 90 mA at 10 ns Low CMOS Standby power ❐ ISB2 = 10 mA 2.0 V data retention Automatic power-down when deselected TTL-compatible inputs and outputs Easy memory expansion with CE and OE features Available in Pb-free 36-Pin (400-Mil) Molded SOJ package ■ ■ ■ ■ ■ ■ ■ Logic Block Diagram I/O0 INPUT BUFFER A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 I/O1 ROW DECODER I/O2 SENSE AMPS 512K x 8 I/O3 I/O4 I/O5 CE WE OE COLUMN DECODER POWER DOWN I/O6 I/O7 Selection Guide –10 Maximum access time Maximum operating current Maximum CMOS standby current 10 90 10 Unit ns mA mA Note 1. For guidelines on SRAM system design, refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com. A 11 A 12 A 13 A14 A15 A16 A17 A18 Cypress Semiconductor Corporation Document #: 38-05474 Rev. *E • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised April 20, 2011 [+] Feedback CY7C1049D Contents Pin Configuration ............................................................. 3 Maximum Ratings ............................................................. 3 Operating Range ............................................................... 3 Electrical Characteristics Over the Operating Range ............................................... 3 Capacitance ...................................................................... 4 Thermal Resistance .......................................................... 4 AC Test Loads and Waveforms ....................................... 4 Switching Characteristics Over the Operating Range ............................................... 5 Data Retention Characteristics Over the Operating Range ............................................... 5 Data Retention Waveform ................................................ 6 Switching Waveforms ...................................................... 6 Truth Table ........................................................................ 9 Ordering Information ........................................................ 9 Ordering Code Definitions ........................................... 9 Package Diagram ............................................................ 10 Acronyms ........................................................................ 10 Document Conventions ................................................. 10 Units of Measure ....................................................... 10 Document History Page ................................................. 11 Sales, Solutions, and Legal Information ...................... 12 Worldwide Sales and Design Support ....................... 12 Products .................................................................... 12 PSoC Solutions ......................................................... 12 Document #: 38-05474 Rev. *E Page 2 of 12 [+] Feedback CY7C1049D Pin Configuration SOJ Top View A0 A1 A2 A3 A4 CE I/O0 I/O1 VCC GND I/O2 I/O3 WE A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 NC A18 A17 A16 A15 OE I/O7 I/O6 GND VCC I/O5 I/O4 A14 A13 A12 A11 A10 NC Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied ............................................ –55°C to +125°C Supply Voltage on VCC to Relative GND[2] ...–0.5 V to +6.0 V DC Voltage Applied to Outputs in High Z State[2] .................................. –0.5 V to VCC + 0.5 V DC Input Voltage[2] .............................. –0.5 V to VCC + 0.5 V Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage........................................... >2001 V (per MIL-STD-883, Method 3015) Latch-Up Current ..................................................... >200 mA Operating Range Range Industrial Ambient Temperature –40°C to +85°C VCC 4.5 V–5.5 V Electrical Characteristics Over the Operating Range Parameter VOH VOL VIH[2] VIL[2] IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[2] Input Leakage Current Output Leakage Current VCC Operating Supply Current Test Conditions VCC = Min., IOH = –4.0 mA VCC = Min., IOL = 8.0 mA –10 Min. 2.4 – 2.0 –0.5 –1 –1 100 MHz 83 MHz 66 MHz 40 MHz ISB1 ISB2 Automatic CE Power-Down Current —TTL Inputs Automatic CE Power-Down Current —CMOS Inputs Max. VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fMAX Max. VCC, CE > VCC – 0.3 V, VIN > VCC – 0.3 V, or VIN < 0.3 V, f = 0 – – – – – – – – – – Max. – 0.4 VCC + 0.5 0.8 +1 +1 90 80 70 60 20 10 Unit V V V V μA μA mA mA mA mA mA mA GND < VI < VCC GND < VOUT < VCC, Output Disabled VCC = Max., f = fMAX = 1/tRC Document #: 38-05474 Rev. *E Page 3 of 12 [+] Feedback CY7C1049D Capacitance[3] Parameter CIN COUT Description Input capacitance I/O capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0 V Max. 8 8 Unit pF pF Thermal Resistance[3] Parameter ΘJA ΘJC Description Thermal resistance (Junction to Ambient)[3] Thermal resistance (Junction to Case)[3] Test Conditions Still Air, soldered on a 3 × 4.5 inch, four-layer printed circuit board SOJ Package 57.91 36.73 Unit °C/W °C/W AC Test Loads and Waveforms[4] 10-ns device OUTPUT 50 Ω * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT 1.5 V Z = 50Ω 3.0 V ALL INPUT PULSES 30 pF* GND ≤ 3 ns 90% 10% 90% 10% ≤ 3 ns (a) HIGH-Z CHARACTERISTICS R1 481Ω 5V OUTPUT 5 pF INCLUDING JIG AND SCOPE (c) R2 255Ω Equivalent to: (b) THÉVENIN EQUIVALENT 167Ω 1.73 V OUTPUT Notes 2. Minimum voltage is –2.0 V and VIH(max) = VCC + 2 V for pulse durations of less than 20 ns. 3. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05474 Rev. *E Page 4 of 12 [+] Feedback CY7C1049D Switching Characteristics[5] Over the Operating Range -10 Parameter Read Cycle tpower tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD Write Cycle[9, 10] tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low Z[8] WE LOW to High Z[7, 8] 10 7 7 0 0 7 6 0 3 – – – – – – – – – – 5 ns ns ns ns ns ns ns ns ns ns VCC(typical) to the First Access[6] Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low CE LOW to Low Z[8] Z[8] OE HIGH to High Z[7, 8] CE HIGH to High Z[7, 8] CE LOW to Power-Up CE HIGH to Power-Down 100 10 – 3 – – 0 – 3 – 0 – – – 10 – 10 5 – 5 – 5 – 10 μs ns ns ns ns ns ns ns ns ns ns ns Description Min. Max. Unit Data Retention Characteristics Over the Operating Range Parameter VDR ICCDR tCDR [3] Description VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time Conditions[12] VCC = VDR = 2.0 V, CE > VCC – 0.3 V VIN > VCC – 0.3 V or VIN < 0.3 V Min. 2.0 – 0 tRC Max – 10 – – Unit V mA ns ns tR[11] Notes 4. AC characteristics (except High-Z) for 10-ns parts are tested using the load conditions shown in Figure (a). High-Z characteristics are tested for all speeds using the test load shown in Figure (c) 5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 6. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed. 7. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (c) of AC Test Loads. Transition is measured when the outputs enter a high impedance state. 8. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 9. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 10. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document #: 38-05474 Rev. *E Page 5 of 12 [+] Feedback CY7C1049D Data Retention Waveform DATA RETENTION MODE VCC 4.5 V tCDR CE VDR > 2 V 4.5 V tR Switching Waveforms Figure 1. Read Cycle No. 1[13, 14] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Notes 11. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 50 μs or stable at VCC(min.) > 50 μs 12. No input may exceed VCC + 0.5 V. 13. Device is continuously selected. OE, CE = VIL. 14. WE is HIGH for read cycle. Document #: 38-05474 Rev. *E Page 6 of 12 [+] Feedback CY7C1049D Switching Waveforms(continued) Figure 2. Read Cycle No. 2 (OE Controlled)[14, 15] ADDRESS tRC CE tACE OE tDOE DATA OUT VCC SUPPLY CURRENT tLZOE HIGH IMPEDANCE tLZCE tPU 50% tHZOE tHZCE DATA VALID tPD 50% ISB ICC HIGH IMPEDANCE Figure 3. Write Cycle No. 1 (CE Controlled)[16, 17] tWC ADDRESS tSCE CE tSA tSCE tAW tPWE WE tSD DATA I/O DATA VALID tHD tHA Notes 15. Address valid prior to or coincident with CE transition LOW. 16. Data I/O is high impedance if OE = VIH. 17. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. Document #: 38-05474 Rev. *E Page 7 of 12 [+] Feedback CY7C1049D Switching Waveforms(continued) Figure 4. Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[16, 17] tWC ADDRESS tSCE CE tAW tSA WE tPWE tHA OE tSD DATA I/O NOTE 18 tHZOE DATAIN VALID tHD Figure 5. Write Cycle No. 3 (WE Controlled, OE LOW)[17] tWC ADDRESS tSCE CE tAW tSA WE tSD DATA I/O NOTE 18 tHZWE DATA VALID tPWE tHA tHD tLZWE Document #: 38-05474 Rev. *E Page 8 of 12 [+] Feedback CY7C1049D m bngggggggg Truth Table CE H L L L OE X L X H WE X H L H I/O0–I/O7 High-Z Data Out Data In High-Z Power-down Read Write Selected, Outputs Disabled Mode Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Ordering Information Speed (ns) 10 Ordering Code CY7C1049D-10VXI Package Diagram 51-85090 Package Type 36-Lead (400-Mil) Molded SOJ (Pb-free) Operating Range Industrial Ordering Code Definitions CY 7 C 1 04 9 D - 10 VX I Temperature Range: I = Industrial Package Type: VX = 36-Lead Molded SOJ (Pb-free) Speed: 10 ns D = C9, 90 nm Technology 9 = Data width × 8-bits 04 = 4-Mbit density 1 = Fast Asynchronous SRAM family Technology Code: C = CMOS 7 = SRAM CY = Cypress Please contact your local Cypress sales representative for availability of these parts. Note 18. During this period the I/Os are in the output state and input signals should not be applied. Document #: 38-05474 Rev. *E Page 9 of 12 [+] Feedback CY7C1049D Package Diagram Figure 6. 36-Pin (400-Mil) Molded SOJ (51-85090) 51-85090 *E Acronyms Acronym CE CMOS I/O OE SRAM SOJ TSOP VFBGA chip enable Complementary metal oxide semiconductor Input/output output enable Static random access memory Small Outline J-Lead Thin Small Outline Package Very Fine-Pitch Ball Grid Array Description Document Conventions Units of Measure Symbol ns V µA mA mV mW MHz pF °C W nano seconds Volts micro Amperes milli Amperes milli Volts milli Watts Mega Hertz pico Farad degree Celcius Watts Unit of Measure Document #: 38-05474 Rev. *E Page 10 of 12 [+] Feedback CY7C1049D Document History Page Document Title: CY7C1049D 4-Mbit (512K x 8) Static RAM Document Number: 38-05474 Revision ** *A *B ECN 201560 233729 351096 Orig. of Change SWI RKF PCI Submission Date See ECN See ECN See ECN Description of Change Advance Datasheet for C9 IPP 1.AC, DC parameters are modified as per EROS(Spec # 01-2165) 2.Pb-free offering in the ‘ordering information’ Changed from Advance to Preliminary Removed 17, 20 ns Speed bin Added footnote # 4 Redefined ICC values for Com’l and Ind’l temperature ranges ICC (Com’l): Changed from 67 and 54 mA to 75 and 70 mA for 12 and 15 ns speed bins respectively ICC (Ind’l): Changed from 80, 67 and 54 mA to 90, 85 and 80 mA for 10, 12 and 15 ns speed bins respectively Added VIH(max) spec in Note# 2 Modified Note# 10 on tR Changed tSCE from 8 to 7 ns for 10 ns speed bin Changed reference voltage level for measurement of Hi-Z parameters from ±500 mV to ±200 mV Added Truth Table on page# 6 Removed L-Version Added 10 ns parts in the Ordering Information Table Added Lead-Free Product Information Shaded Ordering Information Table Converted from Preliminary to Final Removed -12 and -15 speed bins Removed Commercial Operating Range product information Changed Maximum Rating for supply voltage from 7 V to 6 V Updated Thermal Resistance table Changed tHZWE from 6 ns to 5 ns Updated footnote #7 on High-Z parameter measurement Replaced Package Name column with Package Diagram in the Ordering Information table *C 446328 NXR See ECN *D *E 3109184 3235742 AJU PRAS 12/13/2010 Added Ordering Code Definitions. Updated Package Diagram. 04/20/2011 Updated template. Added Acronyms and Units of measure. Document #: 38-05474 Rev. *E Page 11 of 12 [+] Feedback CY7C1049D Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5 © Cypress Semiconductor Corporation, 2004-2011. The information contained herein is subject to change without notice. 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Document #: 38-05474 Rev. *E Revised April 20, 2011 Page 12 of 12 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback