CY7C1049G
CY7C1049GE
4-Mbit (512K words × 8-bit) Static RAM
with Error-Correcting Code (ECC)
4-Mbit (512K words × 8-bit) Static RAM with Error-Correcting Code (ECC)
Features
■
■
■
offered in single and dual chip-enable options and in multiple pin
configurations. The CY7C1049GE device includes an ERR pin
that signals an error-detection and correction event during a read
cycle.
High speed
❐ tAA = 10 ns
Embedded ECC for single-bit error correction[1, 2]
Data writes are performed by asserting the Chip Enable (CE) and
Write Enable (WE) inputs LOW, while providing the data on I/O0
through I/O7 and address on A0 through A18 pins.
Low active and standby currents
❐ Active current: ICC = 38 mA typical
❐ Standby current: ISB2 = 6 mA typical
Data reads are performed by asserting the Chip Enable (CE) and
Output Enable (OE) inputs LOW and providing the required
address on the address lines. Read data is accessible on the I/O
lines (I/O0 through I/O7).
■
Operating voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V, and
4.5 V to 5.5 V
■
1.0-V data retention
■
TTL-compatible inputs and outputs
■
Error indication (ERR) pin to indicate 1-bit error detection and
correction
■
The device is deselected (CE HIGH)
■
The control signal OE is de-asserted
Pb-free 36-pin SOJ and 44-pin TSOP II packages
On the CY7C1049GE devices, the detection and correction of a
single-bit error in the accessed location is indicated by the
assertion of the ERR output (ERR = HIGH)[1]. See the Truth
Table on page 14 for a complete description of read and write
modes.
■
All I/Os (I/O0 through I/O7) are placed in a high-impedance state
during the following events:
Functional Description
CY7C1049G and CY7C1049GE are high-performance CMOS
fast static RAM devices with embedded ECC. Both devices are
The logic block diagram is on page 2.
Product Portfolio
Power Dissipation
Product[3]
Features and Options (see Pin
Configurations on page 4)
CY7C1049G(E)18 Single or Dual Chip Enables
CY7C1049G(E)30
CY7C1049G(E)
Optional ERR pins
Range
Industrial
VCC Range
(V)
Speed
(ns)
Operating ICC,
(mA)
f = fmax
10/15
Standby, ISB2
(mA)
Typ[4]
Max
Typ[4]
Max
6
8
1.65 V–2.2 V
15
–
40
2.2 V–3.6 V
10
38
45
4.5 V–5.5 V
10
38
45
Notes
1. This device does not support automatic write-back on error detection.
2. SER FIT Rate 2001 V
Latch-up current .................................................... > 140 mA
Operating Range
Supply voltage
on VCC relative to GND [8] ..................... –0.5 to VCC + 0.5 V
DC voltage applied to outputs
in HI-Z State [8] ................................... –0.5 V to VCC + 0.5 V
Grade
Industrial
Ambient Temperature
–40 C to +85 C
VCC
1.65 V to 2.2 V,
2.2 V to 3.6 V,
4.5 V to 5.5 V
DC Electrical Characteristics
Over the operating range of –40 C to 85 C
Parameter
VOH
VOL
VIH
VIL
Description
Output HIGH
voltage
Output LOW
voltage
Input HIGH
voltage
Input LOW
voltage
Test Conditions
1.65 V to 2.2 V VCC = Min, IOH = –0.1 mA
10 ns / 15 ns
Min
Typ [9]
Max
1.4
–
–
2.2 V to 2.7 V
VCC = Min, IOH = –1.0 mA
2
–
–
2.7 V to 3.0 V
VCC = Min, IOH = –4.0 mA
2.2
–
–
3.0 V to 3.6 V
VCC = Min, IOH = –4.0 mA
2.4
–
–
4.5 V to 5.5 V
VCC = Min, IOH = –4.0 mA
2.4
–
–
4.5 V to 5.5 V
VCC = Min, IOH = –0.1mA
VCC – 0.5[10]
–
–
1.65 V to 2.2 V VCC = Min, IOL = 0.1 mA
V
–
–
0.2
2.2 V to 2.7 V
VCC = Min, IOL = 2 mA
–
–
0.4
2.7 V to 3.6 V
VCC = Min, IOL = 8 mA
–
–
0.4
4.5 V to 5.5 V
VCC = Min, IOL = 8 mA
1.65 V to 2.2 V –
–
–
0.4
1.4
–
VCC + 0.2[8]
0.3[8]
2.2 V to 2.7 V
–
2
–
VCC +
2.7 V to 3.6 V
–
2
–
VCC + 0.3[8]
4.5 V to 5.5 V
–
2
–
VCC + 0.5[8]
1.65 V to 2.2 V –
–0.2[8]
–
0.4
2.2 V to 2.7 V
–
–0.3[8]
–
0.6
2.7 V to 3.6 V
–
–0.3[8]
–
0.8
–
–0.5[8]
4.5 V to 5.5 V
Unit
V
V
V
–
0.8
IIX
Input leakage current
GND < VIN < VCC
–1
–
+1
A
IOZ
Output leakage current
GND < VOUT < VCC, Output disabled
–1
–
+1
A
ICC
Operating supply current
Max VCC, IOUT = 0 mA, f = 100 MHz
CMOS levels
f = 66.7 MHz
–
38
45
mA
–
–
40
ISB1
Automatic CE power-down
current – TTL inputs
Max VCC, CE > VIH,
VIN > VIH or VIN < VIL, f = fMAX
–
–
15
mA
ISB2
Automatic CE power-down
current – CMOS inputs
Max VCC, CE > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V, f = 0
–
6
8
mA
Notes
8. VIL(min) = –2.0 V and VIH(max) = VCC + 2 V for pulse durations of less than 20 ns.
9. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = 1.8 V (for VCC range of 1.65 V – 2.2 V),
VCC = 3 V (for VCC range of 2.2V – 3.6 V), and VCC = 5 V (for VCC range of 4.5 V – 5.5 V), TA = 25 °C.
10. This parameter is guaranteed by design and not tested.
Document Number: 001-95412 Rev. *F
Page 6 of 19
CY7C1049G
CY7C1049GE
Capacitance
Parameter [11]
Description
CIN
Input capacitance
COUT
I/O capacitance
Test Conditions
36-pin SOJ
TA = 25 C, f = 1 MHz,
VCC = VCC(typ)
44-pin TSOP II Unit
10
10
pF
10
10
pF
Thermal Resistance
Parameter [11]
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
Test Conditions
36-pin SOJ
Still air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
44-pin TSOP II Unit
59.52
68.85
C/W
31.48
15.97
C/W
AC Test Loads and Waveforms
Figure 4. AC Test Loads and Waveforms [12]
High-Z Characteristics:
VCC
50
Output
VTH
Z0 = 50
R1
Output
30 pF*
* Including
jig and
scope
(a)
* Capacitive load consists
of all components of the
test environment
(b)
All Input Pulses
VHIGH
GND
R2
5 pF*
90%
90%
10%
Rise Time:
> 1 V/ns
10%
Fall Time:
> 1 V/ns
(c)
Parameters
1.8 V
3.0 V
5.0 V
Unit
R1
1667
317
317
R2
1538
351
351
VTH
0.9
1.5
1.5
V
VHIGH
1.8
3
3
V
Notes
11. Tested initially and after any design or process changes that may affect these parameters.
12. Full-device AC operation assumes a 100-µs ramp time from 0 to VCC(min) and a 100-µs wait time after VCC stabilization.
Document Number: 001-95412 Rev. *F
Page 7 of 19
CY7C1049G
CY7C1049GE
Data Retention Characteristics
Over the operating range of –40 C to 85 C
Parameter
VDR
Description
Conditions
Min
Max
Unit
1
–
V
–
8
mA
0
–
ns
VCC > 2.2 V
10
–
ns
VCC < 2.2 V
15
–
ns
VCC for data retention
[14]
ICCDR
Data retention current
tCDR[13]
Chip deselect to data retention
time
tR[13, 14]
Operation recovery time
VCC = 1.2 V, CE > VCC – 0.2 V ,
VIN > VCC – 0.2 V, or VIN < 0.2 V
Data Retention Waveform
Figure 5. Data Retention Waveform[14]
VCC
VCC(min)
DATA RETENTION MODE
VDR = 1.0 V
tCDR
VCC(min)
tR
CE
Notes
13. These parameters are guaranteed by design.
14. Full-device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC (min) > 100 s.
Document Number: 001-95412 Rev. *F
Page 8 of 19
CY7C1049G
CY7C1049GE
AC Switching Characteristics
Over the operating range of –40 C to 85 C
Parameter [15]
Description
10 ns
15 ns
Min
Max
Min
Max
Unit
Read Cycle
tRC
Read cycle time
10
–
15
–
ns
tAA
Address to data / ERR valid
–
10
–
15
ns
tOHA
Data / ERR hold from address change
3
–
3
–
ns
tACE
CE LOW to data / ERR valid
–
10
–
15
ns
tDOE
OE LOW to data / ERR valid
–
4.5
–
8
ns
0
–
0
–
ns
–
5
–
8
ns
3
–
3
–
ns
–
5
–
8
ns
CE LOW to
power-up[17, 18]
0
–
0
–
ns
CE HIGH to
power-down[17, 18]
–
10
–
15
ns
tLZOE
tHZOE
OE LOW to low impedance
OE HIGH to
HI-Z[16]
impedance[16]
tLZCE
CE LOW to low
tHZCE
CE HIGH to HI-Z[16]
tPU
tPD
Write Cycle
[16]
[18, 19]
tWC
Write cycle time
10
–
15
–
ns
tSCE
CE LOW to write end
7
–
12
–
ns
tAW
Address setup to write end
7
–
12
–
ns
tHA
Address hold from write end
0
–
0
–
ns
tSA
Address setup to write start
0
–
0
–
ns
tPWE
WE pulse width
7
–
12
–
ns
tSD
Data setup to write end
5
–
8
–
ns
tHD
Data hold from write end
0
–
0
–
ns
tLZWE
WE HIGH to low impedance[16]
3
–
3
–
ns
–
5
–
8
ns
tHZWE
[16]
WE LOW to HI-Z
Notes
15. Test conditions assume a signal transition time (rise/fall) of 3 ns or less, timing reference levels of 1.5 V (for VCC > 3 V) and VCC/2 (for VCC < 3 V), and input pulse
levels of 0 to 3 V (for VCC > 3 V) and 0 to VCC (for VCC < 3 V). Test conditions for the read cycle use output loading, as shown in part (a) of Figure 4 on page 7, unless specified otherwise.
16. tHZOE, tHZCE, tHZWE, tLZOE, tLZCE, and tLZWE are specified with a load capacitance of 5 pF, as shown in part (b) of Figure 4 on page 7. Transition is measured 200 mV from steady state
voltage.
17. These parameters are guaranteed by design and are not tested.
18. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL. These signals must be LOW to initiate a write, and the HIGH transition of any
of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates the write.
19. The minimum write cycle pulse width in Write Cycle No. 2 (WE Controlled, OE LOW) should be equal to sum of tDS and tHZWE.
Document Number: 001-95412 Rev. *F
Page 9 of 19
CY7C1049G
CY7C1049GE
Switching Waveforms
Figure 6. Read Cycle No. 1 of CY7C1049G (Address Transition Controlled) [20, 21]
tRC
ADDRESS
tAA
tOHA
DATA I/O
PREVIOUS DATAOUT
VALID
DATAOUT VALID
Figure 7. Read Cycle No. 1 of CY7C1049GE (Address Transition Controlled) [20, 21]
tRC
ADDRESS
tAA
tOHA
DATA I/O
PREVIOUS DATAOUT
VALID
DATAOUT VALID
tAA
tOHA
ERR
PREVIOUS ERR VALID
ERR VALID
Notes
20. The device is continuously selected, OE = VIL, CE = VIL.
21. WE is HIGH for the read cycle.
Document Number: 001-95412 Rev. *F
Page 10 of 19
CY7C1049G
CY7C1049GE
Switching Waveforms (continued)
Figure 8. Read Cycle No. 2 (OE Controlled) [22, 23]
ADDRESS
tRC
CE
tPD
tHZCE
tACE
OE
t HZOE
tDOE
tLZOE
BHE/
BLE
tDBE
tLZBE
DATA I/O
HIGH IMPEDANCE
t HZBE
DATAOUT VALID
HIGH
IMPEDANCE
tLZCE
tPU
VCC
SUPPLY
CURRENT
ISB
Notes
22. WE is HIGH for the read cycle.
23. Address valid prior to or coincident with CE LOW transition.
Document Number: 001-95412 Rev. *F
Page 11 of 19
CY7C1049G
CY7C1049GE
Switching Waveforms (continued)
Figure 9. Write Cycle No. 1 (CE Controlled) [24, 25]
tW
C
ADDRESS
tS A
tSC E
CE
tA W
tPW
tH A
E
W E
tB W
B H E/
BLE
O E
tHZOE
tH D
tS D
D A T A I /O
D A T AI N
V A L ID
Figure 10. Write Cycle No. 2 (WE Controlled, OE LOW) [24, 25, 26]
tW C
ADDRESS
tSCE
CE
tB W
BHE /
BLE
tS A
tA W
tH A
tPW E
WE
t LZ W E
t HZW E
D A T A I /O
tS D
DATA
tH D
IN
V A L ID
Notes
24. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL. These signals must be LOW to initiate a write, and the HIGH transition of any
of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates the write.
25. Data I/O is in HI-Z state if CE = VIH, or OE = VIH.
26. The minimum write cycle pulse width should be equal to sum of tSD and tHZWE.
Document Number: 001-95412 Rev. *F
Page 12 of 19
CY7C1049G
CY7C1049GE
Switching Waveforms (continued)
Figure 11. Write Cycle No. 3 (WE Controlled) [27, 28, 29]
tWC
ADDRESS
tSCE
CE1
CE2
tAW
tHA
tSA
WE
tPWE
tBW
BHE/BLE
OE
tHD
tSD
DATA I/O
NOTE 30
DATA IN VALID
tHZOE
Notes
27. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL. These signals must be LOW to initiate a write, and the HIGH transition of any
of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates the write.
28. Data I/O is in HI-Z state if CE = VIH, or OE = VIH.
29. Data I/O is high impedance if OE = VIH.
30. During this period the I/Os are in output state. Do not apply input signals.
Document Number: 001-95412 Rev. *F
Page 13 of 19
CY7C1049G
CY7C1049GE
Truth Table
CE
OE
[31]
H
X
WE
I/O0–I/O7
Mode
Power
[31]
HI-Z
Power down
Standby (ISB)
X
L
L
H
Data out
Read all bits
Active (ICC)
L
X
L
Data in
Write all bits
Active (ICC)
L
H
H
HI-Z
Selected, outputs disabled
Active (ICC)
ERR Output – CY7C1049GE
Output [32]
0
1
HI-Z
Mode
Read operation, no single-bit error in the stored data.
Read operation, single-bit error detected and corrected.
Device deselected or outputs disabled or Write operation.
Notes
31. The input voltage levels on these pins should be either at VIH or VIL.
32. ERR pin is an output pin. It should be left floating when not used.
Document Number: 001-95412 Rev. *F
Page 14 of 19
CY7C1049G
CY7C1049GE
Ordering Information
Speed
(ns)
10
15
Voltage
Range
Package
Diagram
Ordering Code
2.2 V–3.6 V CY7C1049G30-10VXI
51-85090 36-pin Molded SOJ
CY7C1049G30-10VXIT
51-85090 36-pin Molded SOJ, Tape and Reel
CY7C1049GE30-10ZSXI
51-85087 44-pin TSOP II, ERR output
CY7C1049GE30-10ZSXIT
51-85087 44-pin TSOP II, ERR output, Tape and Reel
CY7C1049G30-10ZSXI
51-85087 44-pin TSOP II
CY7C1049G30-10ZSXIT
51-85087 44-pin TSOP II, Tape and Reel
1.65 V–2.2 V CY7C1049G18-15ZSXI
Operating
Range
Industrial
51-85087 44-pin TSOP II
CY7C1049G18-15ZSXIT
10
Package Type (all Pb-free)
51-85087 44-pin TSOP II, Tape and Reel
4.5 V–5.5 V CY7C1049G-10VXI
51-85090 36-pin Molded SOJ
CY7C1049G-10VXIT
51-85090 36-pin Molded SOJ, Tape and Reel
CY7C1049G-10ZSXI
51-85087 44-pin TSOP II
CY7C1049G-10ZSXIT
51-85087 44-pin TSOP II, Tape and Reel
Ordering Code Definitions
CY 7 C 1 04 9
G
X
XX - XX XX X
I
X
X = blank or T
blank = Bulk; T = Tape and Reel
Temperature Range: I = Industrial
Pb-free
Package Type: XX = V or ZS
V= 36-pin Molded SOJ; ZS = 44-pin TSOP II
Speed: XX = 10 ns or 15 ns
Voltage Range: XX = 30 or 18 or blank
30 = 2.2 V–3.6 V; 18 = 1.65 V–2.2 V; no character = 4.5 V–5.5 V
X = blank or E
blank = without ERR output;
E = with ERR output Single bit error indication
Process Technology: G = 65 nm
Data Width: 9 = × 8-bits
Density: 04 = 4-Mbit
Family Code: 1 = Fast Asynchronous SRAM family
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 001-95412 Rev. *F
Page 15 of 19
CY7C1049G
CY7C1049GE
Package Diagrams
Figure 12. 44-pin TSOP II Package Outline, 51-85087
51-85087 *E
Figure 13. 36-pin SOJ V36.4 (Molded) Package Outline, 51-85090
51-85090 *G
Document Number: 001-95412 Rev. *F
Page 16 of 19
CY7C1049G
CY7C1049GE
Acronyms
Acronym
Document Conventions
Description
Units of Measure
BHE
Byte High Enable
BLE
Byte Low Enable
°C
degrees Celsius
CE
Chip Enable
MHz
megahertz
CMOS
Complementary Metal Oxide Semiconductor
A
microampere
I/O
Input/Output
s
microsecond
OE
Output Enable
mA
milliampere
SRAM
Static Random Access Memory
mm
millimeter
TSOP
Thin Small Outline Package
ns
nanosecond
TTL
Transistor-Transistor Logic
ohm
VFBGA
Very Fine-Pitch Ball Grid Array
%
percent
WE
Write Enable
pF
picofarad
V
volt
W
watt
Document Number: 001-95412 Rev. *F
Symbol
Unit of Measure
Page 17 of 19
CY7C1049G
CY7C1049GE
Document History Page
Document Title: CY7C1049G/CY7C1049GE, 4-Mbit (512K words × 8-bit) Static RAM with Error-Correcting Code (ECC)
Document Number: 001-95412
Rev.
ECN No.
Orig. of
Change
Submission
Date
**
4685774
VINI
03/13/2015
New data sheet.
*A
4831087
NILE
07/10/2015
Updated Package Diagrams:
Added spec 51-85090 *G (Figure 13).
Removed spec 51-85082 *E.
Removed spec 51-85150 *H.
Description of Change
*B
4968879
NILE
10/16/2015
Fixed typo in bookmarks.
*C
5020573
VINI
11/25/2015
Changed status from Preliminary to Final.
Updated Pin Configurations:
Removed figure “36-pin SOJ Single Chip Enable with ERR CY7C1049GE”.
Updated Ordering Information:
Updated part numbers.
*D
5429076
NILE
09/07/2016
Updated Maximum Ratings:
Updated Note 8 (Replaced “2 ns” with “20 ns”).
Updated DC Electrical Characteristics:
Removed Operating Range “2.7 V to 3.6 V” and all values corresponding to
VOH parameter.
Included Operating Ranges “2.7 V to 3.0 V” and “3.0 V to 3.6 V” and all
values corresponding to VOH parameter.
Changed minimum value of VIH parameter from 2.2 V to 2 V corresponding
to Operating Range “4.5 V to 5.5 V”.
Updated Ordering Information:
Updated part numbers.
Updated to new template.
*E
5725349
AESATMP7
05/03/2017
Updated Cypress Logo and Copyright.
*F
6118848
NILE
04/03/2018
Updated Features:
Added Note 2 and referred the same note in “Embedded ECC for single-bit
error correction”.
Updated to new template.
Completing Sunset Review.
Document Number: 001-95412 Rev. *F
Page 18 of 19
CY7C1049G
CY7C1049GE
Sales, Solutions, and Legal Information
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© Cypress Semiconductor Corporation, 2015-2018. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
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product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 001-95412 Rev. *F
Revised April 3, 2018
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