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CY7C1049GN30-10ZSXI

CY7C1049GN30-10ZSXI

  • 厂商:

    CYPRESS(赛普拉斯)

  • 封装:

    TSOP44

  • 描述:

    IC SRAM 4MBIT PARALLEL 44TSOP II

  • 数据手册
  • 价格&库存
CY7C1049GN30-10ZSXI 数据手册
CY7C1049GN 4-Mbit (512K words × 8-bit) Static RAM 4-Mbit (512K words × 8-bit) Static RAM Features Functional Description ■ High speed ❐ tAA = 10 ns CY7C1049GN is a high-performance CMOS fast static RAM device organized as 512K words by 8-bits. ■ Low active and standby currents ❐ Active current: ICC = 38 mA typical ❐ Standby current: ISB2 = 6 mA typical Data writes are performed by asserting the Chip Enable (CE) and Write Enable (WE) inputs LOW, while providing the data on I/O0 through I/O7 and address on A0 through A18 pins. ■ Operating voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V, and 4.5 V to 5.5 V ■ 1.0 V data retention ■ TTL-compatible inputs and outputs ■ Pb-free 36-pin SOJ and 44-pin TSOP II packages Data reads are performed by asserting the Chip Enable (CE) and Output Enable (OE) inputs LOW and providing the required address on the address lines. Read data is accessible on the I/O lines (I/O0 through I/O7). All I/Os (I/O0 through I/O7) are placed in a high-impedance state during the following events: ■ The device is deselected (CE HIGH) ■ The control signal OE is de-asserted The logic block diagram is on page 2. Product Portfolio Product CY7C1049GN18 Range VCC Range (V) Industrial Power Dissipation Speed (ns) Operating ICC, (mA) 10/15 f = fmax Typ[1] Standby, ISB2 (mA) Max Typ[1] Max 6 8 1.65 V–2.2 V 15 – 40 CY7C1049GN30 2.2 V–3.6 V 10 38 45 CY7C1049GN 4.5 V–5.5 V 10 38 45 Note 1. Typical values are included only for reference and are not guaranteed or tested. Typical values are measured at VCC = 1.8 V (for a VCC range of 1.65 V–2.2 V), VCC = 3 V (for a VCC range of 2.2 V–3.6 V), and VCC = 5 V (for a VCC range of 4.5 V–5.5 V), TA = 25 °C. Cypress Semiconductor Corporation Document Number: 002-10613 Rev. *C • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised November 14, 2017 CY7C1049GN Logic Block Diagram – CY7C1049GN 512K x 8 RAM ARRAY SENSE  AMPLIFIERS A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 ROW DECODER INPUT BUFFER I/O0‐I/O7 A10 A11 A12 A13 A14 A15 A16 A17 A18 COLUMN  DECODER Document Number: 002-10613 Rev. *C WE OE CE Page 2 of 17 CY7C1049GN Contents Pin Configurations ........................................................... 4 Maximum Ratings ............................................................. 5 Operating Range ............................................................... 5 DC Electrical Characteristics .......................................... 5 Capacitance ...................................................................... 6 Thermal Resistance .......................................................... 6 AC Test Loads and Waveforms ....................................... 6 Data Retention Characteristics ....................................... 7 Data Retention Waveform ................................................ 7 AC Switching Characteristics ......................................... 8 Switching Waveforms ...................................................... 9 Truth Table ...................................................................... 12 Ordering Information ...................................................... 13 Ordering Code Definitions ......................................... 13 Document Number: 002-10613 Rev. *C Package Diagrams .......................................................... 14 Acronyms ........................................................................ 15 Document Conventions ................................................. 15 Units of Measure ....................................................... 15 Document History Page ................................................. 16 Sales, Solutions, and Legal Information ...................... 17 Worldwide Sales and Design Support ....................... 17 Products .................................................................... 17 PSoC® Solutions ...................................................... 17 Cypress Developer Community ................................. 17 Technical Support ..................................................... 17 Page 3 of 17 CY7C1049GN Pin Configurations Figure 1. 36-pin SOJ pinout [2] A0 A1 A2 A3 A4 CE I/O0 I/O1 VCC GND I/O2 I/O3 WE A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 SOJ 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 NC A18 A17 A16 A15 OE I/O7 I/O6 GND VCC I/O5 I/O4 A14 A13 A12 A11 A10 NC Figure 2. 44-pin TSOP II pinout, Single Chip Enable [2] NC NC A0 A1 A2 A3 A4 /CE I/O0 I/O1 VCC VSS I/O2 I/O3 /WE A5 A6 A7 A8 A9 NC NC 1 44 2 43 3 42 4 41 5 40 6 39 7 38 8 37 9 44-pin TSOP II 36 10 35 11 34 12 33 13 32 14 31 15 30 16 29 17 28 18 27 19 26 20 25 21 24 22 23 NC NC NC A18 A17 A16 A15 /OE I/O7 I/O6 VSS VCC I/O5 I/O4 A14 A13 A12 A11 A10 NC NC NC Note 2. NC pins are not connected internally to the die. Document Number: 002-10613 Rev. *C Page 4 of 17 CY7C1049GN DC input voltage [3] .............................. –0.5 V to VCC + 0.5 V Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage temperature ................................ –65 C to +150 C Ambient temperature with power applied ................................... –55 C to +125 C Current into outputs (in LOW state) ............................ 20 mA Static discharge voltage (MIL-STD-883, Method 3015) ................................. > 2001 V Latch-up current .................................................... > 140 mA Operating Range Supply voltage on VCC relative to GND [3] ..................... –0.5 to VCC + 0.5 V DC voltage applied to outputs in HI-Z State [3] ................................... –0.5 V to VCC + 0.5 V Grade Industrial Ambient Temperature –40 C to +85 C VCC 1.65 V to 2.2 V, 2.2 V to 3.6 V, 4.5 V to 5.5 V DC Electrical Characteristics Over the operating range of –40 C to 85 C Parameter VOH Description Output HIGH voltage 1.65 V to 2.2 V VCC = Min, IOH = –0.1 mA Output LOW voltage VIH VIL Input LOW voltage Typ [4] Max 1.4 – – VCC = Min, IOH = –1.0 mA 2 – – 2.7 V to 3.0 V VCC = Min, IOH = –4.0 mA 2.2 – – 3.0 V to 3.6 V VCC = Min, IOH = –4.0 mA 2.4 – – 4.5 V to 5.5 V VCC = Min, IOH = –4.0 mA 2.4 – – – – VCC = Min, IOH = –0.1mA VCC – 0.5[5] Unit V 1.65 V to 2.2 V VCC = Min, IOL = 0.1 mA – – 0.2 2.2 V to 2.7 V VCC = Min, IOL = 2 mA – – 0.4 2.7 V to 3.6 V VCC = Min, IOL = 8 mA – – 0.4 4.5 V to 5.5 V VCC = Min, IOL = 8 mA – – 0.4 1.4 – VCC + 0.2[3] 0.3[3] 1.65 V to 2.2 V – Input HIGH voltage 10 ns/15 ns Min 2.2 V to 2.7 V 4.5 V to 5.5 V VOL Test Conditions 2.2 V to 2.7 V – 2 – VCC + 2.7 V to 3.6 V – 2 – VCC + 0.3[3] 4.5 V to 5.5 V – 2 – VCC + 0.5[3] 1.65 V to 2.2 V – –0.2[3] – 0.4 2.2 V to 2.7 V – –0.3[3] – 0.6 2.7 V to 3.6 V – –0.3[3] – 0.8 4.5 V to 5.5 V – –0.5[3] – 0.8 – +1 V V V A IIX Input leakage current GND < VIN < VCC –1 IOZ Output leakage current GND < VOUT < VCC, Output disabled –1 – +1 A ICC Operating supply current Max VCC, IOUT = 0 mA, f = 100 MHz CMOS levels f = 66.7 MHz – 38 45 mA – – 40 ISB1 Automatic CE power-down current – TTL inputs Max VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fMAX – – 15 mA ISB2 Automatic CE power-down current – CMOS inputs Max VCC, CE > VCC – 0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V, f = 0 – 6 8 mA Notes 3. VIL(min) = –2.0 V and VIH(max) = VCC + 2 V for pulse durations of less than 20 ns. 4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = 1.8 V (for VCC range of 1.65 V – 2.2 V), VCC = 3 V (for VCC range of 2.2V – 3.6 V), and VCC = 5 V (for VCC range of 4.5 V – 5.5 V), TA = 25 °C. 5. This parameter is guaranteed by design and not tested. Document Number: 002-10613 Rev. *C Page 5 of 17 CY7C1049GN Capacitance Parameter [6] Description CIN Input capacitance COUT I/O capacitance Test Conditions 36-pin SOJ TA = 25 C, f = 1 MHz, VCC = VCC(typ) 44-pin TSOP II Unit 10 10 pF 10 10 pF Thermal Resistance Parameter [6] Description JA Thermal resistance (junction to ambient) JC Thermal resistance (junction to case) Test Conditions 36-pin SOJ Still air, soldered on a 3 × 4.5 inch, four-layer printed circuit board 44-pin TSOP II Unit 59.52 68.85 C/W 31.48 15.97 C/W AC Test Loads and Waveforms Figure 3. AC Test Loads and Waveforms [7] High-Z Characteristics: VCC 50  Output VTH Z0 = 50  R1 Output 30 pF* * Including jig and scope (a) * Capacitive load consists of all components of the test environment  (b) All Input Pulses VHIGH GND R2 5 pF* 90% 90% 10% Rise Time: > 1 V/ns 10% Fall Time: > 1 V/ns (c) Parameters 1.8 V 3.0 V 5.0 V Unit R1 1667 317 317  R2 1538 351 351  VTH 0.9 1.5 1.5 V VHIGH 1.8 3 3 V Notes 6. Tested initially and after any design or process changes that may affect these parameters. 7. Full-device AC operation assumes a 100-µs ramp time from 0 to VCC(min) and a 100-µs wait time after VCC stabilization. Document Number: 002-10613 Rev. *C Page 6 of 17 CY7C1049GN Data Retention Characteristics Over the operating range of –40 C to 85 C Parameter VDR Description Conditions Min Max Unit 1 – V – 8 mA 0 – ns VCC > 2.2 V 10 – ns VCC < 2.2 V 15 – ns VCC for data retention [8] ICCDR Data retention current tCDR[9] Chip deselect to data retention time tR[8, 9] Operation recovery time VCC = 1.2 V, CE > VCC – 0.2 V , VIN > VCC – 0.2 V, or VIN < 0.2 V Data Retention Waveform Figure 4. Data Retention Waveform [8] VCC VCC(min) DATA RETENTION MODE VDR = 1.0 V tCDR VCC(min) tR CE Notes 8. Full-device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC (min) > 100 s. 9. These parameters are guaranteed by design. Document Number: 002-10613 Rev. *C Page 7 of 17 CY7C1049GN AC Switching Characteristics Over the operating range of –40 C to 85 C Parameter [10] Description 10 ns 15 ns Min Max Min Max Unit Read Cycle tRC Read cycle time 10 – 15 – ns tAA Address to data – 10 – 15 ns tOHA Data hold from address change 3 – 3 – ns tACE CE LOW to data – 10 – 15 ns tDOE OE LOW to data – 4.5 – 8 ns 0 – 0 – ns – 5 – 8 ns 3 – 3 – ns – 5 – 8 ns 0 – 0 – ns – 10 – 15 ns tLZOE tHZOE OE LOW to low impedance OE HIGH to High-Z [11] tLZCE CE LOW to low impedance tHZCE CE HIGH to High-Z [11] tPU tPD Write Cycle [11] CE LOW to power-up [11] [12, 13] CE HIGH to power-down [12, 13] [13, 14] tWC Write cycle time 10 – 15 – ns tSCE CE LOW to write end 7 – 12 – ns tAW Address setup to write end 7 – 12 – ns tHA Address hold from write end 0 – 0 – ns tSA Address setup to write start 0 – 0 – ns tPWE WE pulse width 7 – 12 – ns tSD Data setup to write end 5 – 8 – ns tHD Data hold from write end 0 – 0 – ns tLZWE WE HIGH to low impedance [11] 3 – 3 – ns – 5 – 8 ns tHZWE WE LOW to High-Z [11] Notes 10. Test conditions assume a signal transition time (rise/fall) of 3 ns or less, timing reference levels of 1.5 V (for VCC > 3 V) and VCC/2 (for VCC < 3 V), and input pulse levels of 0 to 3 V (for VCC > 3 V) and 0 to VCC (for VCC < 3 V). Test conditions for the read cycle use output loading, as shown in part (a) of Figure 3 on page 6, unless specified otherwise. 11. tHZOE, tHZCE, tHZWE, tLZOE, tLZCE, and tLZWE are specified with a load capacitance of 5 pF, as shown in part (b) of Figure 3 on page 6. Transition is measured 200 mV from steady state voltage. 12. These parameters are guaranteed by design and are not tested. 13. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL. These signals must be LOW to initiate a write, and the HIGH transition of any of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates the write. 14. The minimum write cycle pulse width in Write Cycle No. 2 (WE Controlled, OE LOW) should be equal to sum of tDS and tHZWE. Document Number: 002-10613 Rev. *C Page 8 of 17 CY7C1049GN Switching Waveforms Figure 5. Read Cycle No. 1 (Address Transition Controlled) [15, 16] tRC ADDRESS tAA tOHA DATA I/O PREVIOUS DATAOUT VALID DATAOUT VALID Figure 6. Read Cycle No. 2 (OE Controlled) [15, 16] ADDRESS tRC CE tPD tHZCE tACE OE t HZOE tDOE tLZOE DATA I/O HIGH IMPEDANCE DATAOUT VALID HIGH IMPEDANCE tLZCE tPU VCC SUPPLY CURRENT ISB Notes 15. WE is HIGH for the read cycle. 16. Address valid prior to or coincident with CE LOW transition. Document Number: 002-10613 Rev. *C Page 9 of 17 CY7C1049GN Switching Waveforms (continued) Figure 7. Write Cycle No. 1 (CE Controlled) [17, 18] tW C ADDRESS tS A tSC E CE tA W tPW tH A E W E OE tHZOE tH D tS D D A T A I /O D A T AI N V A L I D Figure 8. Write Cycle No. 2 (WE Controlled, OE LOW) [17, 18, 19] tW C ADDRESS tSCE CE tS A tAW tH A tPW E WE t LZW E t HZW E D A T A I /O tS D DATA tH D IN V A L ID Notes 17. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL. These signals must be LOW to initiate a write, and the HIGH transition of any of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates the write. 18. Data I/O is in HI-Z state if CE = VIH, or OE = VIH. 19. The minimum write cycle pulse width should be equal to sum of tSD and tHZWE. Document Number: 002-10613 Rev. *C Page 10 of 17 CY7C1049GN Switching Waveforms (continued) Figure 9. Write Cycle No. 3 (WE Controlled) [20, 21, 22] tWC ADDRESS tSCE CE1 CE2 tAW tSA WE tHA tPWE OE tHD tSD DATA I/O NOTE 23 DATA IN VALID tHZOE Notes 20. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL. These signals must be LOW to initiate a write, and the HIGH transition of any of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates the write. 21. Data I/O is in HI-Z state if CE = VIH, or OE = VIH. 22. Data I/O is high impedance if OE = VIH. 23. During this period the I/Os are in output state. Do not apply input signals. Document Number: 002-10613 Rev. *C Page 11 of 17 CY7C1049GN Truth Table CE H OE [24] X WE I/O0–I/O7 Mode Power [24] HI-Z Power down Standby (ISB) X L L H Data out Read all bits Active (ICC) L X L Data in Write all bits Active (ICC) L H H HI-Z Selected, outputs disabled Active (ICC) Note 24. The input voltage levels on these pins should be either at VIH or VIL. Document Number: 002-10613 Rev. *C Page 12 of 17 CY7C1049GN Ordering Information Speed (ns) 10 Voltage Range Package Diagram Ordering Code 2.2 V–3.6 V CY7C1049GN30-10ZSXI Package Type (all Pb-free) 51-85087 44-pin TSOP II CY7C1049GN30-10ZSXIT 51-85087 44-pin TSOP II, Tape and Reel CY7C1049GN30-10VXI 51-85090 36-pin Molded SOJ CY7C1049GN30-10VXIT 51-85090 36-pin Molded SOJ, Tape and Reel 4.5 V–5.5 V CY7C1049GN-10VXI Operating Range Industrial 51-85090 36-pin Molded SOJ CY7C1049GN-10VXIT 51-85090 36-pin Molded SOJ, Tape and Reel Ordering Code Definitions CY 7 C 1 04 9 GN XX - XX XX X I X X = blank or T blank = Bulk; T = Tape and Reel Temperature Range: I = Industrial Pb-free Package Type: XX = ZS or V ZS = 44-pin TSOP II; V= 36-pin Molded SOJ Speed: XX = 10 ns Voltage Range: XX = 30 or blank 30 = 2.2 V–3.6 V; no character = 4.5 V–5.5 V Process Technology: GN = 65 nm Data Width: 9 = × 8-bits Density: 04 = 4-Mbit Family Code: 1 = Fast Asynchronous SRAM family Technology Code: C = CMOS Marketing Code: 7 = SRAM Company ID: CY = Cypress Document Number: 002-10613 Rev. *C Page 13 of 17 CY7C1049GN Package Diagrams Figure 10. 44-pin TSOP Z44-II Package Outline, 51-85087 51-85087 *E Figure 11. 36-pin SOJ V36.4 (Molded) Package Outline, 51-85090 51-85090 *G Document Number: 002-10613 Rev. *C Page 14 of 17 CY7C1049GN Acronyms Acronym Document Conventions Description Units of Measure BHE byte high enable BLE byte low enable °C Degrees Celsius CE chip enable MHz megahertz CMOS complementary metal oxide semiconductor A microamperes I/O input/output s microseconds OE output enable mA milliamperes SRAM static random access memory mm millimeter TSOP thin small outline package ns nanoseconds TTL transistor-transistor logic  ohms VFBGA very fine-pitch ball grid array % percent WE write enable pF picofarads V volts W watts Document Number: 002-10613 Rev. *C Symbol Unit of Measure Page 15 of 17 CY7C1049GN Document History Page Document Title: CY7C1049GN, 4-Mbit (512K words × 8-bit) Static RAM Document Number: 002-10613 Rev. ECN No. Orig. of Change Submission Date ** 5074703 NILE 01/06/2016 New data sheet. *A 5082587 NILE 01/12/2016 Updated Logic Block Diagram – CY7C1049GN. Updated Ordering Information: Updated part numbers. *B 5437570 NILE 09/15/2016 Updated DC Electrical Characteristics: Removed details of VOH parameter corresponding to “2.7 V to 3.6 V” and Test Condition “VCC = Min, IOH = –4.0 mA”. Added details of VOH parameter corresponding to “2.7 V to 3.0 V” and Test Condition “VCC = Min, IOH = –4.0 mA”. Added details of VOH parameter corresponding to “3.0 V to 3.6 V” and Test Condition “VCC = Min, IOH = –4.0 mA”. Changed minimum value of VIH parameter corresponding to “4.5 V to 5.5 V” from 2.2 V to 2 V. Updated Note 3 (Replaced “2 ns” with “20 ns”). Updated Ordering Information: Updated part numbers. Updated to new template. *C 5966829 NILE 11/14/2017 Updated Switching Waveforms: Updated Figure 6. Updated Figure 7. Updated Figure 8. Updated Figure 9. Updated to new template. Completing Sunset Review. Document Number: 002-10613 Rev. *C Description of Change Page 16 of 17 CY7C1049GN Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products ARM® Cortex® Microcontrollers Automotive cypress.com/arm cypress.com/automotive Clocks & Buffers Interface cypress.com/clocks cypress.com/interface Internet of Things Memory cypress.com/iot cypress.com/memory Microcontrollers cypress.com/mcu PSoC cypress.com/psoc Power Management ICs Cypress Developer Community Forums | WICED IOT Forums | Projects | Video | Blogs | Training | Components Technical Support cypress.com/support cypress.com/pmic Touch Sensing cypress.com/touch USB Controllers Wireless Connectivity PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 cypress.com/usb cypress.com/wireless © Cypress Semiconductor Corporation, 2016-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document, including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the Software is prohibited. TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. Document Number: 002-10613 Rev. *C Revised November 14, 2017 Page 17 of 17
CY7C1049GN30-10ZSXI 价格&库存

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