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CY7C1051H
8-Mbit (512K Words × 16-Bit) Static RAM
with Error-Correcting Code (ECC)
8-Mbit (512K Words × 16-Bit) Static RAM with Error-Correcting Code (ECC)
Features
Functional Description
■
High speed
❐ tAA = 10 ns
CY7C1051H is a high-performance CMOS fast static RAM
device with embedded ECC[1].
■
Embedded error-correcting code (ECC) for single-bit error
correction
■
Low active and standby currents
❐ ICC = 90-mA typical at 100 MHz
❐ ISB2 = 20-mA typical
■
Operating voltage range: 2.2 V to 3.6 V.
■
1.0-V data retention
To access device, assert the chip enable (CE) input LOW. To
perform data writes, assert the Write Enable (WE) input LOW,
and provide the data and address on the device data pins (I/O0
through I/O15) and address pins (A0 through A18) respectively.
The Byte High Enable (BHE) and Byte Low Enable (BLE) inputs
control byte writes, and write data on the corresponding I/O lines
to the memory location specified. BHE controls I/O8 through
I/O15 and BLE controls I/O0 through I/O7.
■
Transistor-transistor logic (TTL) compatible inputs and outputs
■
Available in Pb-free 44-pin TSOP II and Pb-free 48-ball FBGA
packages
To perform data reads, assert the Output Enable (OE) input and
provide the required address on the address lines. Read data is
accessible on I/O lines (I/O0 through I/O15). You can perform
byte accesses by asserting the required byte enable signal (BHE
or BLE) to read either the upper byte or the lower byte of data
from the specified address location.
All I/Os (I/O0 through I/O15) are placed in a high-impedance state
when the device is deselected (CE HIGH), or control signals are
de-asserted (OE, BLE, BHE).
See the Truth Table on page 13 for a complete description of
read and write modes.
The logic block diagrams are provided on page 2.
The CY7C1051H is available in 44-pin TSOP II package.
For a complete list of related documentation, click here.
Product Portfolio
Current Consumption
Product
Features and Options
(see Pin Configurations
on page 4)
CY7C1051H30 Single chip enables
Range
Industrial
Speed Operating ICC, (mA) Standby, I
SB2 (mA)
(ns)
f = fmax
VCC Range
(V)
2.2 V–3.6 V
10
Typ[2]
Max
Typ[2]
Max
90
110
20
30
Notes
1. This device does not support automatic write-back on error detection.
2. Typical values are included only for reference and are not guaranteed or tested. Typical values are measured at VCC = 3 V (for a VCC range of 2.2 V–3.6 V) TA = 25 °C.
Cypress Semiconductor Corporation
Document Number: 002-03314 Rev. *D
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised November 13, 2020
CY7C1051H
Logic Block Diagram – CY7C1051H
ECC DECODER
MEMORY
ARRAY
INPUT BUFFER
SENSE
AMPLIFIERS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
ROW DECODER
ECC ENCODER
I/O0‐I/O7
I/O8‐I/O15
A10
A11
A12
A13
A14
A15
A16
A17
A18
COLUMN DECODER
BHE
WE
OE
CE
BLE
Document Number: 002-03314 Rev. *D
Page 2 of 19
CY7C1051H
Contents
Pin Configurations ........................................................... 4
Maximum Ratings ............................................................. 5
Operating Range ............................................................... 5
DC Electrical Characteristics .......................................... 5
Capacitance ...................................................................... 6
Thermal Resistance .......................................................... 6
AC Test Loads and Waveforms ....................................... 6
Data Retention Characteristics ....................................... 7
Data Retention Waveform ................................................ 7
AC Switching Characteristics ......................................... 8
Switching Waveforms ...................................................... 9
Truth Table ...................................................................... 13
Ordering Information ...................................................... 14
Ordering Code Definitions ......................................... 14
Document Number: 002-03314 Rev. *D
Package Diagram ............................................................ 15
Acronyms ........................................................................ 17
Document Conventions ................................................. 17
Units of Measure ....................................................... 17
Document History Page ................................................. 18
Sales, Solutions, and Legal Information ...................... 19
Worldwide Sales and Design Support ....................... 19
Products .................................................................... 19
PSoC® Solutions ...................................................... 19
Cypress Developer Community ................................. 19
Technical Support ..................................................... 19
Page 3 of 19
CY7C1051H
Pin Configurations
Figure 1. 44-pin TSOP II pinout
A0
A1
A2
A3
A4
/C E
I/O 0
I/O 1
I/O 2
I/O 3
VCC
VSS
I/O 4
I/O 5
I/O 6
I/O 7
/W E
A5
A6
A7
A8
A9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
4 4 -p in T S O P II 3 6
35
34
33
32
31
30
29
28
27
26
25
24
23
A17
A 16
A15
/O E
/B H E
/B L E
I/O 1 5
I/O 1 4
I/O 1 3
I/O 1 2
VSS
VCC
I/O 1 1
I/O 1 0
I/O 9
I/O 8
A18
A14
A13
A12
A11
A10
Figure 2. 48-ball FBGA pinout (Top View)
Document Number: 002-03314 Rev. *D
1
2
3
4
5
6
BLE
OE
A0
A1
A2
NC
A
I/O8
BHE
A3
A4
CE
I/O0
B
I/O9
I/O10
A5
A6
I/O1
I/O2
C
VSS
I/O11
A17
A7
I/O3
VCC
D
VCC
I/O12
NC
A16
I/O4
VSS
E
I/O14
I/O13
A14
A15
I/O5
I/O6
F
I/O15
NC
A12
A13
WE
I/O7
G
A18
A8
A9
A10
A11
NC
H
Page 4 of 19
CY7C1051H
DC input voltage[3] .............................. –0.5 V to VCC + 0.5 V
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage temperature ................................ –65 C to +150 C
Ambient temperature
with power applied ................................... –55 C to +125 C
Supply voltage
on VCC relative to GND ...................... –0.5 V to VCC + 0.5 V
Current into outputs (LOW) ........................................ 20 mA
Static discharge voltage
(MIL-STD-883, Method 3015) ................................. > 2001 V
Latch-up current .................................................... > 140 mA
Operating Range
DC voltage applied to outputs
in High Z State[3] ................................. –0.5 V to VCC + 0.5 V
Grade
Ambient Temperature
VCC
Industrial
–40 C to +85 C
2.2 V to 3.6 V
DC Electrical Characteristics
Over the operating range of –40 C to 85 C
Parameter
VOH
VOL
VIH[3]
VIL[3]
Description
Output
HIGH
voltage
Test Conditions
Min
Typ [4]
Max
2.2 V to 2.7 V VCC = Min, IOH = –1.0 mA
2.0
–
–
2.7 V to 3.0 V VCC = Min, IOH = –4.0 mA
2.2
–
–
3.0 V to 3.6 V VCC = Min, IOH = –4.0 mA
2.4
–
–
–
–
0.4
–
–
0.4
Output LOW 2.2 V to 2.7 V VCC = Min, IOL = 2 mA
voltage
2.7 V to 3.6 V VCC = Min, IOL = 8 mA
Input HIGH 2.2 V to 2.7 V
voltage
2.7 V to 3.6 V
Input LOW
voltage
10 ns
2.0
–
VCC + 0.3
2.0
–
VCC + 0.3
2.2 V to 2.7 V
–0.3
–
0.6
2.7 V to 3.6 V
–0.3
–
0.8
Unit
V
V
V
V
IIX
Input leakage current
GND < VIN < VCC
–1.0
–
+1.0
A
IOZ
Output leakage current
GND < VOUT < VCC, Output disabled
–1.0
–
+1.0
A
ICC
Operating supply current
VCC = Max, IOUT = 0 mA,
–
90.0
110.0
mA
ISB1
Automatic CE power down Max VCC, CE > VIH [4],
current – TTL inputs
VIN > VIH or VIN < VIL, f = fMAX
–
–
40.0
mA
ISB2
Automatic CE power down Max VCC, CE > VCC – 0.2 V[5],
current – CMOS inputs
VIN > VCC – 0.2 V or VIN < 0.2 V, f = 0
–
20.0
30.0
mA
f = 100 MHz
CMOS levels
Notes
3. VIL(min) = –2.0 V and VIH(max) = VCC + 2 V for pulse durations of less than 20 ns.
4. Typical values are included only for reference and are not guaranteed or tested. Typical values are measured at VCC = 3 V (for a VCC range of 2.2 V–3.6 V), TA = 25 °C.
5. This parameter is guaranteed by design and is not tested.
Document Number: 002-03314 Rev. *D
Page 5 of 19
CY7C1051H
Capacitance
Parameter [6]
Description
CIN
Input capacitance
COUT
I/O capacitance
Test Conditions
44-pin TSOP II 48-ball VFBGA Unit
TA = 25 C, f = 1 MHz, VCC = VCC(typ)
10
10
pF
10
10
pF
Thermal Resistance
Parameter [6]
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
Test Conditions
44-pin TSOP II 48-ball VFBGA Unit
Still air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
66.93
31.50
C/W
13.09
15.75
C/W
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms [7]
High-Z Characteristics:
VCC
50
Output
VTH
Z0 = 50
Output
30 pF*
* Including
JIG and
Scope
90%
3.0 V
Unit
R1
317
R2
351
VTH
1.5
V
VHIGH
3
V
90%
10%
Rise Time:
> 1 V/ns
Parameters
(b)
All Input Pulses
VHIGH
GND
R2
5 pF*
(a)
* Capacitive load consists
of all components of the
test environment
R1
10%
(c)
Fall Time:
> 1 V/ns
Notes
6. Tested initially and after any design or process changes that may affect these parameters.
7. Full-device AC operation assumes a 100-µs ramp time from 0 to VCC(min) and 100-µs wait time after VCC stabilizes to its operational value.
Document Number: 002-03314 Rev. *D
Page 6 of 19
CY7C1051H
Data Retention Characteristics
Over the operating range of –40 C to 85 C
Parameter
VDR
Description
Conditions
VCC for data retention
–
[8]
Min
Max
Unit
1.0
–
V
ICCDR
Data retention current
VCC = VDR, CE > VCC – 0.2 V ,
VIN > VCC – 0.2 V or VIN < 0.2 V
–
30.0
mA
tCDR[8]
Chip deselect to data retention
time
–
0
–
ns
tR[8, 9]
Operation recovery time
VCC > 2.2 V
10.0
–
ns
Data Retention Waveform
Figure 4. Data Retention Waveform
VCC
VCC(min)
DATA RETENTION MODE
VDR = 1.0 V
tCDR
VCC(min)
tR
CE
Notes
8. This parameter is guaranteed by design and is not tested.
9. Full-device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s.
Document Number: 002-03314 Rev. *D
Page 7 of 19
CY7C1051H
AC Switching Characteristics
Over the operating range of –40 C to 85 C
Parameter [10]
Description
10 ns
Unit
Min
Max
–
µs
Read Cycle
tPOWER
VCC (stable) to the first access [11, 12]
100.0
tRC
Read cycle time
10.0
–
ns
tAA
Address to data valid
–
10.0
ns
tOHA
Data hold from address change
3.0
–
ns
tACE
CE LOW to data valid
–
10.0
ns
tDOE
OE LOW to data valid
–
5.0
ns
0
–
ns
–
5.0
ns
3.0
–
ns
–
5.0
ns
0
–
ns
[13, 14, 15]
tLZOE
OE LOW to low Z
tHZOE
OE HIGH to high Z [13, 14, 15]
tLZCE
CE LOW to low Z
13, 14, 15]
[13, 14, 15]
tHZCE
CE HIGH to high Z
tPU
CE LOW to power-up [12]
tPD
CE HIGH to power-down
tDBE
Byte enable to data valid
tLZBE
tHZBE
Byte enable to low Z
[12]
[13, 14]
Byte disable to high Z
[13, 14]
–
10.0
ns
–
5.0
ns
0
–
ns
–
6.0
ns
10.0
–
ns
Write Cycle [16, 17]
tWC
Write cycle time
tSCE
CE LOW to write end
7.0
–
ns
tAW
Address setup to write end
7.0
–
ns
tHA
Address hold from write end
0
–
ns
tSA
Address setup to write start
0
–
ns
tPWE
WE pulse width
7.0
–
ns
tSD
Data setup to write end
5.0
–
ns
tHD
Data hold from write end
0
–
ns
3.0
–
ns
–
5.0
ns
7.0
–
ns
WE HIGH to low Z
[13, 14, 15]
tHZWE
WE LOW to high Z
[13, 14, 15]
tBW
Byte Enable to write end
tLZWE
Notes
10. Test conditions assume signal transition time (rise/fall) of 3 ns or less, timing reference levels of 1.5 V (for VCC > 3 V) and VCC/2 (for VCC < 3 V), and input pulse levels
of 0 to 3 V (for VCC > 3 V) and 0 to VCC (for VCC < 3V). Test conditions for the read cycle use the output loading, shown in part (a) of Figure 3 on page 6, unless specified otherwise.
11. tPOWER gives the minimum amount of time that the power supply is at stable VCC until the first memory access is performed.
12. These parameters are guaranteed by design and are not tested.
13. tHZOE, tHZCE, tHZWE, and tHZBE are specified with a load capacitance of 5 pF, as shown in part (b) of Figure 3 on page 6. Hi-Z, Lo-Z transition is measured 200 mV from steady state
voltage.
14. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.
15. Tested initially and after any design or process changes that may affect these parameters.
16. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL, and BHE or BLE = VIL. These signals must be LOW to initiate a write, and the
HIGH transition of any of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates
the write.
17. The minimum write pulse width for Write Cycle No. 2 (WE Controlled, OE LOW) should be sum of tHZWE and tSD.
Document Number: 002-03314 Rev. *D
Page 8 of 19
CY7C1051H
Switching Waveforms
Figure 5. Read Cycle No. 1 of CY7C1051H (Address Transition Controlled) [18, 19]
tRC
ADDRESS
tAA
tOHA
PREVIOUS DATAOUT
VALID
DATA I/O
DATAOUT VALID
Figure 6. Read Cycle No. 2 (OE Controlled) [19, 20]
ADDRESS
tRC
CE
tPD
tHZCE
tACE
OE
tHZOE
tDOE
tLZOE
BHE/
BLE
tDBE
tLZBE
DATA I/O
HIGH IMPEDANCE
tHZBE
HIGH
IMPEDANCE
DATAOUT VALID
tLZCE
VCC
SUPPLY
CURRENT
tPU
ICC
ISB
Notes
18. The device is continuously selected, OE = VIL, CE = VIL, BHE or BLE or both = VIL.
19. WE is HIGH for read cycle.
20. Address valid prior to or coincident with CE LOW transition.
Document Number: 002-03314 Rev. *D
Page 9 of 19
CY7C1051H
Switching Waveforms (continued)
Figure 7. Write Cycle No. 1 (CE Controlled) [21, 22]
tW C
ADDRESS
t SA
tSCE
CE
tAW
tHA
tPW E
WE
tBW
BHE/
BLE
OE
tHZOE
DATA I/O
t HD
tSD
Note 24
DATA IN VALID
Figure 8. Write Cycle No. 2 (WE Controlled, OE LOW) [21, 22, 23]
tWC
ADDRESS
tSCE
CE
tBW
BHE/
BLE
tSA
tAW
tHA
tPWE
WE
tHZWE
DATA I/O
Note 24
tSD
tLZWE
tHD
DATAIN VALID
Notes
21. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL and BHE or BLE = VIL. These signals must be LOW to initiate a write, and the
HIGH transition of any of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates
the write.
22. Data I/O is in high-impedance state if CE = VIH, or OE = VIH or BHE, and/or BLE = VIH.
23. The minimum write cycle pulse width should be equal to sum of tHZWE and tSD.
24. During this period the I/Os are in output state. Do not apply input signals.
Document Number: 002-03314 Rev. *D
Page 10 of 19
CY7C1051H
Switching Waveforms (continued)
Figure 9. Write Cycle No. 3 (WE controlled) [25, 26]
tW C
ADDRESS
tS C E
CE
tA W
tS A
tH A
tP W E
WE
tB W
B H E /B L E
OE
tH Z O E
D A T A I/O
Note27
tH D
tS D
D A T A IN V A L ID
Notes
25. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL and BHE or BLE = VIL. These signals must be LOW to initiate a write, and the
HIGH transition of any of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates
the write.
26. Data I/O is in high-impedance state if CE = VIH, or OE = VIH or BHE, and/or BLE = VIH.
27. During this period, the I/Os are in output state. Do not apply input signals.
Document Number: 002-03314 Rev. *D
Page 11 of 19
CY7C1051H
Switching Waveforms (continued)
Figure 10. Write Cycle No. 4 (BLE or BHE Controlled) [28, 29]
tWC
ADDRESS
tSCE
CE
tAW
tSA
tHA
tBW
BHE/
BLE
tPWE
WE
tHZWE
DATA I/O
Note 30
tSD
tHD
tLZWE
DATAIN VALID
Notes
28. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL, and BHE or BLE = VIL. These signals must be LOW to initiate a write, and the
HIGH transition of any of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates
the write.
29. Data I/O is in high-impedance state if CE = VIH, or OE = VIH, or BHE, and/or BLE = VIH.
30. During this period, the I/Os are in output state. Do not apply input signals.
Document Number: 002-03314 Rev. *D
Page 12 of 19
CY7C1051H
Truth Table
CE
H
OE
[31]
X
WE
BLE
BHE
[31]
[31]
[31]
High-Z
High-Z
Power down
Standby (ISB)
X
X
X
I/O0–I/O7
I/O8–I/O15
Mode
Power
L
L
H
L
L
Data out
Data out
Read all bits
Active (ICC)
L
L
H
L
H
Data out
High-Z
Read lower bits only
Active (ICC)
L
L
H
H
L
High-Z
Data out
Read upper bits only
Active (ICC)
L
X
L
L
L
Data in
Data in
Write all bits
Active (ICC)
L
X
L
L
H
Data in
High-Z
Write lower bits only
Active (ICC)
L
X
L
H
L
High-Z
Data in
Write upper bits only
Active (ICC)
L
H
H
X
X
High-Z
High-Z
Selected, outputs disabled
Active (ICC)
L
X
X
H
H
High-Z
High-Z
Selected, outputs disabled
Active (ICC)
Note
31. The input voltage levels on these pins should be either at VIH or VIL.
Document Number: 002-03314 Rev. *D
Page 13 of 19
CY7C1051H
Ordering Information
Speed
(ns)
10
Voltage
Range
Ordering Code
2.2 V–3.6 V CY7C1051H30-10ZSXI
Package Package Type
Diagram (all Pb-free)
Key Features /
Differentiators
Operating
Range
51-85087 44-pin TSOP II
Single Chip Enable
Industrial
CY7C1051H30-10ZSXIT
CY7C1051H30-10BVXI
51-85150 48-ball VFBGA
Ordering Code Definitions
CY 7 C 1 05 1
H
XX - 10
XX X
I
X
X = Blank or T
blank = Bulk; T = Tape and Reel
Temperature Range: I = Industrial
Pb-free
Package Type: XX = ZS or BV
ZS = 44-pin TSOP II; BV = 48-ball VFBGA
Speed: 10 ns
Voltage Range:
30 = 2.2 V–3.6 V
Process Technology: Revision Code “H” = 65 nm Technology
Data Width: 1 = × 16-bits
Density: 05 = 8-Mbit
Family Code: 1 = Fast Asynchronous SRAM family
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 002-03314 Rev. *D
Page 14 of 19
CY7C1051H
Package Diagram
Figure 11. 44-pin TSOP II (18.4 × 10.2 × 1.194 mm) Package Outline, 51-85087
51-85087 *F
Document Number: 002-03314 Rev. *D
Page 15 of 19
CY7C1051H
Package Diagram (continued)
Figure 12. 48-ball VFBGA (6 × 8 × 1.0 mm) Package Outline, 51-85150
51-85150 *I
Document Number: 002-03314 Rev. *D
Page 16 of 19
CY7C1051H
Acronyms
Document Conventions
Table 1. Acronyms Used in this Document
Units of Measure
Acronym
Description
Table 2. Units of Measure
BHE
Byte High Enable
BLE
Byte Low Enable
°C
degree Celsius
CE
Chip Enable
MHz
megahertz
CMOS
Complementary Metal Oxide Semiconductor
A
microampere
I/O
Input/Output
s
microsecond
OE
Output Enable
mA
milliampere
SRAM
Static Random Access Memory
mm
millimeter
TSOP
Thin Small Outline Package
ns
nanosecond
TTL
Transistor-Transistor Logic
ohm
VFBGA
Very Fine-Pitch Ball Grid Array
%
percent
WE
Write Enable
pF
picofarad
V
volt
W
watt
Document Number: 002-03314 Rev. *D
Symbol
Unit of Measure
Page 17 of 19
CY7C1051H
Document History Page
Document Title: CY7C1051H, 8-Mbit (512K Words × 16-Bit) Static RAM with Error-Correcting Code (ECC)
Document Number: 002-03314
Rev.
ECN No.
Submission
Date
**
4943606
10/09/2015
New data sheet.
*A
5258628
05/27/2016
Changed status from Preliminary to Final.
Updated to new template.
*B
5435280
09/13/2016
Updated Maximum Ratings:
Updated Note 3 (Replaced “2 ns” with “20 ns”).
Updated DC Electrical Characteristics:
Removed Operating Range “2.7 V to 3.6 V” and all values corresponding to VOH parameter.
Included Operating Ranges “2.7 V to 3.0 V” and “3.0 V to 3.6 V” and all values corresponding
to VOH parameter.
Updated Ordering Information:
Updated part numbers.
Updated Ordering Code Definitions.
Updated to new template.
Completing Sunset Review.
*C
5975928
11/27/2017
Updated Cypress Logo and Copyright.
*D
7023423
11/13/2020
Added 48-ball VFBGA package related information in all instances across the document.
Updated Ordering Information:
Updated part numbers.
Updated Package Diagram:
spec 51-85087 – Changed revision from *E to *F.
Added spec 51-85150 *I.
Updated to new template.
Completing Sunset Review.
Document Number: 002-03314 Rev. *D
Description of Change
Page 18 of 19
CY7C1051H
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Document Number: 002-03314 Rev. *D
Revised November 13, 2020
Page 19 of 19
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