Please note that Cypress is an Infineon Technologies Company.
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Continuity of document content
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Infineon continues to support existing part numbers. Please continue to use the
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CY7C10612G
CY7C10612GE
16-Mbit (1M × 16) Static RAM
16-Mbit (1M × 16) Static RAM
Features
Functional Description
■
High speed
❐ tAA = 10 ns
■
Embedded error-correcting code (ECC) for single-bit error
correction
■
Low active power
❐ ICC = 90 mA typical
The CY7C10612G and CY7C10612GE are high performance
CMOS fast static RAM devices with embedded ECC. These
devices are offered in single chip enable option. The
CY7C10612GE device includes an error indication pin that
signals an error-detection and correction event during a read
cycle.
To write to the device, take Chip Enables (CE) and Write Enable
(WE) input LOW. If Byte Low Enable (BLE) is LOW, then data
from I/O pins (I/O0 through I/O7), is written into the location
specified on the address pins (A0 through A19). If Byte High
Enable (BHE) is LOW, then data from I/O pins (I/O8 through
I/O15) is written into the location specified on the address pins
(A0 through A19).
■
Low CMOS standby power
❐ ISB2 = 20 mA typical
■
Operating voltages of 3.3 ± 0.3 V
■
1.0 V data retention
■
Transistor-transistor logic (TTL) compatible inputs and outputs
■
ERR pin to indicate 1-bit error detection and correction
■
Available in Pb-free 54-pin TSOP II package
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appears on I/O0 to I/O7. If
Byte High Enable (BHE) is LOW, then data from memory
appears on I/O8 to I/O15. See Truth Table on page 14 for a
complete description of Read and Write modes.
The input or output pins (I/O0 through I/O15) are placed in a high
impedance state when the device is deselected (CE HIGH), the
outputs are disabled (OE HIGH), the BHE and BLE are disabled
(BHE, BLE HIGH), or during a write operation (CE LOW and WE
LOW).
On the CY7C10612GE devices the detection and correction of a
single-bit error in the accessed location is indicated by the
assertion of the ERR output (ERR = high). See the Truth Table
on page 14 for a complete description of read and write modes.
The CY7C10612G and CY7C10612GE are available in a 54-pin
TSOP II package.
For a complete list of related documentation, click here.
Selection Guide
-10
Unit
Maximum Access Time
Description
10
ns
Maximum Operating Current
110
mA
Maximum CMOS Standby Current
30
mA
Cypress Semiconductor Corporation
Document Number: 001-88702 Rev. *F
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised January 3, 2018
CY7C10612G
CY7C10612GE
Logic Block Diagram – CY7C10612G
1M x 16
ARRAY
SENSE AMPS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
ROW DECODER
INPUT BUFFER
I/O0 – I/O7
I/O8 – I/O15
A10
A11
A 12
A 13
A 14
A15
A16
A17
A18
A19
COLUMN
DECODER
BHE
WE
CE
OE
BLE
Logic Block Diagram – CY7C10612GE
Document Number: 001-88702 Rev. *F
Page 2 of 19
CY7C10612G
CY7C10612GE
Contents
Pin Configurations ........................................................... 4
Maximum Ratings ............................................................. 6
Operating Range ............................................................... 6
DC Electrical Characteristics .......................................... 6
Capacitance ...................................................................... 7
Thermal Resistance .......................................................... 7
AC Test Loads and Waveforms ....................................... 7
Data Retention Characteristics ....................................... 8
Data Retention Waveform ................................................ 8
AC Switching Characteristics ......................................... 9
Switching Waveforms .................................................... 10
Truth Table ...................................................................... 14
ERR Output – CY7C10612GE ........................................ 14
Document Number: 001-88702 Rev. *F
Ordering Information ...................................................... 15
Ordering Code Definitions ......................................... 15
Package Diagrams .......................................................... 16
Acronyms ........................................................................ 17
Document Conventions ................................................. 17
Units of Measure ....................................................... 17
Document History Page ................................................. 18
Sales, Solutions, and Legal Information ...................... 19
Worldwide Sales and Design Support ....................... 19
Products .................................................................... 19
PSoC® Solutions ...................................................... 19
Cypress Developer Community ................................. 19
Technical Support ..................................................... 19
Page 3 of 19
CY7C10612G
CY7C10612GE
Pin Configurations
Figure 1. 54-pin TSOP II pinout (Top View) [1]
CY7C10612G
I/O12
VCC
I/O13
I/O14
VSS
I/O15
A4
A3
A2
A1
A0
BHE
CE
VCC
WE
NC
A19
A18
A17
A16
A15
I/O0
VCC
I/O1
I/O2
VSS
I/O3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
45
44
I/O11
VSS
I/O10
I/O9
VCC
I/O8
A5
A6
A7
A8
A9
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
NC
OE
VSS
NC
BLE
A10
A11
A12
A13
A14
I/O7
VSS
I/O6
I/O5
VCC
I/O4
54
53
52
51
50
49
48
47
46
Note
1. NC pins are not connected on the die.
Document Number: 001-88702 Rev. *F
Page 4 of 19
CY7C10612G
CY7C10612GE
Pin Configurations (continued)
Figure 2. 54-pin TSOP II pinout with ERR (Top View) [2, 3]
CY7C10612GE
Note
2. NC pins are not connected on the die.
3. ERR is an Output pin. If not used, this pin should be left floating.
Document Number: 001-88702 Rev. *F
Page 5 of 19
CY7C10612G
CY7C10612GE
DC Input Voltage[4] ............................. –0.5 V to VCC + 0.5 V
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage Temperature ............................... –65 C to +150 C
Ambient Temperature
with Power Applied .................................. –55 C to +125 C
Supply Voltage
on VCC Relative to GND[4] .................. –0.5 V to VCC + 0.5 V
Current into Outputs (LOW) ........................................ 20 mA
Static Discharge Voltage
(MIL-STD-883, Method 3015) ..... ............................> 2001 V
Latch Up Current ................................................... > 200 mA
Operating Range
DC Voltage Applied to Outputs
in High Z State[4] ................................. –0.5 V to VCC + 0.5 V
Range
Ambient Temperature
VCC
Industrial
–40 C to +85 C
3.3 V 0.3 V
DC Electrical Characteristics
Over the operating range of –40 C to 85 C
Parameter
VOH
Description
Output HIGH
Voltage
Test Conditions
10 ns
Unit
Min
Typ [5]
Max
2.2 V to 2.7 V VCC = Min, IOH = –4.0 mA
2.2
–
–
2.7 V to 3.0 V VCC = Min, IOH = –4.0 mA
2.4
–
–
–
–
0.4
V
2.0
–
VCC + 0.3
V
VCC = Min, IOL = 8 mA
V
VOL
Output LOW Voltage
VIH[4]
VIL[4]
Input HIGH Voltage
–0.3
–
0.8
V
IIX
Input Leakage Current
GND < VIN < VCC
–1.0
–
+1.0
A
IOZ
Output Leakage Current
GND < VOUT < VCC, Output disabled
–1.0
–
+1.0
A
ICC
Operating Supply Current
VCC = Max,
IOUT = 0 mA,
CMOS levels
f = 100 MHz
–
90.0
110.0
mA
f = 66.7 MHz
–
70.0
80.0
mA
–
Input LOW Voltage
–
ISB1
Automatic CE Power-down
Current – TTL Inputs
Max VCC, CE > VIH [5],
VIN > VIH or VIN < VIL, f = fMAX
–
–
40.0
mA
ISB2
Automatic CE Power-down
Current – CMOS Inputs
Max VCC, CE > VCC – 0.2 V [5],
VIN > VCC – 0.2 V or VIN < 0.2 V, f = 0
–
20.0
30.0
mA
Notes
4. VIL(min) = –2.0 V and VIH(max) = VCC + 2 V for pulse durations of less than 20 ns.
5. Typical values are included only for reference and are not guaranteed or tested. Typical values are measured at VCC = 1.8 V (for a VCC range of 1.65 V–2.2 V),
VCC = 3 V (for a VCC range of 2.2 V–3.6 V), and VCC = 5 V (for a VCC range of 4.5 V–5.5 V), TA = 25 °C.
Document Number: 001-88702 Rev. *F
Page 6 of 19
CY7C10612G
CY7C10612GE
Capacitance
Parameter [6]
Description
CIN
Input Capacitance
COUT
I/O Capacitance
Test Conditions
54-pin TSOP II Unit
TA = 25 C, f = 1 MHz, VCC = 3.3 V
10
pF
Thermal Resistance
Parameter [6]
Description
JA
Thermal Resistance
(junction to ambient)
JC
Thermal Resistance
(junction to case)
Test Conditions
54-pin TSOP II Unit
Still air, soldered on a 3 × 4.5 inch, four-layer printed circuit
board
93.63
C/W
21.58
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms [7]
HIGH Z CHARACTERISTICS:
R1 317
3.3 V
50
VTH = 1.5 V
OUTPUT
Z0 = 50
OUTPUT
30 pF*
5 pF*
INCLUDING
JIG AND
SCOPE
(b)
(a)
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
R2
351
ALL INPUT PULSES
3.0 V
GND
90%
90%
10%
RISE TIME:
> 1 V/ns
10%
(c)
FALL TIME:
> 1 V/ns
Notes
6. Tested initially and after any design or process changes that may affect these parameters.
7. Full-device AC operation assumes a 100-µs ramp time from 0 to VCC (min) and 100-µs wait time after VCC stabilizes to its operational value.
Document Number: 001-88702 Rev. *F
Page 7 of 19
CY7C10612G
CY7C10612GE
Data Retention Characteristics
Over the Operating Range –45 C to 85 C
Parameter
Description
Conditions
Min
Typ [8]
Max
Unit
–
1.0
–
–
V
–
–
30.0
mA
VDR
VCC for Data Retention
ICCDR
Data Retention Current
tCDR[9]
Chip Deselect to Data Retention Time
–
0.0
–
–
ns
tR[9, 10]
Operation Recovery Time
–
10.0
–
–
ns
VCC = 2 V, CE VCC – 0.2 V,
VIN VCC – 0.2 V or VIN 0.2 V
Data Retention Waveform
Figure 4. Data Retention Waveform
DATA RETENTION MODE
VCC
3.0 V
tCDR
VDR > 1 V
3.0 V
tR
CE
Notes
8. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
9. This parameter is guaranteed by design and is not tested.
10. Full device operation requires linear VCC ramp from VDR to VCC(min.) 100 s or stable at VCC(min.) 100 s.
Document Number: 001-88702 Rev. *F
Page 8 of 19
CY7C10612G
CY7C10612GE
AC Switching Characteristics
Over the Operating Range
Parameter [11]
Description
-10
Min
Max
Unit
Read Cycle
tPOWER
VCC to the first access [12]
100.0
–
µs
tRC
Read cycle time
10.0
–
ns
tAA
Address to data valid
–
10.0
ns
tOHA
Data hold from address change
3.0
–
ns
tACE
CE LOW to data valid
–
10.0
ns
tDOE
OE LOW to data valid
–
5.0
ns
0.0
–
ns
tLZOE
OE LOW to low Z
[13, 14, 15]
[13, 14, 15]
tHZOE
OE HIGH to high Z
tLZCE
CE LOW to low Z [13, 14, 15]
tHZCE
tPU
CE HIGH to high Z
–
5.0
ns
3.0
–
ns
[13, 14, 15]
–
5.0
ns
[16]
0.0
–
ns
CE LOW to power-up
tPD
CE HIGH to power-down
tDBE
Byte enable to data valid
tLZBE
tHZBE
Write Cycle
[16]
–
10.0
ns
–
5.0
ns
Byte enable to low Z
1.0
–
ns
Byte disable to high Z
–
6.0
ns
[17, 18]
tWC
Write cycle time
10.0
–
ns
tSCE
CE LOW to write end
7.0
–
ns
tAW
Address setup to write end
7.0
–
ns
tHA
Address hold from write end
0.0
–
ns
tSA
Address setup to write start
0.0
–
ns
tPWE
WE pulse width
7.0
–
ns
tSD
Data setup to write end
5.0
–
ns
tHD
Data hold from write end
0.0
–
ns
tLZWE
WE HIGH to low Z [13, 14, 15]
3.0
–
ns
tHZWE
WE LOW to high Z
[13, 14, 15]
–
5.0
ns
tBW
Byte enable to end of write
7.0
–
ns
Notes
11. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, and input pulse levels of 0 to 3.0 V. Test conditions for the read cycle use
output loading shown in part a) of Figure 3 on page 7, unless specified otherwise.
12. tPOWER gives the minimum amount of time that the power supply is at typical VCC values until the first memory access is performed.
13. tHZOE, tHZCE, tHZWE, tHZBE , tLZOE, tLZCE, tLZWE, and tLZBE are specified with a load capacitance of 5 pF as in (b) of Figure 3 on page 7. Transition is measured 200 mV from steady
state voltage.
14. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.
15. Tested initially and after any design or process changes that may affect these parameters.
16. These parameters are guaranteed by design and are not tested.
17. The internal write time of the memory is defined by the overlap of WE, CE = VIL. Chip enable must be active and WE and byte enables must be LOW to initiate a write,
and the transition of any of these signals can terminate. The input data setup and hold timing should be referenced to the edge of the signal that terminates the write.
18. The minimum write cycle time for Write Cycle No. 2 (WE Controlled, OE LOW) is the sum of tHZWE and tSD.
Document Number: 001-88702 Rev. *F
Page 9 of 19
CY7C10612G
CY7C10612GE
Switching Waveforms
Figure 5. Read Cycle No. 1 (Address Transition Controlled) for CY7C10612G [19, 20]
tRC
RC
ADDRESS
tOHA
DATA I/O
tAA
PREVIOUS DATA VALID
DATA OUT VALID
Figure 6. Read Cycle No. 1 (Address Transition Controlled) for CY7C10612GE [20, 21]
Notes
19. The device is continuously selected. OE, CE = VIL, BHE, BLE or both = VIL.
20. WE is HIGH for read cycle.
21. Address valid before or similar to CE transition LOW.
Document Number: 001-88702 Rev. *F
Page 10 of 19
CY7C10612G
CY7C10612GE
Switching Waveforms (continued)
Figure 7. Read Cycle No. 2 (OE Controlled) [22, 23]
ADDRESS
tRC
CE
tPD
tHZCE
tACE
OE
tHZOE
tDOE
tLZOE
BHE/
BLE
tDBE
tLZBE
DATA I/O
HIGH IMPEDANCE
tHZBE
DATAOUT VALID
HIGH
IMPEDANCE
tLZCE
VCC
SUPPLY
CURRENT
tPU
ISB
Notes
22. WE is HIGH for read cycle.
23. Address valid before or similar to CE transition LOW.
Document Number: 001-88702 Rev. *F
Page 11 of 19
CY7C10612G
CY7C10612GE
Switching Waveforms (continued)
Figure 8. Write Cycle No. 1 (CE Controlled) [24, 25, 26]
tWC
ADDRESS
tSA
CE
tSCE
tAW
tHA
tPWE
WE
tBW
BHE, BLE
tSD
tHD
DATA IN VALID
DATA I/O
Figure 9. Write Cycle No. 2 (WE Controlled, OE LOW) [24, 25, 26]
tWC
ADDRESS
tSCE
CE
tAW
tHA
tSA
tPWE
WE
tBW
BHE, BLE
tHZWE
DATA I/O
Note 27
tSD
tHD
DATA IN VALID
tLZWE
Notes
24. Data I/O is high impedance if OE, BHE, and/or BLE = VIH.
25. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL and BHE or BLE = VIL. These signals must be LOW to initiate a write, and the
HIGH transition of any of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates
the write.
26. The minimum write cycle pulse width should be equal to the sum of tHZWE and tSD.
27. During this period the I/Os are in output state. Do not apply input signals.
Document Number: 001-88702 Rev. *F
Page 12 of 19
CY7C10612G
CY7C10612GE
Switching Waveforms (continued)
Figure 10. Write Cycle No. 3 (BLE or BHE Controlled) [28, 29]
tWC
ADDRESS
tSA
tBW
BHE, BLE
tAW
tHA
tPWE
WE
tSCE
CE
Note 30
DATA I/O
tSD
tHD
DATA IN VALID
Notes
28. Data I/O is high impedance if OE, BHE, and/or BLE = VIH.
29. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL and BHE or BLE = VIL. These signals must be LOW to initiate a write, and the
HIGH transition of any of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates
the write.
30. During this period, the I/Os are in output state. Do not apply input signals.
Document Number: 001-88702 Rev. *F
Page 13 of 19
CY7C10612G
CY7C10612GE
Truth Table
I/O0–I/O7
I/O8–I/O15
Mode
Power
CE
OE
WE
BLE
BHE
H
X
X
X
X
High Z
High Z
Power-down
Standby (ISB)
L
L
H
L
L
Data Out
Data Out
Read all bits
Active (ICC)
L
L
H
L
H
Data Out
High Z
Read lower bits only
Active (ICC)
L
L
H
H
L
High Z
Data Out
Read upper bits only
Active (ICC)
L
X
L
L
L
Data In
Data In
Write all bits
Active (ICC)
L
X
L
L
H
Data In
High Z
Write lower bits only
Active (ICC)
L
X
L
H
L
High Z
Data In
Write upper bits only
Active (ICC)
L
H
H
X
X
High Z
High Z
Selected, outputs disabled Active (ICC)
ERR Output – CY7C10612GE
Output[31]
0
1
High-Z
Mode
Read Operation, no error in the stored data.
Read Operation, single-bit error detected and corrected.
Device deselected or Outputs disabled or Write Operation.
Note
31. ERR is an Output pin. If not used, this pin should be left floating.
Document Number: 001-88702 Rev. *F
Page 14 of 19
CY7C10612G
CY7C10612GE
Ordering Information
Speed
(ns)
Package
Diagram
Ordering Code
10
CY7C10612G30-10ZSXI
Package Type (Pb-free)
51-85160 54-pin TSOP II
CY7C10612G30-10ZSXIT
54-pin TSOP II, Tape and Reel
CY7C10612GE30-10ZSXI
54-pin TSOP II, with ERR Pin
CY7C10612GE30-10ZSXIT
54-pin TSOP II, with ERR Pin, Tape and Reel
Operating
Range
Industrial
Ordering Code Definitions
CY
7
C
1
06 1
2
G
E
30 - 10 ZS X
I
X
X = blank or T
blank = Bulk; T = Tape and Reel
Temperature Range:
I = Industrial
Pb-free
Package Type:
ZS = 54-pin TSOP II
Speed Grade: 10 ns
Voltage Range: 30 = 3 V to 3.6 V
X = blank or E
blank = without ERR output;
E = with ERR output, Single bit error correction indicator
Process Technology: G = 65 nm
Single chip enable
Bus Width: 1 = × 16
Density: 06 = 16-Mbit
Fast asynchronous SRAM family
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 001-88702 Rev. *F
Page 15 of 19
CY7C10612G
CY7C10612GE
Package Diagrams
Figure 11. 54-pin TSOP II (22.4 × 11.84 × 1.0 mm) Z54-II Package Outline, 51-85160
51-85160 *E
Document Number: 001-88702 Rev. *F
Page 16 of 19
CY7C10612G
CY7C10612GE
Acronyms
Document Conventions
Table 1. Acronyms Used in this Document
Units of Measure
Acronym
Description
Table 2. Units of Measure
BHE
Byte High Enable
BLE
Byte Low Enable
°C
degree Celsius
CE
Chip Enable
MHz
megahertz
CMOS
Complementary Metal Oxide Semiconductor
µA
microampere
I/O
Input/Output
s
microsecond
OE
Output Enable
mA
milliampere
SRAM
Static Random Access Memory
mm
millimeter
TSOP
Thin Small Outline Package
mV
millivolt
TTL
Transistor-Transistor Logic
WE
Write Enable
Document Number: 001-88702 Rev. *F
Symbol
Unit of Measure
ns
nanosecond
ohm
%
percent
pF
picofarad
V
volt
W
watt
Page 17 of 19
CY7C10612G
CY7C10612GE
Document History Page
Document Title: CY7C10612G/CY7C10612GE, 16-Mbit (1M × 16) Static RAM
Document Number: 001-88702
Rev.
ECN No.
Orig. of
Change
Submission
Date
*D
4865557
NILE
07/31/2015
Changed status from Preliminary to Final.
*E
5437839
NILE
09/15/2016
Updated Maximum Ratings:
Updated Note 4 (Replaced “2 ns” with “20 ns”).
Updated DC Electrical Characteristics:
Removed all values corresponding to VOH parameter.
Included Operating Ranges “2.2 V to 2.7 V” and “2.7 V to 3.0 V” and all values
corresponding to VOH parameter.
Updated Ordering Information:
Updated part numbers.
Updated Ordering Code Definitions.
Updated to new template.
Completing Sunset Review.
*F
6011828
AESATMP8
01/03/2018
Updated logo and Copyright.
Document Number: 001-88702 Rev. *F
Description of Change
Page 18 of 19
CY7C10612G
CY7C10612GE
Sales, Solutions, and Legal Information
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closest to you, visit us at Cypress Locations.
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© Cypress Semiconductor Corporation, 2013-2018. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC (“Cypress”). This document,
including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing
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such as unauthorized access to or use of a Cypress product. In addition, the products described in these materials may contain design defects or errors known as errata which may cause the product
to deviate from published specifications. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any
liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming
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information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons
systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances
management, or other uses where the failure of the device or system could cause personal injury, death, or property damage (“Unintended Uses”). A critical component is any component of a device
or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you
shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from
and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 001-88702 Rev. *F
Revised January 3, 2018
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