CY7C10612GN30-10ZSXIT

CY7C1061GN/CY7C10612GN 16-Mbit (1M words × 16 bit) Static RAM 16-Mbit (1M words × 16 bit) Static RAM Features Functional Description ■ High speed ❐ tAA = 10 ns/15 ns The CY7C1061GN/CY7C10612GN is a high performance CMOS Static RAM organized as 1,048,576 words by 16 bits. ■ Low active power ❐ ICC = 90 mA at 100 MHz ■ Low CMOS standby current ❐ ISB2 = 20 mA (typ) ■ Operating voltages of 2.2 V to 3.6 V To write to the device, take Chip Enables (CE1 LOW and CE2 HIGH) and Write Enable (WE) input LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A19). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A19). ■ 1.0 V data retention ■ Automatic power down when deselected ■ TTL compatible inputs and outputs ■ Easy memory expansion with CE1 and CE2 features ■ Available in Pb-free 48-pin TSOP I, 54-pin TSOP II, and 48-ball VFBGA packages ■ Offered in dual Chip Enable options To read from the device, take Chip Enables (CE1 LOW and CE2 HIGH) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appears on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory appears on I/O8 to I/O15. See Truth Table on page 13 for a complete description of Read and Write modes. The input or output pins (I/O0 through I/O15) are placed in a high impedance state when the device is deselected (CE1 HIGH/CE2 LOW), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE1 LOW, CE2 HIGH, and WE LOW). Logic Block Diagram SENSE AMPS A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 ROW DECODER INPUT BUFFER 1M x 16 ARRAY I/O0 – I/O7 I/O8 – I/O15 A10 A11 A 12 A 13 A 14 A15 A16 A17 A18 A19 COLUMN DECODER BHE WE OE BLE Cypress Semiconductor Corporation Document Number: 001-93680 Rev. *C • 198 Champion Court • CE2 CE1 San Jose, CA 95134-1709 • 408-943-2600 Revised September 29, 2016 CY7C1061GN/CY7C10612GN Contents Selection Guide ................................................................ 3 Pin Configurations ........................................................... 3 Maximum Ratings ............................................................. 6 Operating Range ............................................................... 6 DC Electrical Characteristics .......................................... 6 Capacitance ...................................................................... 7 Thermal Resistance .......................................................... 7 AC Test Loads and Waveforms ....................................... 7 Data Retention Characteristics ....................................... 8 Over the Operating Range ............................................... 8 Data Retention Waveform ................................................ 8 AC Switching Characteristics ......................................... 9 Switching Waveforms .................................................... 10 Truth Table ...................................................................... 13 Document Number: 001-93680 Rev. *C Ordering Information ...................................................... 14 Ordering Code Definitions ......................................... 14 Package Diagrams .......................................................... 15 Acronyms ........................................................................ 18 Document Conventions ................................................. 18 Units of Measure ....................................................... 18 Document History Page ................................................. 19 Sales, Solutions, and Legal Information ...................... 21 Worldwide Sales and Design Support ....................... 21 Products .................................................................... 21 PSoC®Solutions ....................................................... 21 Cypress Developer Community ................................. 21 Technical Support ..................................................... 21 Page 2 of 21 CY7C1061GN/CY7C10612GN Selection Guide -10 -15 Unit Maximum access time Description 10 15 ns Maximum operating current 110 80 mA Maximum CMOS standby current 30 30 mA Pin Configurations Figure 1. 48-ball VFBGA (8 × 9.5 × 1 mm) Dual Chip Enable pinout, Package/Grade ID: BVXI [1] 1 2 3 4 5 6 BLE OE A0 A1 A2 CE2 A I/O8 BHE A3 A4 CE1 I/O0 B I/O9 I/O10 A5 A6 I/O1 I/O2 C VSS I/O11 A17 A7 I/O3 VCC D VCC I/O12 NC A16 I/O4 VSS E I/O14 I/O13 A14 A15 I/O5 I/O6 F I/O15 NC A12 A13 WE I/O7 G A18 A8 A9 A10 A11 A19 H Note 1. NC pins are not connected internally to the die. Document Number: 001-93680 Rev. *C Page 3 of 21 CY7C1061GN/CY7C10612GN Pin Configurations (continued) Figure 2. 48-ball VFBGA (6 × 8 × 1.0 mm) Single Chip Enable pinout, Package/Grade ID: BV1XI [2] 1 2 3 4 5 6 BLE OE A0 A1 A2 NC I/O8 BHE A3 A4 CE I/O9 I/O10 A5 A6 VSS I/O11 A17 Figure 3. 48-ball VFBGA (6 × 8 × 1.0 mm) Dual Chip Enable pinout, Package/Grade ID: BVJXI [2] 1 2 3 4 5 6 A BLE OE A0 A1 A2 CE2 A I/O0 B I/O8 BHE A3 A4 CE1 I/O0 B I/O1 I/O2 C I/O9 I/O10 A5 A6 I/O1 I/O2 C A7 I/O3 VCC D VSS I/O11 A17 A7 VCC D ERR A16 I/O4 VSS E I/O3 VCC I/O12 NC A16 I/O4 VSS E VCC I/O14 I/O13 A14 A15 I/O5 I/O6 F I/O14 I/O13 A14 A15 I/O5 I/O6 F I/O15 A19 A12 A13 WE I/O7 G I/O15 A19 A12 A13 WE I/O7 G A18 A8 A9 A10 A11 NC H A18 A8 A9 A10 A11 NC H Figure 4. 54-pin TSOP II (22.4 × 11.84 × 1.0 mm) Dual Chip Enable pinout (Top View) [2] I/O12 VCC I/O13 I/O14 VSS I/O15 A4 A3 A2 A1 A0 BHE CE1 VCC WE CE2 A19 A18 A17 A16 A15 I/O0 VCC I/O1 I/O2 VSS I/O3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 I/O11 VSS I/O10 I/O9 VCC I/O8 A5 A6 A7 A8 A9 NC OE VSS NC BLE A10 A11 A12 A13 A14 I/O7 VSS I/O6 I/O5 VCC I/O4 I/O12 Figure 5. 54-pin TSOP II (22.4 × 11.84 × 1.0 mm) Single Chip Enable pinout (Top View) [2] I/O12 VCC I/O13 I/O14 VSS I/O15 A4 A3 A2 A1 A0 BHE CE VCC WE NC A19 A18 A17 A16 A15 I/O0 VCC I/O1 I/O2 VSS I/O3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 45 44 I/O11 VSS I/O10 I/O9 VCC I/O8 A5 A6 A7 A8 A9 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 NC OE VSS NC BLE A10 A11 A12 A13 A14 I/O7 VSS I/O6 I/O5 VCC I/O4 54 53 52 51 50 49 48 47 46 Note 2. NC pins are not connected internally to the die. Document Number: 001-93680 Rev. *C Page 4 of 21 CY7C1061GN/CY7C10612GN Pin Configurations (continued) Figure 6. 48-pin TSOP I (12 × 18.4 × 1 mm) pinout (Top View) [3] A4 A3 A2 A1 A0 NC CE I/O0 I/O1 I/O2 I/O3 VDD GND I/O4 I/O5 I/O6 I/O7 WE NC A19 A18 A17 A16 A15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A5 A6 A7 A8 OE BHE BLE I/O15 I/O14 I/O13 I/O12 GND VDD I/O11 I/O10 I/O9 I/O8 NC A9 A10 A11 A12 A13 A14 Note 3. NC pins are not connected internally to the die. Document Number: 001-93680 Rev. *C Page 5 of 21 CY7C1061GN/CY7C10612GN DC Input Voltage [4] ............................ –0.5 V to VCC + 0.5 V Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ............................... –65 C to +150 C Ambient Temperature with Power Applied .................................. –55 C to +125 C Current into Outputs (LOW) ........................................ 20 mA Static Discharge Voltage (MIL-STD-883, Method 3015) .................................. >2001 V Latch Up Current .................................................... >200 mA Operating Range Supply Voltage on VCC relative to GND [4] .................. –0.5 V to VCC + 0.5 V DC Voltage Applied to Outputs in High Z State [4] ................................ –0.5 V to VCC + 0.5 V Range Ambient Temperature VCC Industrial –40 C to +85 C 1.65 V to 2.2 V, 2.2 V to 3.6 V DC Electrical Characteristics Over the Operating Range Parameter VOH VOL VIH VIL Description Output HIGH voltage Output LOW voltage Input HIGH voltage [4] Input LOW voltage [4] Test Conditions 10 ns/15 ns Unit Min Typ [5] Max 1.65 V to 2.2 V VCC = Min, IOH = –0.1 mA 1.4 – – 2.2 V to 2.7 V VCC = Min, IOH = –0.1 mA 2.0 – – 2.7 V to 3.0 V VCC = Min, IOH = –4.0 mA 2.2 – – 3.0 V to 3.6 V VCC = Min, IOH = –4.0 mA 2.4 – – 1.65 V to 2.2 V VCC = Min, IOL = 0.1 mA – – 0.2 2.2 V to 2.7 V VCC = Min, IOL = 2 mA – – 0.4 2.7 V to 3.6 V VCC = Min, IOL = 8 mA – – 0.4 1.65 V to 2.2 V – 1.4 – VCC + 0.2 2.2 V to 2.7 V – 2.0 – VCC + 0.3 V V 2.7 V to 3.6 V – 2.0 – VCC + 0.3 1.65 V to 2.2 V – –0.2 – 0.4 2.2 V to 2.7 V – –0.3 – 0.6 2.7 V to 3.6 V – –0.3 – 0.8 V V IIX Input leakage current GND < VI < VCC –1 – +1 A IOZ Output leakage current GND < VOUT < VCC, Output disabled –1 – +1 A ICC VCC operating supply current VCC = Max, IOUT = 0 mA, f = 100 MHz – 90 110 mA f = 66.7 MHz – 70 80 – – 40 mA – 20 30 mA CMOS levels ISB1 Automatic CE power down current – TTL inputs[6] Max VCC, CE1 > VIH, CE2 < VIL, VIN > VIH or VIN < VIL, f = fMAX ISB2 Automatic CE power down current – CMOS inputs[6] Max VCC, CE1 > VCC – 0.3 V, CE2 < 0.3 V, VIN > VCC – 0.3 V or VIN < 0.3 V, f = 0 Notes 4. VIL(min) = –2.0 V and VIH(max) = VCC + 2 V for pulse durations of less than 20 ns. 5. Typical values are included only for reference and are not guaranteed or tested. Typical values are measured at VCC = 1.8 V (for a VCC range of 1.65 V–2.2 V), VCC = 3 V (for a VCC range of 2.2 V–3.6 V) at TA = 25 °C. 6. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH. Document Number: 001-93680 Rev. *C Page 6 of 21 CY7C1061GN/CY7C10612GN Capacitance Parameter [7] Description CIN Input capacitance COUT I/O capacitance Test Conditions TA = 25 C, f = 1 MHz, VCC = 3.3 V 48-pin TSOP I 54-pin TSOP II 48-ball VFBGA Unit 10 10 10 pF 10 10 10 pF Thermal Resistance Parameter [7] Description JA Thermal resistance (junction to ambient) JC Thermal resistance (junction to case) Test Conditions Still air, soldered on a 3 × 4.5 inch, four layer printed circuit board 48-pin TSOP I 54-pin TSOP II 48-ball VFBGA Unit 57.99 93.63 31.50 C/W 13.42 21.58 15.75 C/W AC Test Loads and Waveforms Figure 7. AC Test Loads and Waveforms [8] High-Z Characteristics: VCC 50  Output VTH Z0 = 50  Output 30 pF* Including JIG and Scope (b) All Input Pulses VHIGH GND R2  5 pF* (a) * Capacitive Load Consists of all Components of the Test Environment R1 90% 90% 10% Rise Time: > 1 V/ns 10% (c) Fall Time: > 1 V/ns Parameters 1.8 V 3.0 V Unit R1 1667 317  R2 1538 351  VTH 0.9 1.5 V VHIGH 1.8 3 V Notes 7. Tested initially and after any design or process changes that may affect these parameters. 8. Full-device AC operation assumes a 100-µs ramp time from 0 to VCC (min) and 100-µs wait time after VCC stabilizes to its operational value. Document Number: 001-93680 Rev. *C Page 7 of 21 CY7C1061GN/CY7C10612GN Data Retention Characteristics Over the Operating Range Parameter Description Conditions Min Max Unit VDR VCC for data retention – 1 – V ICCDR Data retention current VCC = 1.2 V, – 30 mA CE1 > VCC – 0.2 V, CE2 < 0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V tCDR [9] tR[10] Chip deselect to data retention time – 0 – ns Operation recovery time VCC > 2.2 V 10 – ns VCC < 2.2 V 15 – Data Retention Waveform Figure 8. Data Retention Waveform [11] Data Retention Mode VCC VCC (min) VDR > 1 V tCDR VCC (min) tR CE Notes 9. Tested initially and after any design or process changes that may affect these parameters. 10. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 100 s or stable at VCC(min.) > 100 s. 11. CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH. Document Number: 001-93680 Rev. *C Page 8 of 21 CY7C1061GN/CY7C10612GN AC Switching Characteristics Over the Operating Range Parameter [12] -10 Description -15 Min Max Min Max Unit Read Cycle tpower VCC(typical) to the first access [13] 100 – 100 – s tRC Read cycle time 10 – 15 – ns tAA Address to data valid – 10 – 15 ns tOHA Data hold from address change 3 – 3 – ns tACE CE1 LOW/CE2 HIGH to data valid – 10 – 15 ns tDOE OE LOW to data valid – 5 – 8 ns 0 – 1 – ns – 5 – 8 ns 3 – 3 – ns – 5 – 8 ns 0 – 0 – ns tLZOE OE LOW to low Z [14] [14, 15] tHZOE OE HIGH to high Z tLZCE CE1 LOW/CE2 HIGH to low Z [14] tHZCE tPU CE1 HIGH/CE2 LOW to high Z [14, 15] CE1 LOW/CE2 HIGH to power-up [16] [16] tPD CE1 HIGH/CE2 LOW to power-down – 10 – 15 ns tDBE Byte enable to data valid – 5 – 8 ns tLZBE Byte enable to low Z 0 – 1 – ns Byte disable to high Z – 6 – 8 ns 10 – 15 – ns 7 – 12 – ns 7 – 12 – ns tHZBE Write Cycle tWC [17, 18] Write cycle time end[19] tSCE CE1 LOW/CE2 HIGH to write tAW Address setup to write end tHA Address hold from write end 0 – 0 – ns tSA Address setup to write start 0 – 0 – ns tPWE WE pulse width 7 – 12 – ns tSD Data setup to write end 5 – 8 – ns tHD Data hold from write end 0 – 0 – ns tLZWE WE HIGH to low Z [14] 3 – 3 – ns – 5 – 8 ns 7 – 12 – ns [14, 15] tHZWE WE LOW to high Z tBW Byte Enable to End of Write Notes 12. Test conditions assume signal transition time (rise/fall) of 3 ns or less, timing reference levels of 1.5 V (for VCC > 3 V) and VCC/2 (for VCC < 3 V), and input pulse levels of 0 to 3 V (for VCC > 3 V) and 0 to VCC (for VCC < 3V). Test conditions for the read cycle use the output loading, shown in part (a) of Figure 7 on page 7, unless specified otherwise. 13. tPOWER gives the minimum amount of time that the power supply is at typical VCC values until the first memory access is performed. 14. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device. 15. tHZOE, tHZCE, tHZWE, and tHZBE are specified with a load capacitance of 5 pF, as shown in part (b) of Figure 7 on page 7. Hi-Z, Lo-Z transition is measured 200 mV from steady state voltage. 16. These parameters are guaranteed by design and are not tested. 17. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, and CE2 = VIH. Chip enables must be active and WE and byte enables must be LOW to initiate a write, and the transition of any of these signals can terminate. The input data setup and hold timing should be referenced to the edge of the signal that terminates the write. 18. The minimum write cycle time for Write Cycle No. 2 (WE Controlled, OE LOW) is the sum of tHZWE and tSD. 19. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH. Document Number: 001-93680 Rev. *C Page 9 of 21 CY7C1061GN/CY7C10612GN Switching Waveforms Figure 9. Read Cycle No. 1 (Address Transition Controlled) [20, 21] tRC RC Address tAA tOHA Data Out Previous Data Valid Data Valid Figure 10. Read Cycle No. 2 (OE Controlled) [21, 22, 23] Address tRC CE tACE OE tHZOE tDOE BHE, BLE tLZOE tHZCE tDBE tLZBE Data Out High Impedance Data Valid tLZCE VCC Supply Current tHZBE High Impedance tPD tPU 50% 50% IICC CC IISB SB Notes 20. The device is continuously selected. OE, CE = VIL, BHE, BLE or both = VIL. 21. WE is HIGH for read cycle. 22. CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH. 23. Address valid before or similar to CE transition LOW. Document Number: 001-93680 Rev. *C Page 10 of 21 CY7C1061GN/CY7C10612GN Switching Waveforms (continued) Figure 11. Write Cycle No. 1 (CE Controlled) [24, 25, 26] tWC Address tSA CE tSCE tAW tHA tPWE WE tBW BHE, BLE tSD tHD Data I/O Figure 12. Write Cycle No. 2 (WE Controlled, OE LOW) [24, 25, 26] tWC Address tSCE CE tAW tHA tSA tPWE WE tBW BHE, BLE tHZWE tSD tHD Data I/O tLZWE Notes 24. CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH. 25. Data I/O is high impedance if OE, BHE, and/or BLE = VIH. 26. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. Document Number: 001-93680 Rev. *C Page 11 of 21 CY7C1061GN/CY7C10612GN Switching Waveforms (continued) Figure 13. Write Cycle No. 3 (BLE or BHE Controlled) [27] tWC Address tSA tBW BHE, BLE tAW tHA tPWE WE tSCE CE tSD tHD Data I/O Note 27. CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH. Document Number: 001-93680 Rev. *C Page 12 of 21 CY7C1061GN/CY7C10612GN Truth Table CE1 CE2 OE WE BLE BHE I/O0–I/O7 I/O8–I/O15 Mode Power H X X X X X High Z High Z Power down Standby (ISB) X L X X X X High Z High Z Power down Standby (ISB) L H L H L L Data out Data out Read all bits Active (ICC) L H L H L H Data out High Z Read lower bits only Active (ICC) L H L H H L High Z Data out Read upper bits only Active (ICC) L H X L L L Data in Data in Write all bits Active (ICC) L H X L L H Data in High Z Write lower bits only Active (ICC) L H X L H L High Z Data in Write upper bits only Active (ICC) L H H H X X High Z High Z Selected, outputs disabled Active (ICC) Document Number: 001-93680 Rev. *C Page 13 of 21 CY7C1061GN/CY7C10612GN Ordering Information Speed (ns) 10 15 Ordering Code Package Diagram Package Type (Pb-free) CY7C1061GN30-10ZSXI 51-85160 54-pin TSOP II, Dual Chip Enable CY7C1061GN30-10ZSXIT 51-85160 54-pin TSOP II, Dual Chip Enable, Tape and Reel CY7C10612GN30-10ZSXI 51-85160 54-pin TSOP II, Single Chip Enable CY7C10612GN30-10ZSXIT 51-85160 54-pin TSOP II, Single Chip Enable, Tape and Reel CY7C1061GN30-10ZXI 51-85183 48-pin TSOP I, Single Chip Enable CY7C1061GN30-10ZXIT 51-85183 48-pin TSOP I, Single Chip Enable, Tape and Reel CY7C1061GN30-10BV1XI 51-85150 48-ball VFBGA, Single Chip Enable, Address MSB A19 at ball G2 CY7C1061GN30-10BV1XIT 51-85150 48-ball VFBGA, Single Chip Enable, Address MSB A19 at ball G2, Tape and Reel CY7C1061GN30-10BVJXI 51-85150 48-ball VFBGA, Dual Chip Enable, Address MSB A19 at ball G2 CY7C1061GN30-10BVJXIT 51-85150 48-ball VFBGA, Dual Chip Enable, Address MSB A19 at ball G2, Tape and Reel CY7C1061GN30-10BVXI 51-85150 48-ball VFBGA, Dual Chip Enable, Address MSB A19 at ball H6 CY7C1061GN30-10BVXIT 51-85150 48-ball VFBGA, Dual Chip Enable, Address MSB A19 at ball H6, Tape and Reel CY7C1061GN18-15ZSXI 51-85160 54-pin TSOP II CY7C1061GN18-15ZSXIT 51-85160 54-pin TSOP II, Tape and Reel Operating Range Industrial Ordering Code Definitions CY 7 C 1 06 1 X G N XX - X XX X I X X = blank or T blank = Bulk; T = Tape and Reel Temperature Range: I = Industrial Pb-free Package Type: XX = ZS or ZX or BV1 or BVJ or BV ZS = 54-pin TSOP II; ZX = 48-pin TSOP I; BV1 = 48-ball VFBGA, Single Chip Enable, Address MSB A19 at ball G2; BVJ = 48-ball VFBGA, Dual Chip Enable, Address MSB A19 at ball G2; BV = 48-ball VFBGA, Dual Chip Enable, Address MSB A19 at ball H6 Speed: X = 10 or 15 10 = 10 ns; 15 = 15 ns Voltage Range: XX = 30 or 18 30 = 2.2 V to 3.6 V; 18 = 1.65 V to 2.2 V N = No ECC Process Technology: G = 65 nm Technology Chip Enable: X = blank or 2 Data Width: 1 = × 16-bits Density: 06 = 16-Mbit density Family Code: 1 = Fast Asynchronous SRAM family Technology Code: C = CMOS Marketing Code: 7 = SRAM Company ID: CY = Cypress Document Number: 001-93680 Rev. *C Page 14 of 21 CY7C1061GN/CY7C10612GN Package Diagrams Figure 14. 54-pin TSOP II (22.4 × 11.84 × 1.0 mm) Z54-II Package Outline, 51-85160 51-85160 *E Document Number: 001-93680 Rev. *C Page 15 of 21 CY7C1061GN/CY7C10612GN Package Diagrams (continued) Figure 15. 48-pin TSOP I (12 × 18.4 × 1.0 mm) Z48A Package Outline, 51-85183 51-85183 *D Document Number: 001-93680 Rev. *C Page 16 of 21 CY7C1061GN/CY7C10612GN Package Diagrams (continued) Figure 16. 48-ball VFBGA (6 × 8 × 1.0 mm) BV48/BZ48 Package Outline, 51-85150 51-85150 *H Document Number: 001-93680 Rev. *C Page 17 of 21 CY7C1061GN/CY7C10612GN Acronyms Acronym Document Conventions Description Units of Measure BHE Byte High Enable BLE Byte Low Enable °C degree Celsius CE Chip Enable MHz megahertz CMOS Complementary Metal Oxide Semiconductor A microampere I/O Input/Output s microsecond OE Output Enable mA milliampere SRAM Static Random Access Memory mm millimeter TSOP Thin Small Outline Package ns nanosecond TTL Transistor-Transistor Logic  ohm VFBGA Very Fine-Pitch Ball Grid Array % percent WE Write Enable pF picofarad V volt W watt Document Number: 001-93680 Rev. *C Symbol Unit of Measure Page 18 of 21 CY7C1061GN/CY7C10612GN Document History Page Document Title: CY7C1061GN/CY7C10612GN, 16-Mbit (1M words × 16 bit) Static RAM Document Number: 001-93680 Rev. ECN No. Orig. of Change Submission Date ** 4505531 VINI 01/02/2015 New data sheet. *A 4900408 NILE 09/11/2015 Updated DC Electrical Characteristics: Updated details in “Test Conditions” column of VOH and VOL parameters. Updated Ordering Information: No change in part numbers. Replaced “51-85178” with “51-85150” in “Package Diagram” column. Replaced “8 × 9.5 × 1 mm” with “6 × 8 × 1.0 mm” in “Package Type” column. Updated Package Diagrams: Removed spec 51-85178 *C. Added spec 51-85150 *H. Updated to new template. *B 5415385 NILE 09/07/2016 Updated Document Title to read as “CY7C1061GN/CY7C10612GN, 16-Mbit (1M words × 16 bit) Static RAM”. Added CY7C10612GN part related information in all instances across the document. Added “1.65 V to 2.2 V” voltage range related information in all instances across the document. Added 48-pin TSOP I package related information in all instances across the document. Added 15 ns speed bin related information in all instances across the document. Updated Pin Configurations: Added Figure 2. Added Figure 3. Added Figure 4. Added Figure 5. Added Figure 6. Removed figure “54-pin TSOP II (22.4 × 11.84 × 1.0 mm) pinout (Top View)”. Updated DC Electrical Characteristics: Updated details in “Test Conditions” column of ICC parameter (Added condition “f = 66.7 MHz” and added corresponding values). Added Note 6 and referred the same note in description of ISB1 and ISB2 parameters. Updated AC Test Loads and Waveforms: Updated Note 8 referred in Figure 7. Updated AC Switching Characteristics: Updated Note 12. Added Note 14 and referred the same note in description of tLZOE, tHZOE, tLZCE, tHZCE parameters. Updated Note 15. Added Note 19 and referred the same note in description of tSCE parameter. Updated Ordering Information: Updated part numbers. Updated Package Diagrams: Added spec 51-85183 *D. Updated to new template. Document Number: 001-93680 Rev. *C Description of Change Page 19 of 21 CY7C1061GN/CY7C10612GN Document History Page (continued) Document Title: CY7C1061GN/CY7C10612GN, 16-Mbit (1M words × 16 bit) Static RAM Document Number: 001-93680 Rev. ECN No. Orig. of Change Submission Date Description of Change *C 5454555 NILE 09/29/2016 Updated Maximum Ratings: Updated Note 4 (Replaced “2 ns” with “20 ns”). Updated DC Electrical Characteristics: Removed Operating Range “2.7 V to 3.6 V” and all values corresponding to VOH parameter. Included Operating Ranges “2.7 V to 3.0 V” and “3.0 V to 3.6 V” and all values corresponding to VOH parameter. Updated Ordering Information: Updated part numbers. Updated Ordering Code Definitions. Document Number: 001-93680 Rev. *C Page 20 of 21 CY7C1061GN/CY7C10612GN Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. 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