CY7C1061AV33-10ZXI

CY7C1061AV33 16-Mbit (1 M × 16) Static RAM Features ■ Functional Description The CY7C1061AV33 is a high performance CMOS Static RAM organized as 1,048,576 words by 16 bits. To write to the device, enable the chip (CE1 LOW and CE2 HIGH) while forcing the Write Enable (WE) input LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A19). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A19). To read from the device, enable the chip by taking CE1 LOW and CE2 HIGH while forcing the Output Enable (OE) LOW and the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See “Truth Table” on page 8 for a complete description of Read and Write modes. The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when the device is deselected (CE1 HIGH/CE2 LOW), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or a Write operation is in progress (CE1 LOW, CE2 HIGH, and WE LOW). High speed ❐ tAA = 10 ns Low active power ❐ 990 mW (max) Operating voltages of 3.3 ± 0.3 V 2.0 V data retention Automatic power down when deselected TTL compatible inputs and outputs Easy memory expansion with CE1 and CE2 features Available in Pb-free and non Pb-free 54-pin TSOP II package and non Pb-free 60-ball fine pitch ball grid array (FBGA) package ■ ■ ■ ■ ■ ■ ■ Logic Block Diagram INPUT BUFFER A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 ROW DECODER SENSE AMPS 1M x 16 ARRAY I/O0–I/O7 I/O8–I/O15 COLUMN DECODER A10 A11 A 12 A 13 A 14 A15 A16 A17 A18 A19 BHE WE OE BLE CE2 CE1 Cypress Semiconductor Corporation Document #: 38-05256 Rev. *J • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised February 2, 2011 [+] Feedback CY7C1061AV33 Contents Selection Guide ................................................................ 3 Pin Configurations ........................................................... 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 DC Electrical Characteristics (Over the Operating Range) ............................................. 4 Capacitance ...................................................................... 4 AC Test Loads and Waveforms ....................................... 4 AC Switching Characteristics (Over the Operating Range) ............................................. 5 Data Retention Waveform ................................................ 6 Switching Waveforms ...................................................... 6 Read Cycle No. 1 (Address Transition Controlled) ...... 6 Read Cycle No. 2 (OE Controlled) .............................. 6 Write Cycle No. 1 (CE1 or CE2 Controlled) ................ 7 Write Cycle No. 2 (WE Controlled, OE LOW) ............. 7 Write Cycle No. 3 (BHE/BLE Controlled) .................... 8 Truth Table ........................................................................ 8 Ordering Information ........................................................ 9 Ordering Code Definitions ........................................... 9 Package Diagrams .......................................................... 10 Document History Page ................................................. 12 Sales, Solutions, and Legal Information ...................... 13 Worldwide Sales and Design Support ....................... 13 Products .................................................................... 13 PSoC Solutions ......................................................... 13 Document #: 38-05256 Rev. *J Page 2 of 13 [+] Feedback CY7C1061AV33 Selection Guide –10 Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current Commercial Industrial Commercial/Industrial 10 275 275 50 mA Unit ns mA Pin Configurations [1, 2] 60-ball FBGA Top View 4 3 54-pin TSOP II (Top View) 1 2 5 6 NC NC NC NC NC NC BLE I/O 8 I/O9 VSS VCC I/O14 OE BHE I/O10 I/O11 I/O12 I/O13 A0 A3 A5 A17 NC A14 A12 A9 A1 A4 A6 A7 A16 A15 A13 A10 A2 CE1 I/O1 I/O 3 I/O4 I/O5 WE A11 CE2 I/O0 I/O2 VCC VSS I/O6 I/O7 A19 A B C D E F G H I/O15 DNU A18 A8 I/O 12 VCC I/O 13 I/O 14 VSS I/O 15 A4 A3 A2 A1 A0 BHE CE1 VCC WE CE2 A19 A18 A17 A16 A15 I/O 0 VCC I/O 1 I/O 2 VSS I/O 3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 I/O 11 VSS I/O 10 I/O 9 VCC I/O 8 A5 A6 A7 A8 A9 NC OE VSS DNU BLE A10 A11 A12 A13 A14 I/O 7 VSS I/O 6 I/O 5 VCC I/O 4 NC NC NC NC NC NC Notes 1. NC pins are not connected on the die. 2. DNU (Do Not Use) pins have to be left floating or tied to VSS to ensure proper operation. Document #: 38-05256 Rev. *J Page 3 of 13 [+] Feedback CY7C1061AV33 DC Input Voltage [3] ............................. –0.5 V to VCC + 0.5 V Current into Outputs (LOW)......................................... 20 mA Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. These user guidelines are not tested. Storage Temperature ............................... –65 °C to +150 °C Ambient Temperature with Power Applied .......................................... –55 °C to +125 °C Supply Voltage on VCC to Relative GND [3] ..–0.5 V to +4.6 V DC Voltage Applied to Outputs in High-Z State [3] ................................. –0.5 V to VCC + 0.5 V Operating Range Range Commercial Industrial Ambient Temperature 0 °C to +70 °C –40 °C to +85 °C VCC 3.3 V ± 0.3 V DC Electrical Characteristics (Over the Operating Range) Parameter VOH VOL VIH VIL IIX IOZ ICC ISB1 ISB2 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage [3] Input Leakage Current Output Leakage Current VCC Operating Supply Current Automatic CE Power-down Current —TTL Inputs Automatic CE Power-down Current —CMOS Inputs GND < VI < VCC GND < VO < VCC, Output Disabled VCC = max, f = fmax = 1/tRC Commercial Industrial Test Conditions IOH = –4.0 mA IOL = 8.0 mA 2.0 –0.3 –1 –1 –10 Min 2.4 0.4 VCC + 0.3 0.8 +1 +1 275 275 70 Max Unit V V V V μA μA mA mA mA CE2 VIH VIN > VIH or VIN < VIL, f = fmax CE2 VCC – 0.3 V, VIN > VCC – 0.3 V, or VIN < 0.3 V, f = 0 Commercial/ Industrial 50 mA Capacitance [4] Parameter CIN COUT Description Input Capacitance I/O Capacitance Test Conditions TA = 25 °C, f = 1 MHz, VCC = 3.3 V TSOP II 6 8 FBGA 8 10 Unit pF pF AC Test Loads and Waveforms [5] 50Ω OUTPUT Z0 = 50Ω VTH = 1.5 V 30 pF* * Capacitive Load consists of all components of the test environment. 3.3 V OUTPUT 5 pF* INCLUDING JIG AND SCOPE (b) R2 351Ω R1 317 Ω (a) ALL INPUT PULSES 3.3 V 90% GND Rise time > 1 V/ns 10% 90% 10% Fall time: > 1 V/ns (c) Notes 3. VIL (min) = –2.0 V for pulse durations of less than 20 ns. 4. Tested initially and after any design or process changes that may affect these parameters. 5. Valid SRAM operation does not occur until the power supplies have reached the minimum operating VDD (3.0 V). As soon as 1 ms (Tpower) after reaching the minimum operating VDD, normal SRAM operation can begin including reduction in VDD to the data retention (VCCDR, 2.0 V) voltage. Document #: 38-05256 Rev. *J Page 4 of 13 [+] Feedback CY7C1061AV33 AC Switching Characteristics (Over the Operating Range) [6] Parameter Read Cycle tpower tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE Write Cycle [10, 11] tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE tBW Write Cycle Time CE1 LOW/CE2 HIGH to Write End Address Setup to Write End Address Hold from Write End Address Setup to Write Start WE Pulse Width Data Setup to Write End Data Hold from Write End WE HIGH to Low-Z WE LOW to High-Z [8] [8] Description –10 Min 1 10 10 3 10 5 1 5 Max Unit VCC(typical) to the first access [7] Read Cycle Time Address to Data Valid Data Hold from Address Change CE1 LOW/CE2 HIGH to Data Valid OE LOW to Data Valid OE LOW to Low-Z OE HIGH to High-Z [8] CE1 LOW/CE2 HIGH to Low-Z CE1 HIGH/CE2 LOW to High-Z [8] [8] [9] ms ns ns ns ns ns ns ns ns 5 ns ns 10 5 ns ns ns 5 ns ns ns ns ns ns ns ns ns ns 5 ns ns 3 0 CE1 LOW/CE2 HIGH to Power Up Byte Enable to Data Valid Byte Enable to Low-Z Byte Disable to High-Z CE1 HIGH/CE2 LOW to Power Down [9] 1 10 7 7 0 0 7 5.5 0 3 7 Byte Enable to End of Write Notes 6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified IOL/IOH and specified transmission line loads. Test conditions for the Read cycle use output loading shown in (a) of the “AC Test Loads and Waveforms [5]” on page 4, unless specified otherwise. 7. This part has a voltage regulator that steps down the voltage from 3 V to 2 V internally. tpower time must be provided initially before a Read/Write operation is started. 8. tHZOE, tHZCE, tHZWE, tHZBE and tLZOE, tLZCE, t\LZWE, tLZBE are specified with a load capacitance of 5 pF as in (b) of “AC Test Loads and Waveforms [5]” on page 4. Transition is measured ±200 mV from steady-state voltage. 9. These parameters are guaranteed by design and are not tested. 10. The internal Write time of the memory is defined by the overlap of CE1 LOW (CE2 HIGH) and WE LOW. Chip enables must be active and WE and byte enables must be LOW to initiate a Write, and the transition of any of these signals can terminate the Write. The input data setup and hold timing should be referenced to the leading edge of the signal that terminates the Write. 11. The minimum Write cycle time for Write Cycle No. 2 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document #: 38-05256 Rev. *J Page 5 of 13 [+] Feedback CY7C1061AV33 Data Retention Waveform DATA RETENTION MODE VCC 3.0 V tCDR CE VDR > 2 V 3.0 V tR Switching Waveforms Read Cycle No. 1 (Address Transition Controlled) [12, 13] tRC RC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Read Cycle No. 2 (OE Controlled) [13, 14] ADDRESS tRC CE1 tPD CE2 tACE BHE/BLE tDBE tLZBE OE tHZOE tDOE DATA OUT tLZOE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% 50% ISB ICC HIGH IMPEDANCE DATA VALID tHZBE tHZCE Notes 12. Device is continuously selected. OE, CE, BHE or BHE, or both = VIL. CE2 = VIH. 13. WE is HIGH for Read cycle. 14. Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH. Document #: 38-05256 Rev. *J Page 6 of 13 [+] Feedback CY7C1061AV33 Switching Waveforms (continued) Write Cycle No. 1 (CE1 or CE2 Controlled) [15, 16] tWC ADDRESS tSCE CE1 CE2 tSA tAW tPWE tHA WE BHE/BLE tBW OE tSD DATA IO NOTE 17 tHZOE VALID DATA tHD Write Cycle No. 2 (WE Controlled, OE LOW) [15, 16] tWC ADDRESS tSCE CE1 CE2 BHE/BLE tBW tAW tSA WE tPWE tHA tSD DATA IO NOTE 17 VALID DATA tHD tHZWE Notes 15. Data IO is high impedance if OE, or BHE or BLE or both = VIH. 16. If CE1 goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state. 17. During this period, the IOs are in output state and input signals should not be applied. tLZWE Document #: 38-05256 Rev. *J Page 7 of 13 [+] Feedback CY7C1061AV33 Switching Waveforms (continued) Write Cycle No. 3 (BHE/BLE Controlled) tWC ADDRESS CE1 CE2 tSCE tAW BHE/BLE tSA WE tPWE tSD DATA IO NOTE 18 VALID DATA tHD tBW tHA Truth Table CE1 H X L L L L L L L CE2 X L H H H H H H H OE X X L L L X X X H WE X X H H H L L L H BLE X X L L H L L H X BHE X X L H L L H L X I/O0–I/O7 High-Z High-Z Data Out Data Out High-Z Data In Data In High-Z High-Z I/O8–I/O15 High-Z High-Z Data Out High-Z Data Out Data In High-Z Data In High-Z Power Down Power Down Read All Bits Read Lower Bits Only Read Upper Bits Only Write All Bits Write Lower Bits Only Write Upper Bits Only Selected, Outputs Disabled Mode Power Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Note 18. During this period, the IOs are in output state and input signals should not be applied. Document #: 38-05256 Rev. *J Page 8 of 13 [+] Feedback CY7C1061AV33 Ordering Information The following table lists the CY7C1061AV33 key package features and ordering codes. The table contains only the parts that are currently available. If you do not see what you are looking for, contact your local sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products. Speed (ns) 10 Ordering Code CY7C1061AV33-10ZXC CY7C1061AV33-10ZXI CY7C1061AV33-10BAXI Package Diagram 51-85160 51-85160 51-85162 Package Type 54-pin TSOP II (Pb-free) 54-pin TSOP II (Pb-free) 60-ball FBGA (Pb-free) Operating Range Commercial Industrial Ordering Code Definitions CY 7 C 1 06 1 A V33 - 10 XXX X Temperature Range: X = C or I C = Commercial; I = Industrial Package Type: XXX = ZX or BAX ZX = 54-pin TSOP II (Pb-free) BAX = 60-ball FBGA (Pb-free) Speed: 10 ns V33 = Voltage range (3 V to 3.6 V) A = 0.16 µm Technology 1 = Data width × 16-bits 06 = 16-Mbit density 1 = Fast Asynchronous SRAM family Technology Code: C = CMOS 7 = SRAM CY = Cypress Document #: 38-05256 Rev. *J Page 9 of 13 [+] Feedback CY7C1061AV33 Package Diagrams Figure 1. 54-pin TSOP II, 51-85160 51-85160 *A Document #: 38-05256 Rev. *J Page 10 of 13 [+] Feedback CY7C1061AV33 Package Diagrams (continued) Figure 2. 60-ball FBGA (8 × 20 × 1.2 mm), 51-85162 51-85162 *E Document #: 38-05256 Rev. *J Page 11 of 13 [+] Feedback CY7C1061AV33 Document History Page Document Title: CY7C1061AV33 16-Mbit (1 M × 16) Static RAM Document Number: 38-05256 Revision ** *A *B ECN 113725 117058 117989 Submission Date 03/28/02 07/31/02 08/30/02 Orig. of Change NSL DFP DFP New Data Sheet Removed 15-ns bin Added 8-ns bin Changed Icc for 8, 10, 12 bins tpower changed from 1 μs to 1 ms. Load Cap Comment changed (for Tx line load) tSD changed to 5.5 ns for the 10-ns bin Changed some 8-ns bin numbers (tHZ, tDOE, tDBE) Removed hz