CY7C1061AV33-8ZI

CY7C1061AV33 1M x 16 Static RAM Features • High speed — tAA = 8, 10, 12 ns • Low active power — 1080 mW (max.) • Operating voltages of 3.3 ± 0.3V • 2.0V data retention • Automatic power-down when deselected • TTL-compatible inputs and outputs • Easy memory expansion with CE1 and CE2 features specified on the address pins (A0 through A19). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A19). Reading from the device is accomplished by enabling the chip by taking CE1 LOW and CE2 HIGH while forcing the Output Enable (OE) LOW and the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this data sheet for a complete description of Read and Write modes. The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when the device is deselected (CE1 HIGH/CE2 LOW), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a Write operation (CE1 LOW, CE2 HIGH, and WE LOW). The CY7C1061AV33 is available in a 54-pin TSOP II package with center power and ground (revolutionary) pinout, and a 48-ball fine-pitch ball grid array (FBGA) package. Functional Description The CY7C1061AV33 is a high-performance CMOS Static RAM organized as 1,048,576 words by 16 bits. Writing to the device is accomplished by enabling the chip (CE1 LOW and CE2 HIGH) while forcing the Write Enable (WE) input LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location Logic Block Diagram INPUT BUFFER Pin Configuration TSOP II (Top View) I/O12 VCC I/O13 I/O14 VSS I/O15 A4 A3 A2 A1 A0 BHE CE1 VCC WE CE2 A19 A18 A17 A16 A15 I/O0 VCC I/O1 I/O2 VSS I/O3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 1M x 16 ARRAY 4096 x 4096 I/O0–I/O7 I/O8–I/O15 COLUMN DECODER BHE WE CE2 CE1 OE BLE I/O11 VSS I/O10 I/O9 VCC I/O8 A5 A6 A7 A8 A9 NC OE VSS DNU (Do Not Use) BLE A10 A11 A12 A13 A14 I/O7 VSS I/O6 I/O5 VCC I/O4 ROW DECODER Selection Guide -8 Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current Commercial Industrial Commercial/Industrial 8 300 300 50 -10 10 275 275 50 -12 12 260 260 50 mA Unit ns mA Cypress Semiconductor Corporation Document #: 38-05256 Rev. *D A10 A11 A 12 A 13 A 14 A15 A16 A17 A18 A19 SENSE AMPS • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised February 21, 2003 CY7C1061AV33 Pin Configurations 48-ball FBGA 1 BLE I/O8 I/O9 VSS VCC I/O14 2 OE BHE I/O10 (Top View) 4 3 A0 A3 A5 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CE1 I/O1 6 CE2 I/O0 I/O2 A B C D E F G H I/O11 A17 I/O12 I/O13 NC A14 A12 A9 I/O 3 VCC I/O4 I/O5 WE A11 VSS I/O6 I/O7 A19 I/O15 DNU A18 A8 Document #: 38-05256 Rev. *D Page 2 of 11 CY7C1061AV33 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage on VCC to Relative GND[1] .... –0.5V to +4.6V DC Voltage Applied to Outputs in High-Z State[1] ....................................–0.5V to VCC + 0.5V DC Input Voltage[1] ................................ –0.5V to VCC + 0.5V Current into Outputs (LOW)......................................... 20 mA Operating Range Range Commercial Industrial Ambient Temperature 0°C to +70°C –40°C to +85°C VCC 3.3V ± 0.3V DC Electrical Characteristics Over the Operating Range -8 Parameter VOH VOL VIH VIL IIX IOZ ICC ISB1 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[1] Input Load Current VCC Operating Supply Current Automatic CE Power-down Current — TTL Inputs Automatic CE Power-down Current — CMOS Inputs GND < VI < VCC VCC = Max., f = fMAX = 1/tRC CE2 VIH VIN > VIH or VIN < VIL, f = fMAX CE2 VCC – 0.3V, VIN > VCC – 0.3V, or VIN < 0.3V, f = 0 Commercial/ Industrial Commercial Industrial Output Leakage Current GND < VOUT < VCC, Output Disabled Test Conditions VCC = Min., IOH = –4.0 mA VCC = Min., IOL = 8.0 mA 2.0 –0.3 –1 –1 2.4 0.4 VCC + 0.3 0.8 +1 +1 300 300 70 2.0 –0.3 –1 –1 2.4 0.4 VCC + 0.3 0.8 +1 +1 275 275 70 2.0 –0.3 –1 –1 -10 2.4 0.4 VCC + 0.3 0.8 +1 +1 260 260 70 -12 V V V V µA µA mA mA mA Min. Max. Min. Max. Min. Max. Unit ISB2 50 50 50 mA Capacitance[2] Parameter CIN Package Z54 BA48 COUT Z54 BA48 Notes: 1. VIL (min.) = –2.0V for pulse durations of less than 20 ns. 2. Tested initially and after any design or process changes that may affect these parameters. Description Input Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 3.3V Max. 6 8 Unit pF pF pF pF I/O Capacitance 8 10 Document #: 38-05256 Rev. *D Page 3 of 11 CY7C1061AV33 AC Test Loads and Waveforms[3] 50Ω OUTPUT Z0 = 50Ω 30 pF* VTH = 1.5V 3.3V OUTPUT 5 pF* INCLUDING JIG AND SCOPE (b) R2 351Ω R1 317 Ω (a) * Capacitive Load consists of all components of the test environment. ALL INPUT PULSES 3.3V 90% GND Rise time > 1V/ns 10% 90% 10% Fall time: > 1V/ns (c) AC Switching Characteristics Over the Operating Range Parameter Read Cycle tpower tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE Write tWC tSCE Cycle[8, 9] Write Cycle Time CE1 LOW/CE2 HIGH to Write End VCC(typical) to the first access[5] Read Cycle Time Address to Data Valid Data Hold from Address Change CE1 LOW / CE2 HIGH to Data Valid OE LOW to Data Valid OE LOW to Low-Z OE HIGH to High-Z[6] Low-Z[6] Power-Up[7] Power-Down[7] CE1 LOW/CE2 HIGH to CE1 LOW/CE2 HIGH to CE1 HIGH/CE2 LOW to Byte Enable to Low-Z Byte Disable to High-Z Description [4] -8 Min. 1 8 8 3 8 5 1 5 3 5 0 8 5 1 5 8 6 10 7 1 0 3 1 3 Max. Min. 1 10 -10 Max. Min. 1 12 10 3 10 5 1 5 3 5 0 10 5 1 5 12 8 -12 Max. Unit ms ns 12 12 6 6 6 12 6 6 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns CE1 HIGH/CE2 LOW to High-Z[6] Byte Enable to Data Valid Notes: 3. Valid SRAM operation does not occur until the power supplies have reached the minimum operating VDD (3.0V). As soon as 1ms (Tpower) after reaching the minimum operating VDD, normal SRAM operation can begin including reduction in VDD to the data retention (VCCDR, 2.0V) voltage. 4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and specified transmission line loads. Test conditions for the Read cycle use output loading shown in part a) of the AC test loads, unless specified otherwise. 5. This part has a voltage regulator which steps down the voltage from 3V to 2V internally. tpower time has to be provided initially before a Read/Write operation is started. 6. tHZOE, tHZCE, tHZWE, tHZBE and tLZOE, tLZCE, t\LZWE, tLZBE are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured ±200 mV from steady-state voltage. 7. These parameters are guaranteed by design and are not tested. 8. The internal Write time of the memory is defined by the overlap of CE1 LOW (CE2 HIGH) and WE LOW. Chip enables must be active and WE and byte enables must be LOW to initiate a Write, and the transition of any of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write. 9. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document #: 38-05256 Rev. *D Page 4 of 11 CY7C1061AV33 AC Switching Characteristics Over the Operating Range (continued)[4] -8 Parameter tAW tHA tSA tPWE tSD tHD tLZWE tHZWE tBW Description Address Set-up to Write End Address Hold from Write End Address Set-up to Write Start WE Pulse Width Data Set-up to Write End Data Hold from Write End WE HIGH to Low-Z WE LOW to High-Z [6] [6] -10 Max. Min. 7 0 0 7 5.5 0 3 5 5 7 8 Max. Min. 8 0 0 8 6 0 3 -12 Max. Unit ns ns ns ns ns ns ns 6 ns ns Min. 6 0 0 6 5 0 3 6 Byte Enable to End of Write Data Retention Waveform DATA RETENTION MODE VCC 3.0V tCDR CE VDR > 2V 3.0V tR Switching Waveforms Read Cycle No. 1[10, 11] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Notes: 10. Device is continuously selected. OE, CE, BHE and/or BHE = VIL. CE2 = VIH. 11. WE is HIGH for Read cycle. Document #: 38-05256 Rev. *D Page 5 of 11 CY7C1061AV33 Switching Waveforms (continued) Read Cycle No. 2 (OE Controlled)[11, 12] ADDRESS tRC CE1 CE2 tACE OE BHE, BLE tDOE tLZOE tDBE tLZBE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% tHZCE tHZBE DATA VALID tPD 50% ISB IICC CC tHZOE HIGH IMPEDANCE DATA OUT Write Cycle No. 1 (CE Controlled) [13, 14, 15] tWC ADDRESS CE tSA tSCE tAW tPWE WE t BW BHE, BLE tSD DATAI/O tHD tHA Notes: 12. Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH. 13. Data I/O is high-impedance if OE or BHE and/or BLE = VIH. 14. If CE1 goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. 15. CE is a shorthand combination of both CE1 and CE2 combined. It is active LOW. Document #: 38-05256 Rev. *D Page 6 of 11 CY7C1061AV33 Switching Waveforms (continued) Write Cycle No. 2 (BLE or BHE Controlled) tWC ADDRESS BHE, BLE tSA tBW tAW tPWE WE tSCE CE tSD DATAI/O tHD tHA Write Cycle No.3 (WE Controlled, OE LOW) ADDRESS [13, 14, 15] tWC CE tSCE tAW tSA tPWE tHA WE tBW BHE, BLE tHZWE DATA I/O tLZWE tSD tHD Document #: 38-05256 Rev. *D Page 7 of 11 CY7C1061AV33 Truth Table CE1 H X L L L L L L L CE2 X L H H H H H H H OE X X L L L X X X H WE X X H H H L L L H BLE X X L L H L L H X BHE X X L H L L H L X I/O0–I/O7 High-Z High-Z Data Out Data Out High-Z Data In Data In High-Z High-Z I/O8–I/O15 High-Z High-Z Data Out High-Z Data Out Data In High-Z Data In High-Z Power-down Power-down Read All Bits Read Lower Bits Only Read Upper Bits Only Write All Bits Write Lower Bits Only Write Upper Bits Only Selected, Outputs Disabled Mode Power Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Ordering Information Speed (ns) 8 Ordering Code[16] CY7C1061AV33-8ZC CY7C1061AV33-8ZI CY7C1061AV33-8BAC CY7C1061AV33-8BAI CY7C1061AV33-10ZC CY7C1061AV33-10ZI CY7C1061AV33-10BAC CY7C1061AV33-10BAI CY7C1061AV33-12ZC CY7C1061AV33-12ZI CY7C1061AV33-12BAC CY7C1061AV33-12BAI Package Name Z54-II BA48G Z54-II BA48G Z54-II BA48G Package Type 54-pin TSOP II 48-ball Mini BGA 54-pin TSOP II 48-ball Mini BGA 54-pin TSOP II 48-ball Mini BGA Operating Range Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial 10 12 Note: 16. Contact a Cypress representative for availability of the 48-ball Mini BGA (BA48) package. Document #: 38-05256 Rev. *D Page 8 of 11 CY7C1061AV33 Package Diagrams 54-lead Thin Small Outline Package, Type II Z54-II 51-85160-** Document #: 38-05256 Rev. *D Page 9 of 11 CY7C1061AV33 Package Diagrams (continued) 48-ball (8 mm x 20 mm x 1.2 mm) FBGA BA48G 51-85162-*A All products and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05256 Rev. *D Page 10 of 11 © Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C1061AV33 Document History Page Document Title: CY7C1061AV33 1M x 16 Static RAM Document Number: 38-05256 REV. ** *A *B ECN NO. 113725 117058 117989 Issue Date 03/28/02 07/31/02 08/30/02 Orig. of Change NSL DFP DFP New Data Sheet Removed 15-ns bin. Added 8-ns bin. Changed Icc for 8, 10, 12 bins. tpower changed from 1 µs to 1 ms. Load Cap Comment changed (for Tx line load). tSD changed to 5.5 ns for the 10-ns bin. Changed some 8-ns bin numbers (tHZ, tDOE, tDBE). Removed hz