CY7C1061BV33-8ZC

CY7C1061BV33 16-Mbit (1M x 16) Static RAM Features Functional Description • High speed The CY7C1061BV33 is a high-performance CMOS Static RAM organized as 1,048,576 words by 16 bits. — tAA = 8, 10, 12 ns Writing to the device is accomplished by enabling the chip (CE LOW) while forcing the Write Enable (WE) input LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A19). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A19). • Low active power — 1080 mW (max.) • Operating voltages of 3.3 ± 0.3V • 2.0V data retention • Automatic power-down when deselected • TTL-compatible inputs and outputs Reading from the device is accomplished by enabling the chip by taking CE LOW while forcing the Output Enable (OE) LOW and the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this data sheet for a complete description of Read and Write modes. The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a Write operation (CE LOW and WE LOW). The CY7C1061BV33 is available in a 54-pin TSOP II package with center power and ground (revolutionary) pinout. Logic Block Diagram 1M x 16 ARRAY 4096 x 4096 SENSE AMPS A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 ROW DECODER INPUT BUFFER I/O0–I/O7 I/O8–I/O15 A10 A11 A 12 A 13 A 14 A15 A16 A17 A18 A19 COLUMN DECODER BHE WE CE OE BLE Cypress Semiconductor Corporation Document #: 38-05693 Rev. *A • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised January 12, 2005 CY7C1061BV33 Selection Guide -8 Maximum Access Time -10 -12 Unit 8 10 12 ns Maximum Operating Current Commercial 300 275 260 mA Industrial 300 275 260 Maximum CMOS Standby Current Commercial/Industrial 50 50 50 mA Pin Configurations[1,2] 54-pin TSOP II (Top View) I/O12 VCC I/O13 I/O14 VSS I/O15 A4 A3 A2 A1 A0 BHE CE VCC WE DNU / VCC A19 A18 A17 A16 A15 I/O0 VCC I/O1 I/O2 VSS I/O3 1 2 3 54 53 4 52 51 5 6 50 49 7 8 9 10 11 12 48 47 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 I/O11 VSS I/O10 I/O9 VCC I/O8 A5 A6 A7 A8 A9 NC OE VSS DNU / VSS BLE A10 A11 A12 A13 A14 I/O7 VSS I/O6 I/O5 VCC I/O4 Notes: 1. DNU / VCC Pin (#16) has to be left floating or connected to VCC and DNU / VSS Pin (#40) has to be left floating or connected to VSS to ensure proper application. 2. NC – No Connect Pins are not connected to the die. Document #: 38-05693 Rev. *A Page 2 of 10 CY7C1061BV33 Maximum Ratings DC Voltage Applied to Outputs in High-Z State[3].................................... –0.5V to VCC + 0.5V (Above which the useful life may be impaired. For user guidelines, not tested.) DC Input Voltage[3] ................................ –0.5V to VCC + 0.5V Current into Outputs (LOW)......................................... 20 mA Storage Temperature ................................. –65°C to +150°C Operating Range Ambient Temperature with Power Applied............................................. –55°C to +125°C Range Supply Voltage on VCC to Relative GND[3] .... –0.5V to +4.6V Ambient Temperature VCC 0°C to +70°C 3.3V ± 0.3V Commercial Industrial –40°C to +85°C DC Electrical Characteristics Over the Operating Range -8 Parameter Description Test Conditions -10 -12 Min. Max. Min. Max. Min. Max. Unit VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA 2.4 2.4 VIH Input HIGH Voltage 2.0 VCC + 0.3 2.0 VCC + 0.3 VIL Input LOW Voltage[3] –0.3 0.8 –0.3 IIX Input Load Current GND < VI < VCC –1 +1 IOZ Output Leakage Current GND < VOUT < VCC, Output Disabled –1 +1 ICC VCC Operating Supply Current VCC = Max., f = fMAX = 1/tRC ISB1 Automatic CE Power-down Current —TTL Inputs Max. VCC, CE > VIH VIN > VIH or VIN < VIL, f = fMAX ISB2 Automatic CE Power-down Current —CMOS Inputs Max. VCC, CE > VCC – 0.3V, VIN > VCC – 0.3V, or VIN < 0.3V, f = 0 0.4 2.4 0.4 V 0.4 V 2.0 VCC + 0.3 V 0.8 –0.3 0.8 V –1 +1 –1 +1 µA –1 +1 –1 +1 µA Commercial 300 275 260 mA Industrial 300 275 260 mA 70 70 70 mA 50 50 50 mA Commercial/ Industrial Capacitance[4] Parameter Package Description CIN Z54 Input Capacitance COUT Z54 I/O Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 3.3V Max. Unit 6 pF 8 pF Thermal Resistance[4] Parameter ΘJA ΘJC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions 54-pin TSOP-II Unit Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA / JESD51. 49.95 °C/W 3.34 °C/W Notes: 3. VIL (min.) = –2.0V and VIH(max) = VCC + 0.5V for pulse durations of less than 20 ns. 4. Tested initially and after any design or process changes that may affect these parameters. 5. Valid SRAM operation does not occur until the power supplies have reached the minimum operating VDD (3.0V). As soon as 1ms (Tpower) after reaching the minimum operating VDD, normal SRAM operation can begin including reduction in VDD to the data retention (VCCDR, 2.0V) voltage. Document #: 38-05693 Rev. *A Page 3 of 10 CY7C1061BV33 AC Test Loads and Waveforms[5] 50Ω VTH = 1.5V OUTPUT Z0 = 50Ω (a) R1 317 Ω 3.3V OUTPUT 30 pF* * Capacitive Load consists of all components of the test environment. R2 351Ω 5 pF* INCLUDING JIG AND SCOPE (b) ALL INPUT PULSES 3.3V 90% GND 90% 10% 10% Fall time: > 1V/ns Rise time > 1V/ns (c) AC Switching Characteristics Over the Operating Range [6] -8 Parameter Description Min. -10 Max. Min. -12 Max. Min. Max. Unit Read Cycle tpower VCC(typical) to the first access[7] 1 tRC Read Cycle Time 8 tAA Address to Data Valid tOHA Data Hold from Address Change 1 1 10 8 3 ms 12 10 3 ns 12 3 ns ns tACE CE LOW to Data Valid 8 10 12 ns tDOE OE LOW to Data Valid 5 5 6 ns tLZOE OE LOW to Low-Z tHZOE OE HIGH to tLZCE CE LOW to Low-Z[8] CE HIGH to High-Z[8] CE LOW to Power-Up[9] tPD CE HIGH to Power-Down[9] tDBE Byte Enable to Data Valid tLZBE Byte Enable to Low-Z tHZBE Byte Disable to High-Z tHZCE tPU 1 High-Z[8] 1 5 3 1 5 3 5 0 ns 6 3 5 0 ns ns 6 0 ns ns 8 10 12 ns 5 5 6 ns 1 1 5 1 5 ns 6 ns Write Cycle[10, 11] tWC Write Cycle Time 8 10 12 ns tSCE CE LOW to Write End 6 7 8 ns Notes: 6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and specified transmission line loads. Test conditions for the Read cycle use output loading shown in part a) of the AC test loads, unless specified otherwise. 7. This part has a voltage regulator which steps down the voltage from 3V to 2V internally. tpower time has to be provided initially before a Read/Write operation is started. 8. tHZOE, tHZCE, tHZWE, tHZBE and tLZOE, tLZCE, t\LZWE, tLZBE are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured ±200 mV from steady-state voltage. 9. These parameters are guaranteed by design and are not tested. 10. The internal Write time of the memory is defined by the overlap of CE LOW and WE LOW. Chip enables must be active and WE and byte enables must be LOW to initiate a Write, and the transition of any of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write. 11. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document #: 38-05693 Rev. *A Page 4 of 10 CY7C1061BV33 AC Switching Characteristics Over the Operating Range (continued)[6] -8 Parameter Description Min. -10 Max. Min. -12 Max. Min. Max. Unit tAW Address Set-up to Write End 6 7 8 ns tHA Address Hold from Write End 0 0 0 ns tSA Address Set-up to Write Start 0 0 0 ns tPWE WE Pulse Width 6 7 8 ns tSD Data Set-up to Write End 5 5.5 6 ns tHD Data Hold from Write End 0 0 0 ns [8] tLZWE WE HIGH to Low-Z tHZWE WE LOW to High-Z[8] 3 tBW Byte Enable to End of Write 3 5 6 3 5 7 ns 6 8 ns ns Data Retention Waveform DATA RETENTION MODE 3.0V VCC VDR > 2V 3.0V tR tCDR CE Switching Waveforms Read Cycle No. 1[12, 13] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Notes: 12. Device is continuously selected. OE, CE, BHE and/or BHE = VIL. 13. WE is HIGH for Read cycle. Document #: 38-05693 Rev. *A Page 5 of 10 CY7C1061BV33 Switching Waveforms (continued) Read Cycle No. 2 (OE Controlled)[13, 14] ADDRESS tRC CE tACE OE tHZOE tDOE BHE, BLE tLZOE tHZCE tDBE tLZBE DATA OUT tHZBE HIGH IMPEDANCE DATA VALID tLZCE VCC SUPPLY CURRENT HIGH IMPEDANCE tPD tPU IICC CC 50% 50% ISB Write Cycle No. 1 (CE Controlled)[15, 16] tWC ADDRESS CE tSA tSCE tAW tHA tPWE WE tBW BHE, BLE tSD tHD DATAI/O Notes: 14. Address valid prior to or coincident with CE transition LOW. 15. Data I/O is high-impedance if OE or BHE and/or BLE = VIH. 16. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. Document #: 38-05693 Rev. *A Page 6 of 10 CY7C1061BV33 Switching Waveforms (continued) Write Cycle No. 2 (BLE or BHE Controlled) tWC ADDRESS tSA BHE, BLE tBW tAW tHA tPWE WE tSCE CE tSD tHD DATAI/O Write Cycle No. 3 (WE Controlled, OE LOW)[15, 16] tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE tBW BHE, BLE tHZWE tSD tHD DATA I/O tLZWE Document #: 38-05693 Rev. *A Page 7 of 10 CY7C1061BV33 Truth Table CE OE WE BLE BHE I/O0–I/O7 I/O8–I/O15 Mode Power H X X X X High-Z High-Z Power-down Standby (ISB) L L H L L Data Out Data Out Read All Bits Active (ICC) L L H L H Data Out High-Z Read Lower Bits Only Active (ICC) L L H H L High-Z Data Out Read Upper Bits Only Active (ICC) L X L L L Data In Data In Write All Bits Active (ICC) L X L L H Data In High-Z Write Lower Bits Only Active (ICC) L X L H L High-Z Data In Write Upper Bits Only Active (ICC) L H H X X High-Z High-Z Selected, Outputs Disabled Active (ICC) Ordering Information Speed (ns) 8 10 12 Ordering Code CY7C1061BV33-8ZC CY7C1061BV33-8ZI CY7C1061BV33-10ZC CY7C1061BV33-10ZI CY7C1061BV33-12ZC CY7C1061BV33-12ZI Document #: 38-05693 Rev. *A Package Name Z54-II Package Type 54-pin TSOP II Z54-II 54-pin TSOP II Z54-II 54-pin TSOP II Operating Range Commercial Industrial Commercial Industrial Commercial Industrial Page 8 of 10 CY7C1061BV33 Package Diagram 54-lead Thin Small Outline Package, Type II Z54-II 51-85160-** All products and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05693 Rev. *A Page 9 of 10 © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY7C1061BV33 Document History Page Document Title: CY7C1061BV33 16-Mbit (1M x 16) Static RAM Document Number: 38-05693 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 283950 See ECN RKF New data sheet *A 309453 See ECN RKF Final data sheet Document #: 38-05693 Rev. *A Page 10 of 10