Please note that Cypress is an Infineon Technologies Company.
The document following this cover page is marked as “Cypress” document as this is the
company that originally developed the product. Please note that Infineon will continue
to offer the product to new and existing customers as part of the Infineon product
portfolio.
Continuity of document content
The fact that Infineon offers the following product as part of the Infineon product
portfolio does not lead to any changes to this document. Future revisions will occur
when appropriate, and any changes will be set out on the document history page.
Continuity of ordering part numbers
Infineon continues to support existing part numbers. Please continue to use the
ordering part numbers listed in the datasheet for ordering.
www.infineon.com
CY7C1061G/CY7C1061GE
16-Mbit (1M words × 16-bit) Static RAM
with Error-Correcting Code (ECC)
16-Mbit (1M words × 16-bit) Static RAM with Error-Correcting Code (ECC)
Features
To access devices with a single chip enable input, assert the chip
enable (CE) input LOW. To access dual chip enable devices,
assert both chip enable inputs – CE1 as LOW and CE2 as HIGH.
■
High speed
❐ tAA = 10 ns/15 ns
■
Embedded error-correcting code (ECC) for single-bit error
correction[1, 2]
■
Low active and standby currents
❐ ICC = 90 mA typical at 100 MHz
❐ ISB2 = 20 mA typical
■
Operating voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V, and
4.5 V to 5.5 V
■
1.0 V data retention
■
Transistor-transistor logic (TTL) compatible inputs and outputs
■
Error indication (ERR) pin to indicate 1-bit error detection and
correction
■
Available in Pb-free 48-pin TSOP I, 54-pin TSOP II, and 48-ball
VFBGA packages
Functional Description
CY7C1061G and CY7C1061GE are high-performance CMOS
fast static RAM devices with embedded ECC[1]. Both devices are
offered in single and dual chip enable options and in multiple pin
configurations. The CY7C1061GE device includes an ERR pin
that signals a single-bit error-detection and correction event
during a read cycle.
To perform data writes, assert the Write Enable (WE) input LOW,
and provide the data and address on the device data pins (I/O0
through I/O15) and address pins (A0 through A19) respectively.
The Byte High Enable (BHE) and Byte Low Enable (BLE) inputs
control byte writes, and write data on the corresponding I/O lines
to the memory location specified. BHE controls I/O8 through
I/O15 and BLE controls I/O0 through I/O7.
To perform data reads, assert the Output Enable (OE) input and
provide the required address on the address lines. Read data is
accessible on I/O lines (I/O0 through I/O15). You can perform
byte accesses by asserting the required byte enable signal (BHE
or BLE) to read either the upper byte or the lower byte of data
from the specified address location.
All I/Os (I/O0 through I/O15) are placed in a high-impedance state
when the device is deselected (CE HIGH for a single chip enable
device and CE1 HIGH / CE2 LOW for a dual chip enable device),
or control signals are de-asserted (OE, BLE, BHE).
On the CY7C1061GE devices, the detection and correction of a
single-bit error in the accessed location is indicated by the
assertion of the ERR output (ERR = High). See the Truth Table
on page 16 for a complete description of read and write modes.
The logic block diagrams are on page 2.
The CY7C1061G and CY7C1061GE devices are available in
48-pin TSOP I, 54-pin TSOP II, and 48-ball VFBGA packages.
For a complete list of related documentation, click here.
Product Portfolio
Current Consumption
Speed Operating ICC, (mA)
(ns)
Standby, ISB2 (mA)
f = fmax
10/15
Typ[3]
Max
Typ[3]
Max
Product
Features and Options
(see Pin Configurations on
page 4)
Range
VCC Range
(V)
CY7C1061G18
Single or dual chip enables
Industrial
1.65 V–2.2 V
15
70
80
2.2 V–3.6 V
10
90
110
4.5 V–5.5 V
10
90
110
CY7C1061G(E)30
CY7C1061G
Optional ERR pins
20
30
Address MSB A19 pin
placement options
compatible with Cypress and
other vendors
Notes
1. This device does not support automatic write-back on error detection.
2. SER FIT Rate 2001 V
Latch-up current .................................................... > 140 mA
Operating Range
Supply voltage
on VCC relative to GND ...................... –0.5 V to VCC + 0.5 V
DC voltage applied to outputs
in High Z State [9] ................................ –0.5 V to VCC + 0.5 V
Grade
Industrial
Ambient Temperature
–40 C to +85 C
VCC
1.65 V to 2.2 V,
2.2 V to 3.6 V,
4.5 V to 5.5 V
DC Electrical Characteristics
Over the operating range of –40 C to 85 C
Parameter
VOH
VOL
VIH[9]
VIL[9]
Description
Output
HIGH
voltage
Test Conditions
10 ns / 15 ns
Min
Typ [10]
Max
1.65 V to 2.2 V VCC = Min, IOH = –0.1 mA
1.4
–
–
2.2 V to 2.7 V VCC = Min, IOH = –1.0 mA
2.0
–
–
2.7 V to 3.0 V VCC = Min, IOH = –4.0 mA
2.2
–
–
3.0 V to 3.6 V VCC = Min, IOH = –4.0 mA
2.4
–
–
4.5 V to 5.5 V VCC = Min, IOH = –4.0 mA
2.4
–
–
4.5 V to 5.5 V VCC = Min, IOH = –0.1 mA
VCC – 0.4 [11]
–
–
Output LOW 1.65 V to 2.2 V VCC = Min, IOL = 0.1 mA
voltage
2.2 V to 2.7 V VCC = Min, IOL = 2 mA
V
–
–
0.2
–
–
0.4
2.7 V to 3.6 V VCC = Min, IOL = 8 mA
–
–
0.4
4.5 V to 5.5 V VCC = Min, IOL = 8 mA
–
–
0.4
Input HIGH 1.65 V to 2.2 V
voltage
2.2 V to 2.7 V
1.4
–
VCC + 0.2
2.0
–
VCC + 0.3
2.7 V to 3.6 V
2.0
–
VCC + 0.3
4.5 V to 5.5 V
2.0
–
VCC + 0.5
Input LOW
voltage
Unit
1.65 V to 2.2 V
–0.2
–
0.4
2.2 V to 2.7 V
–0.3
–
0.6
2.7 V to 3.6 V
–0.3
–
0.8
4.5 V to 5.5 V
–0.5
–
0.8
V
V
V
IIX
Input leakage current
GND < VIN < VCC
–1.0
–
+1.0
A
IOZ
Output leakage current
GND < VOUT < VCC, Output disabled
–1.0
–
+1.0
A
ICC
Operating supply current
VCC = Max, IOUT = 0 mA,
CMOS levels
f = 100 MHz
–
90.0
110.0
mA
f = 66.7 MHz
–
70.0
80.0
ISB1
Automatic CE power down Max VCC, CE > VIH [12],
current – TTL inputs
VIN > VIH or VIN < VIL, f = fMAX
–
–
40.0
mA
ISB2
Automatic CE power down Max VCC, CE > VCC – 0.2 V[12],
current – CMOS inputs
VIN > VCC – 0.2 V or VIN < 0.2 V, f = 0
–
20.0
30.0
mA
Notes
9. VIL(min) = –2.0 V and VIH(max) = VCC + 2 V for pulse durations of less than 20 ns.
10. Typical values are included only for reference and are not guaranteed or tested. Typical values are measured at VCC = 1.8 V (for a VCC range of 1.65 V–2.2 V),
VCC = 3 V (for a VCC range of 2.2 V–3.6 V), and VCC = 5 V (for a VCC range of 4.5 V–5.5 V), TA = 25 °C.
11. This parameter is guaranteed by design and is not tested.
12. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW,
CE is HIGH.
Document Number: 001-81540 Rev. *T
Page 7 of 25
CY7C1061G/CY7C1061GE
Capacitance
Parameter [13]
Description
CIN
Input capacitance
COUT
I/O capacitance
Test Conditions
54-pin TSOP II 48-ball VFBGA 48-pin TSOP I Unit
TA = 25 C, f = 1 MHz, VCC = VCC(typ)
10
10
10
pF
10
10
10
pF
Thermal Resistance
Parameter [13]
Description
Test Conditions
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
54-pin TSOP II 48-ball VFBGA 48-pin TSOP I Unit
Still air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
93.63
31.50
57.99
C/W
21.58
15.75
13.42
C/W
AC Test Loads and Waveforms
Figure 11. AC Test Loads and Waveforms[14]
High-Z Characteristics:
VCC
50
Output
VTH
Z0 = 50
Output
30 pF*
* Including
JIG and
Scope
(b)
All Input Pulses
VHIGH
GND
R2
5 pF*
(a)
* Capacitive load consists
of all components of the
test environment
R1
90%
90%
10%
Rise Time:
> 1 V/ns
10%
Fall Time:
> 1 V/ns
(c)
Parameters
1.8 V
3.0 V
5.0 V
Unit
R1
1667
317
317
R2
1538
351
351
VTH
0.9
1.5
1.5
V
VHIGH
1.8
3
3
V
Notes
13. Tested initially and after any design or process changes that may affect these parameters.
14. Full-device AC operation assumes a 100-µs ramp time from 0 to VCC (min) and 100-µs wait time after VCC stabilizes to its operational value.
Document Number: 001-81540 Rev. *T
Page 8 of 25
CY7C1061G/CY7C1061GE
Data Retention Characteristics
Over the operating range of –40 C to 85 C
Parameter
VDR
Description
Conditions
Min
Max
Unit
1.0
–
V
–
30.0
mA
0
–
ns
VCC > 2.2 V
10.0
–
ns
VCC < 2.2 V
15.0
–
ns
VCC for data retention
[15]
ICCDR
Data retention current
tCDR[16]
Chip deselect to data retention
time
tR[16, 17]
Operation recovery time
VCC = VDR, CE > VCC – 0.2 V ,
VIN > VCC – 0.2 V or VIN < 0.2 V
Data Retention Waveform
Figure 12. Data Retention Waveform [15]
VCC
VCC(min)
tCDR
DATA RETENTION MODE
VDR = 1.0 V
VCC(min)
tR
CE
Notes
15. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW,
CE is HIGH.
16. This parameter is guaranteed by design and is not tested
17. Full-device operation requires linear VCC ramp from VDR to VCC (min) > 100 s or stable at VCC (min) > 100 s.
Document Number: 001-81540 Rev. *T
Page 9 of 25
CY7C1061G/CY7C1061GE
AC Switching Characteristics
Over the operating range of –40 C to 85 C
Parameter [18]
Description
10 ns
15 ns
Unit
Min
Max
Min
Max
–
100.0
–
µs
Read Cycle
tPOWER
VCC (stable) to the first access [19, 20]
100.0
tRC
Read cycle time
10.0
–
15.0
–
ns
tAA
Address to data / ERR valid
–
10.0
–
15.0
ns
tOHA
Data / ERR hold from address change
3.0
–
3.0
–
ns
–
10.0
–
15.0
ns
–
5.0
–
8.0
ns
0
–
1.0
–
ns
tACE
CE LOW to data / ERR valid
tDOE
OE LOW to data / ERR valid
tLZOE
OE LOW to low Z
[21]
[22, 23, 24]
[22, 23, 24]
tHZOE
OE HIGH to high Z
tLZCE
CE LOW to low Z [21, 22, 23, 24]
[21, 22, 23, 24]
tHZCE
CE HIGH to high Z
tPU
CE LOW to power-up [20, 21]
[20, 21]
–
5.0
–
8.0
ns
3.0
–
3.0
–
ns
–
5.0
–
8.0
ns
0
–
0
–
ns
–
10.0
–
15.0
ns
tPD
CE HIGH to power-down
tDBE
Byte enable to data valid
–
5.0
–
8.0
ns
tLZBE
Byte enable to low Z [22, 23]
0
–
1.0
–
ns
–
6.0
–
8.0
ns
10.0
–
15.0
–
ns
tHZBE
Write Cycle
tWC
[22, 23]
Byte disable to high Z
[25, 26]
Write cycle time
[21]
tSCE
CE LOW to write end
tAW
Address setup to write end
7.0
–
12.0
–
ns
7.0
–
12.0
–
ns
tHA
Address hold from write end
0
–
0
–
ns
tSA
Address setup to write start
0
–
tPWE
WE pulse width
7.0
–
0
–
ns
12.0
–
ns
tSD
Data setup to write end
5.0
–
8.0
–
ns
tHD
Data hold from write end
tLZWE
WE HIGH to low Z [22, 23, 24]
tHZWE
WE LOW to high Z
[22, 23, 24]
tBW
Byte Enable to write end
0
–
0
–
ns
3.0
–
3.0
–
ns
–
5.0
–
8.0
ns
7.0
–
12.0
–
ns
Notes
18. Test conditions assume signal transition time (rise/fall) of 3 ns or less, timing reference levels of 1.5 V (for VCC > 3 V) and VCC/2 (for VCC < 3 V), and input pulse
levels of 0 to 3 V (for VCC > 3 V) and 0 to VCC (for VCC < 3V). Test conditions for the read cycle use the output loading, shown in part (a) of Figure 11 on page 8, unless specified
otherwise.
19. tPOWER gives the minimum amount of time that the power supply is at stable VCC until the first memory access is performed.
20. These parameters are guaranteed by design and are not tested.
21. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW,
CE is HIGH.
22. tHZOE, tHZCE, tHZWE, and tHZBE are specified with a load capacitance of 5 pF, as shown in part (b) of Figure 11 on page 8. Hi-Z, Lo-Z transition is measured 200 mV from steady state
voltage.
23. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.
24. Tested initially and after any design or process changes that may affect these parameters.
25. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL, and BHE or BLE = VIL. These signals must be LOW to initiate a write, and the
HIGH transition of any of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates
the write.
26. The minimum write pulse width for Write Cycle No. 2 (WE Controlled, OE LOW) should be sum of tHZWE and tSD.
Document Number: 001-81540 Rev. *T
Page 10 of 25
CY7C1061G/CY7C1061GE
Switching Waveforms
Figure 13. Read Cycle No. 1 of CY7C1061G (Address Transition Controlled) [27, 28]
tRC
ADDRESS
tAA
tOHA
DATA I/O
PREVIOUS DATAOUT
VALID
DATAOUT VALID
Figure 14. Read Cycle No. 2 of CY7C1061GE (Address Transition Controlled) [27, 28]
tRC
ADDRESS
tAA
tOHA
DATA I/O
PREVIOUS DATAOUT
VALID
DATAOUT VALID
tAA
tOHA
ERR
PREVIOUS ERR VALID
ERR VALID
Notes
27. The device is continuously selected, OE = VIL, CE = VIL, BHE or BLE or both = VIL.
28. WE is HIGH for read cycle.
Document Number: 001-81540 Rev. *T
Page 11 of 25
CY7C1061G/CY7C1061GE
Switching Waveforms (continued)
Figure 15. Read Cycle No. 3 (OE Controlled) [29, 30, 31]
ADDRESS
tRC
CE
tPD
tHZCE
tACE
OE
tHZOE
tDOE
tLZOE
BHE/
BLE
tDBE
tLZBE
DATA I/O
HIGH IMPEDANCE
tHZBE
HIGH
IMPEDANCE
DATAOUT VALID
tLZCE
VCC
SUPPLY
CURRENT
tPU
ICC
ISB
Notes
29. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW,
CE is HIGH.
30. WE is HIGH for read cycle.
31. Address valid prior to or coincident with CE LOW transition.
Document Number: 001-81540 Rev. *T
Page 12 of 25
CY7C1061G/CY7C1061GE
Switching Waveforms (continued)
Figure 16. Write Cycle No. 1 (CE Controlled) [32, 33, 34]
tW C
ADDRESS
t SA
tSCE
CE
tAW
tHA
tPW E
WE
tBW
BHE/
BLE
OE
tHZOE
DATA I/O
t HD
tSD
Note 36
DATA IN VALID
Figure 17. Write Cycle No. 2 (WE Controlled, OE LOW) [32, 33, 34, 35]
tWC
ADDRESS
tSCE
CE
tBW
BHE/
BLE
tSA
tAW
tHA
tPWE
WE
tHZWE
DATA I/O
Note 36
tSD
tLZWE
tHD
DATAIN VALID
Notes
32. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW,
CE is HIGH.
33. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL and BHE or BLE = VIL. These signals must be LOW to initiate a write, and the
HIGH transition of any of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates
the write.
34. Data I/O is in high-impedance state if CE = VIH, or OE = VIH or BHE, and/or BLE = VIH.
35. The minimum write cycle pulse width should be equal to sum of tHZWE and tSD.
36. During this period the I/Os are in output state. Do not apply input signals.
Document Number: 001-81540 Rev. *T
Page 13 of 25
CY7C1061G/CY7C1061GE
Switching Waveforms (continued)
Figure 18. Write Cycle No. 3 (WE Controlled) [37, 38, 39]
tW C
ADDRESS
tS C E
CE
tA W
tS A
tH A
tP W E
WE
tB W
B H E /B L E
OE
tH Z O E
D A T A I/O
Note40
tH D
tS D
D A T A IN V A L ID
Notes
37. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW,
CE is HIGH.
38. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL and BHE or BLE = VIL. These signals must be LOW to initiate a write, and the
HIGH transition of any of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates
the write.
39. Data I/O is in high-impedance state if CE = VIH, or OE = VIH or BHE, and/or BLE = VIH.
40. During this period, the I/Os are in output state. Do not apply input signals.
Document Number: 001-81540 Rev. *T
Page 14 of 25
CY7C1061G/CY7C1061GE
Switching Waveforms (continued)
Figure 19. Write Cycle No. 4 (BLE or BHE Controlled) [41, 42, 43]
tWC
ADDRESS
tSCE
CE
tAW
tSA
tHA
tBW
BHE/
BLE
tPWE
WE
tHZWE
DATA I/O
Note 44
tSD
tHD
tLZWE
DATAIN VALID
Notes
41. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW,
CE is HIGH.
42. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL and BHE or BLE = VIL. These signals must be LOW to initiate a write, and the
HIGH transition of any of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates
the write.
43. Data I/O is in high-impedance state if CE = VIH, or OE = VIH or BHE, and/or BLE = VIH.
44. During this period, the I/Os are in output state. Do not apply input signals.
Document Number: 001-81540 Rev. *T
Page 15 of 25
CY7C1061G/CY7C1061GE
Truth Table
CE [45] OE
H
[46]
X
WE
BLE
BHE
[46]
[46]
[46]
High-Z
High-Z
Power down
Standby (ISB)
X
X
X
I/O0–I/O7
I/O8–I/O15
Mode
Power
L
L
H
L
L
Data out
Data out
Read all bits
Active (ICC)
L
L
H
L
H
Data out
High-Z
Read lower bits only
Active (ICC)
L
L
H
H
L
High-Z
Data out
Read upper bits only
Active (ICC)
L
X
L
L
L
Data in
Data in
Write all bits
Active (ICC)
L
X
L
L
H
Data in
High-Z
Write lower bits only
Active (ICC)
L
X
L
H
L
High-Z
Data in
Write upper bits only
Active (ICC)
L
H
H
X
X
High-Z
High-Z
Selected, outputs disabled
Active (ICC)
L
X
X
H
H
High-Z
High-Z
Selected, outputs disabled
Active (ICC)
ERR Output – CY7C1061GE
Output [47]
0
Mode
Read operation, no single-bit error in the stored data.
1
Read operation, single-bit error detected and corrected.
High-Z
Device deselected or outputs disabled or Write operation
Notes
45. For all dual chip enable devices, CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW,
CE is HIGH.
46. The input voltage levels on these pins should be either at VIH or VIL.
47. ERR is an Output pin. If not used, this pin should be left floating.
Document Number: 001-81540 Rev. *T
Page 16 of 25
CY7C1061G/CY7C1061GE
Ordering Information
Speed
(ns)
10
Voltage
Range
Ordering Code
4.5 V–5.5 V CY7C1061G-10BV1XI
CY7C1061GE-10BV1XI
CY7C1061G-10BVJXI
CY7C1061GE-10BVJXI
CY7C1061G-10BVXI
CY7C1061GE-10BVXI
CY7C1061G-10ZSXI
Package Package Type
Diagram (all Pb-free)
Key Features /
Differentiators
51-85150 48-ball VFBGA Single Chip Enable,
Address MSB A19 at ball G2
Dual Chip Enable,
Address MSB A19 at ball G2
Dual Chip Enable,
Address MSB A19 at ball H6
51-85160 54-pin TSOP II Dual Chip Enable
CY7C1061GE-10ZSXI
CY7C1061G-10ZXI
CY7C1061GE30-10BV1XI
CY7C1061G30-10BVJXI
CY7C1061GE30-10BVJXI
CY7C1061G30-10BVXI
CY7C1061GE30-10BVXI
CY7C1061G30-10ZSXI
51-85183 48-pin TSOP I Single Chip Enable
51-85150 48-ball VFBGA Single Chip Enable,
Address MSB A19 at ball G2
Dual Chip Enable,
Address MSB A19 at ball G2
Dual Chip Enable,
Address MSB A19 at ball H6
51-85160 54-pin TSOP II Dual Chip Enable
1.65 V–2.2 V CY7C1061GE18-15BV1XI
CY7C1061G18-15BV1XI
CY7C1061GE18-15BVJXI
CY7C1061G18-15BVJXI
CY7C1061GE18-15BVXI
CY7C1061G18-15BVXI
CY7C1061GE18-15ZSXI
51-85183 48-pin TSOP I Single Chip Enable
CY7C1061G18-15ZXI
Document Number: 001-81540 Rev. *T
No
Yes
No
Yes
No
No
No
Yes
No
Yes
No
Yes
No
No
Yes
51-85150 48-ball VFBGA Single Chip Enable,
Address MSB A19 at ball G2
Yes
Dual Chip Enable,
Address MSB A19 at ball G2
Yes
Dual Chip Enable,
Address MSB A19 at ball H6
Yes
51-85160 54-pin TSOP II Dual Chip Enable
CY7C1061G18-15ZSXI
CY7C1061GE18-15ZXI
Yes
Yes
CY7C1061GE30-10ZXI
15
Industrial
Yes
CY7C1061GE30-10ZSXI
CY7C1061G30-10ZXI
No
Yes
CY7C1061GE-10ZXI
2.2 V–3.6 V CY7C1061G30-10BV1XI
ERR Pin / Operating
Ball
Range
No
No
No
Yes
No
51-85183 48-pin TSOP I Single Chip Enable
Yes
No
Page 17 of 25
CY7C1061G/CY7C1061GE
Ordering Information (continued)
Speed
(ns)
10
Voltage
Range
Ordering Code
4.5 V–5.5 V CY7C1061G-10BV1XIT
CY7C1061GE-10BV1XIT
CY7C1061G-10BVJXIT
CY7C1061GE-10BVJXIT
CY7C1061G-10BVXIT
CY7C1061GE-10BVXIT
CY7C1061G-10ZSXIT
CY7C1061GE-10ZSXIT
CY7C1061G-10ZXIT
CY7C1061GE-10ZXIT
Package Package Type
Diagram (all Pb-free)
Key Features /
Differentiators
51-85150 48-ball VFBGA Single Chip Enable,
Address MSB A19 at ball
G2, Tape and Reel
Dual Chip Enable,
Address MSB A19 at ball
G2, Tape and Reel
Dual Chip Enable,
Address MSB A19 at ball
H6, Tape and Reel
51-85160 54-pin TSOP II Dual Chip Enable,
Tape and Reel
51-85183 48-pin TSOP I Single Chip Enable,
Tape and Reel
2.2 V–3.6 V CY7C1061G30-10BV1XIT
51-85150 48-ball VFBGA Single Chip Enable,
Address MSB A19 at ball
CY7C1061GE30-10BV1XIT
G2, Tape and Reel
CY7C1061G30-10BVJXIT
CY7C1061GE30-10BVJXIT
CY7C1061G30-10BVXIT
CY7C1061GE30-10BVXIT
CY7C1061G30-10ZSXIT
CY7C1061GE30-10ZSXIT
CY7C1061G30-10ZXIT
CY7C1061GE30-10ZXIT
15
Dual Chip Enable,
Address MSB A19 at ball
G2, Tape and Reel
Dual Chip Enable,
Address MSB A19 at ball
H6, Tape and Reel
51-85160 54-pin TSOP II Dual Chip Enable,
Tape and Reel
51-85183 48-pin TSOP I Single Chip Enable,
Tape and Reel
1.65 V–2.2 V CY7C1061GE18-15BV1XIT 51-85150 48-ball VFBGA Single Chip Enable,
Address MSB A19 at ball
CY7C1061G18-15BV1XIT
G2, Tape and Reel
CY7C1061GE18-15BVJXIT
CY7C1061G18-15BVJXIT
CY7C1061GE18-15BVXIT
CY7C1061G18-15BVXIT
CY7C1061GE18-15ZSXIT
CY7C1061G18-15ZSXIT
CY7C1061GE18-15ZXIT
CY7C1061G18-15ZXIT
Document Number: 001-81540 Rev. *T
ERR Pin / Operating
Ball
Range
No
Industrial
Yes
No
Yes
No
Yes
No
Yes
No
Yes
No
Yes
No
Yes
No
Yes
No
Yes
No
Yes
Yes
No
Dual Chip Enable,
Address MSB A19 at ball
G2, Tape and Reel
Yes
Dual Chip Enable,
Address MSB A19 at ball
H6, Tape and Reel
Yes
No
No
51-85160 54-pin TSOP II Dual Chip Enable,
Tape and Reel
Yes
51-85183 48-pin TSOP I Single Chip Enable,
Tape and Reel
Yes
No
No
Page 18 of 25
CY7C1061G/CY7C1061GE
Ordering Code Definitions
CY 7 C 1 06 1
G
E
XX - XX XX X
I
X
X = blank or T
blank = Bulk; T = Tape and Reel
Temperature Range: I = Industrial
Pb-free
Package Type: XX = BV or ZS or Z
BV = 48-ball VFBGA; ZS = 54-pin TSOP II; Z = 48-pin TSOP I
Speed: XX = 10 ns or 15 ns
Voltage Range: XX = no character or 30 or 18
no character = 4.5 V–5.5 V; 30 = 2.2 V–3.6 V; 18 = 1.65 V–2.2 V
X = blank or E
blank = without ERR output;
E = with ERR output, Single bit error correction indicator
Process Technology: Revision Code “G” = 65 nm
Data Width: 1 = × 16-bits
Density: 06 = 16-Mbit
Family Code: 1 = Fast Asynchronous SRAM family
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 001-81540 Rev. *T
Page 19 of 25
CY7C1061G/CY7C1061GE
Package Diagrams
Figure 20. 48-pin TSOP I (12 × 18.4 × 1.0 mm) Z48A Package Outline, 51-85183
STANDARD PIN OUT (TOP VIEW)
2X (N/2 TIPS)
0.10
2X
2
1
N
SEE DETAIL B
A
0.10 C
A2
0.10
2X
8
R
B
E
(c)
5
e
N/2 +1
N/2
5
D1
D
0.20
2X (N/2 TIPS)
GAUGE PLANE
9
C
PARALLEL TO
SEATING PLANE
C
SEATING PLANE
4
0.25 BASIC
0°
A1
L
DETAIL A
B
A
B
SEE DETAIL A
0.08MM M C A-B
b
6
7
WITH PLATING
REVERSE PIN OUT (TOP VIEW)
e/2
3
1
N
7
c
c1
X
X = A OR B
b1
N/2
N/2 +1
SYMBOL
DIMENSIONS
MIN.
NOM.
MAX.
1.
2.
PIN 1 IDENTIFIER FOR STANDARD PIN OUT (DIE UP).
PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN): INK OR LASER MARK.
1.00
1.05
4.
TO BE DETERMINED AT THE SEATING PLANE
0.20
0.23
A2
0.95
0.17
0.22
b
0.17
c1
0.10
0.16
c
0.10
0.21
D
20.00 BASIC
18.40 BASIC
E
12.00 BASIC
5.
DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE
MOLD PROTRUSION ON E IS 0.15mm PER SIDE AND ON D1 IS 0.25mm PER SIDE.
6.
DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08mm TOTAL IN EXCESS OF b DIMENSION AT MAX.
MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON LOWER RADIUS OR
THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND AN ADJACENT LEAD
TO BE 0.07mm .
7.
THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN
0.10mm AND 0.25mm FROM THE LEAD TIP.
8.
LEAD COPLANARITY SHALL BE WITHIN 0.10mm AS MEASURED FROM THE
SEATING PLANE.
0.50 BASIC
0
0°
R
0.08
0.60
0.70
8
0.20
48
-C- . THE SEATING PLANE IS
DEFINED AS THE PLANE OF CONTACT THAT IS MADE WHEN THE PACKAGE
LEADS ARE ALLOWED TO REST FREELY ON A FLAT HORIZONTAL SURFACE.
0.27
D1
0.50
DIMENSIONS ARE IN MILLIMETERS (mm).
3.
b1
N
NOTES:
0.15
0.05
L
DETAIL B
1.20
A
A1
e
BASE METAL
SECTION B-B
9. DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.
10. JEDEC SPECIFICATION NO. REF: MO-142(D)DD.
51-85183 *F
Document Number: 001-81540 Rev. *T
Page 20 of 25
CY7C1061G/CY7C1061GE
Package Diagrams (continued)
Figure 21. 54-pin TSOP II (22.4 × 11.84 × 1.0 mm) Z54-II Package Outline, 51-85160
51-85160 *E
Document Number: 001-81540 Rev. *T
Page 21 of 25
CY7C1061G/CY7C1061GE
Package Diagrams (continued)
Figure 22. 48-ball VFBGA (6 × 8 × 1.0 mm) BV48/BZ48 Package Outline, 51-85150
51-85150 *H
Document Number: 001-81540 Rev. *T
Page 22 of 25
CY7C1061G/CY7C1061GE
Acronyms
Acronym
Document Conventions
Description
Units of Measure
BHE
Byte High Enable
BLE
Byte Low Enable
°C
degree Celsius
CE
Chip Enable
MHz
megahertz
CMOS
Complementary Metal Oxide Semiconductor
A
microampere
I/O
Input/Output
s
microsecond
OE
Output Enable
mA
milliampere
SRAM
Static Random Access Memory
mm
millimeter
TSOP
Thin Small Outline Package
ns
nanosecond
TTL
Transistor-Transistor Logic
ohm
VFBGA
Very Fine-Pitch Ball Grid Array
%
percent
WE
Write Enable
pF
picofarad
V
volt
W
watt
Document Number: 001-81540 Rev. *T
Symbol
Unit of Measure
Page 23 of 25
CY7C1061G/CY7C1061GE
Document History Page
Document Title: CY7C1061G/CY7C1061GE, 16-Mbit (1M words × 16-bit) Static RAM with Error-Correcting Code (ECC)
Document Number: 001-81540
Rev.
ECN No.
Orig. of
Change
Submission
Date
*P
4791835
NILE
06/09/2015
Changed status from Preliminary to Final.
*Q
5436639
NILE
09/14/2016
Updated Maximum Ratings:
Updated Note 9 (Replaced “2 ns” with “20 ns”).
Updated DC Electrical Characteristics:
Removed Operating Range “2.7 V to 3.6 V” and all values corresponding to
VOH parameter.
Included Operating Ranges “2.7 V to 3.0 V” and “3.0 V to 3.6 V” and all values
corresponding to VOH parameter.
Changed minimum value of VIH parameter from 2.2 V to 2 V corresponding to
Operating Range “4.5 V to 5.5 V”.
Updated Ordering Information:
Updated part numbers.
Updated to new template.
*R
5580947
NILE
01/10/2017
Updated Logic Block Diagram – CY7C1061G.
Updated Package Diagrams:
spec 51-85183 – Changed revision from *D to *F.
Updated to new template.
*S
5775815
AESATMP9
06/16/2017
Updated logo and copyright.
*T
6245720
NILE
07/13/2018
Updated Features:
Added Note 2 and referred the same note in “Embedded error-correcting code
(ECC) for single-bit error correction”.
Updated to new template.
Completing Sunset Review.
Document Number: 001-81540 Rev. *T
Description of Change
Page 24 of 25
CY7C1061G/CY7C1061GE
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
Arm® Cortex® Microcontrollers
Automotive
cypress.com/arm
cypress.com/automotive
Clocks & Buffers
Interface
cypress.com/clocks
cypress.com/interface
Internet of Things
Memory
cypress.com/iot
cypress.com/memory
Microcontrollers
cypress.com/mcu
PSoC
cypress.com/psoc
Power Management ICs
Cypress Developer Community
Community | Projects | Video | Blogs | Training | Components
Technical Support
cypress.com/support
cypress.com/pmic
Touch Sensing
cypress.com/touch
USB Controllers
Wireless Connectivity
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2012–2018. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC (“Cypress”). This document,
including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress’s patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing
device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress does not assume any liability arising out of any security breach,
such as unauthorized access to or use of a Cypress product. In addition, the products described in these materials may contain design defects or errors known as errata which may cause the product
to deviate from published specifications. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any
liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming
code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this
information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons
systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances
management, or other uses where the failure of the device or system could cause personal injury, death, or property damage (“Unintended Uses”). A critical component is any component of a device
or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you
shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from
and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 001-81540 Rev. *T
Revised July 13, 2018
Page 25 of 25
工商网监
湘ICP备2023018690号
