CY7C1069AV33-12ZC

CY7C1069AV33 2M x 8 Static RAM Features • High speed — tAA = 10, 12 ns • Low active power — 990 mW (max.) • Operating voltages of 3.3 ± 0.3V • 2.0V data retention • Automatic power-down when deselected • TTL-compatible inputs and outputs • Easy memory expansion with CE1 and CE2 features • Available in Pb-free and non Pb-free 54-pin TSOP II , non Pb-free 60-ball fine-pitch ball grid array (FBGA) package Functional Description The CY7C1069AV33 is a high-performance CMOS Static RAM organized as 2,097,152 words by 8 bits. Writing to the device is accomplished by enabling the chip (by taking CE1 LOW and CE2 HIGH) and Write Enable (WE) inputs LOW. Reading from the device is accomplished by enabling the chip (CE1 LOW and CE2 HIGH) as well as forcing the Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. See the truth table at the back of this data sheet for a complete description of Read and Write modes. The input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE1 HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or during a Write operation (CE1 LOW, CE2 HIGH, and WE LOW). The CY7C1069AV33 is available in a 54-pin TSOP II package with center power and ground (revolutionary) pinout, and a 60-ball fine-pitch ball grid array (FBGA) package. Logic Block Diagram Pin Configurations[1, 2] TSOP II Top View NC VCC NC I/O6 VSS I/O7 A4 A3 A2 A1 A0 NC CE1 VCC WE CE2 A19 A18 A17 A16 A15 I/O0 VCC I/O1 NC VSS NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 Data in Drivers I/O0 I/O1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 CE1 CE2 WE OE SENSE AMPS I/O2 I/O3 I/O4 I/O5 2048K x 8 ARRAY COLUMN DECODER POWER DOWN I/O6 I/O7 NC VSS NC I/O5 VCC I/O4 A5 A6 A7 A8 A9 NC OE VSS DNU A20 A10 A11 A12 A13 A14 I/O3 VSS I/O2 NC ROW DECODER VCC NC A17 A18 A19 A20 A16 A13 A14 A15 Cypress Semiconductor Corporation Document #: 38-05255 Rev. *F • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised August 3, 2006 [+] [+] Feedback CY7C1069AV33 Selection Guide –10 Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 10 275 50 60-ball FBGA (Top View) 3 4 –12 12 260 50 Unit ns mA mA Pin Configurations[1, 2](continued) 1 2 5 6 NC NC NC NC NC NC NC NC I/O0 VSS OE NC NC I/O 1 A0 A3 A5 A17 A18 A14 A 12 A9 A1 A4 A6 A7 A2 CE1 NC CE2 NC I/O4 A B C D E F G H I/O5 V CC V CC I/O2 I/O3 NC A19 NC DNU A8 A 16 I/O6 VSS A15 A13 A10 NC WE I/O7 NC A11 A20 NC NC NC NC NC NC Notes: 1. NC pins are not connected on the die. 2. DNU pins have to be left floating or tied to VSS to ensure proper application. Document #: 38-05255 Rev. *F Page 2 of 9 [+] [+] Feedback CY7C1069AV33 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage on VCC to Relative GND [3] DC Input Voltage[3] ................................ –0.5V to VCC + 0.5V Current into Outputs (LOW)......................................... 20 mA Operating Range Range Commercial Industrial Ambient Temperature 0°C to +70°C –40°C to +85°C VCC 3.3V ± 0.3V .... –0.5V to +4.6V DC Voltage Applied to Outputs in High-Z State[3] ....................................–0.5V to VCC + 0.5V DC Electrical Characteristics Over the Operating Range –10 Parameter VOH VOL VIH VIL IIX IOZ ICC ISB1 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[3] Input Leakage Current VCC Operating Supply Current Automatic CE Power-down Current —TTL Inputs Automatic CE Power-down Current —CMOS Inputs GND < VI < VCC VCC = Max., f = fMAX = 1/tRC CE2 < VIL, Max. VCC, CE1 > VIH VIN > VIH or VIN < VIL, f = fMAX CE2 < 0.3V, Max. VCC, CE1> VCC – 0.3V, VIN > VCC – 0.3V, or VIN < 0.3V, f = 0 Output Leakage Current GND < VOUT < VCC, Output Disabled Test Conditions VCC = Min., IOH = –4.0 mA VCC = Min., IOL = 8.0 mA 2.0 –0.3 –1 –1 Min. 2.4 0.4 VCC + 0.3 0.8 +1 +1 275 70 2.0 –0.3 –1 –1 Max. Min. 2.4 0.4 VCC + 0.3 0.8 +1 +1 260 70 –12 Max. Unit V V V V µA µA mA mA ISB2 50 50 mA Capacitance[4] Parameter CIN COUT Description Input Capacitance I/O Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 3.3V TSOP II 6 8 FBGA 8 10 Unit pF pF AC Test Loads and Waveforms[5] 50Ω OUTPUT Z0 = 50Ω (a) VTH = 1.5V 30 pF* *Capacitive Load consists of all components of the test environment 3.3V OUTPUT 5 pF* *Including jig and scope (b) 90% 10% Fall time: > 1V/ns (c) Notes: 3. VIL (min.) = –2.0V for pulse durations of less than 20 ns. 4. Tested initially and after any design or process changes that may affect these parameters. 5. Valid SRAM operation does not occur until the power supplies have reached the minimum operating VDD (3.0V). As soon as 1ms (Tpower) after reaching the minimum operating VDD, normal SRAM operation can begin including reduction in VDD to the data retention (VCCDR, 2.0V) voltage. R1 317 Ω R2 351 Ω All input pulses 3.3V GND Rise time > 1V/ns 90% 10% Document #: 38-05255 Rev. *F Page 3 of 9 [+] [+] Feedback CY7C1069AV33 AC Switching Characteristics Over the Operating Range Parameter Read Cycle tpower tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD Write tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE Cycle[10, 11] Write Cycle Time CE1 LOW/CE2 HIGH to Write End Address Set-up to Write End Address Hold from Write End Address Set-up to Write Start WE Pulse Width Data Set-up to Write End Data Hold from Write End WE HIGH to WE LOW to Low-Z[9] 9 High-Z[ ] [7] –10 Description VCC(typical) to the First Access[8] Read Cycle Time Address to Data Valid Data Hold from Address Change CE1 LOW/CE2 HIGH to Data Valid OE LOW to Data Valid OE LOW to Low-Z [9] [9] –12 Max. Min. 1 12 10 12 3 10 5 12 6 1 5 6 3 5 6 0 10 12 12 8 8 0 0 8 6 0 3 5 6 Max. Unit ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Min. 1 10 3 1 3 0 OE HIGH to High-Z [9] CE1 LOW/CE2 HIGH to Low-Z CE1 HIGH/CE2 LOW to CE1 LOW/CE2 HIGH to 9] High-Z[ Power-up[10] [10] CE1 HIGH/CE2 LOW to Power-down 10 7 7 0 0 7 5.5 0 3 Data Retention Waveform DATA RETENTION MODE VCC 3.0V tCDR CE VDR > 2V 3.0V tR Notes: 6. Valid SRAM operation does not occur until the power supplies have reached the minimum operating VDD (3.0V). As soon as 1ms (Tpower) after reaching the minimum operating VDD, normal SRAM operation can begin including reduction in VDD to the data retention (VCCDR, 2.0V) voltage. 7. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and transmission line loads. Test conditions for the Read cycle use output loading shown in part a) of the AC test loads, unless specified otherwise. 8. This part has a voltage regulator which steps down the voltage from 3V to 2V internally. tpower time has to be provided initially before a Read/Write operation is started. 9. tHZOE, tHZSCE, tHZWE and tLZOE, tLZCE, and tLZWE are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured ±200 mV from steady-state voltage. 10. These parameters are guaranteed by design and are not tested. 11. The internal Write time of the memory is defined by the overlap of CE1 LOW/CE2 HIGH, and WE LOW. CE1 and WE must be LOW along with CE2 HIGH to initiate a Write, and the transition of any of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write. 12. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document #: 38-05255 Rev. *F Page 4 of 9 [+] [+] Feedback CY7C1069AV33 Switching Waveforms Read Cycle No. 1[13, 14] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Read Cycle No. 2 (OE Controlled)[14, 15] ADDRESS tRC CE1 CE2 tASCE OE tDOE tLZOE DATA OUT VCC SUPPLY CURRENT HIGH IMPEDANCE tLZSCE tPU 50% DATA VALID tPD 50% ISB ICC tHZOE tHZSCE HIGH IMPEDANCE Notes: 13. Device is continuously selected. CE1 = VIL, CE2 = VIH. 14. WE is HIGH for Read cycle. 15. Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH. Document #: 38-05255 Rev. *F Page 5 of 9 [+] [+] Feedback CY7C1069AV33 Switching Waveforms (continued) Write Cycle No. 1 (CE1 Controlled)[16, 17, 18] tWC ADDRESS CE tSA tSCE tAW tPWE WE t BW tSD DATAI/O tHD tHA Write Cycle No. 2 (WE Controlled, OE LOW)[16, 17, 18] tWC ADDRESS CE tSCE tAW tSA tPWE tHA WE tHZWE DATA I/O tLZWE tSD tHD Truth Table CE1 H X L L L CE2 X L H H H OE X X L X H WE X X H L H I/O0–I/O7 High-Z High-Z Data Out Data In High-Z Power-down Power-down Read All Bits Write All Bits Selected, Outputs Disabled Mode Power Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Notes: 16. Data I/O is high-impedance if OE = VIH. 17. If CE1 goes HIGH/CE2 LOW simultaneously with WE going HIGH, the output remains in a high–impedance state. 18. CE above is defined as a combination of CE1 and CE2. It is active low. Document #: 38-05255 Rev. *F Page 6 of 9 [+] [+] Feedback CY7C1069AV33 Ordering Information Speed (ns) 10 Ordering Code CY7C1069AV33-10ZC CY7C1069AV33-10ZXC CY7C1069AV33-10BAC CY7C1069AV33-10ZI CY7C1069AV33-10ZXI CY7C1069AV33-10BAI CY7C1069AV33-12ZC CY7C1069AV33-12ZXC CY7C1069AV33-12BAC CY7C1069AV33-12ZI CY7C1069AV33-12ZXI CY7C1069AV33-12BAI Package Diagram 51-85160 51-85162 51-85160 51-85162 51-85160 51-85162 51-85160 51-85162 Package Type 54-pin TSOP II 54-pin TSOP II (Pb-free) 60-ball (8 mm x 20 mm x 1.2 mm) FBGA 54-pin TSOP II 54-pin TSOP II (Pb-free) 60-ball (8 mm x 20 mm x 1.2 mm) FBGA 54-pin TSOP II 54-pin TSOP II (Pb-free) 60-ball (8 mm x 20 mm x 1.2 mm) FBGA 54-pin TSOP II 54-pin TSOP II (Pb-free) 60-ball (8 mm x 20 mm x 1.2 mm) FBGA Operating Range Commercial Industrial 12 Commercial Industrial Package Diagrams 54-pin TSOP II (51-85160) 51-85160-** Document #: 38-05255 Rev. *F Page 7 of 9 [+] [+] Feedback CY7C1069AV33 Package Diagrams (continued) 60-ball FBGA (8 mm x 20 mm x 1.2 mm) (51-85162) TOP VIEW A1 CORNER BOTTOM VIEW A1 CORNER 6 5 4 3 2 1 DUMMY BALL (0.3) X12 1 2 3 4 5 6 Ø0.05 M C Ø0.25 M C A B Ø0.30±0.05(48X) A B C 20.00±0.10 18.00 2.625 D 20.00±0.10 E F G H A B C D 0.75 E F G H 5.25 DIMENSIONS IN MM 0.75 PART # 1.00 BA60A 1.875 0.75 0.75 1.00 3.75 STANDARD PKG. LEAD FREE PKG. A B 8.00±0.10 A BK60A PKG WEIGHT: 0.30 gms 0.53±0.05 0.25 C 0.21±0.05 6.00 0.15 C B 0.15(4X) 8.00±0.10 51-85162-*D SEATING PLANE 0.36 C 1.20 MAX All product and company names mentioned in this document may be the trademarks of their respective holders Document #: 38-05255 Rev. *F Page 8 of 9 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] [+] Feedback CY7C1069AV33 Document History Page Document Title: CY7C1069AV33 2M x 8 Static RAM Document Number: 38-05255 REV. ** *A *B ECN NO. 113724 117060 117990 Issue Date 03/27/02 07/31/02 08/30/02 Orig. of Change NSL DFP DFP New Data Sheet Removed 15-ns bin Added 8-ns bin Changing ICC for 8, 10, 12 bins tpower changed from 1 µs to 1 ms Load Cap Comment changed (for Tx line load) tSD changed to 5.5 ns for the 10-ns bin Changed some 8-ns bin #'s (tHZ, tDOE, tDBE) Removed hz < lz comments Final Data Sheet Added note 4 to “AC Test Loads and Waveforms” and note 7 to tpu and tpd Updated Input/Output Caps (for 48BGA only) to 8 pf/10 pf and for the 54-pin TSOP to 6/8 pf Changed ISB1 from 100 mA to 70 mA Shaded the 48fBGA product offering information Changed the Logic Block Diagram On page # 1 Added notes under Pin Configuration Changed the Package diagram of 51-85162 from Rev *A to Rev *D Changed 48-Ball FBGA to 60-Ball FBGA in Pin Configuration Updated the Ordering Information Removed 8 ns speed bin from product offering Changed the description of IIX from Input Load Current to Input Leakage Current in DC Electrical Characteristics table Updated the Ordering Information Description of Change *C 120385 11/13/02 DFP *D *E 124441 403984 2/25/03 See ECN MEG NXR *F 492137 See ECN NXR Document #: 38-05255 Rev. *F Page 9 of 9 [+] [+] Feedback