1CY7C1006B
CY7C106B CY7C1006B
256K x 4 Static RAM
Features
• High speed — tAA = 12 ns • CMOS for optimum speed/power • Low active power — 495 mW • Low standby power — 275 mW • 2.0V data retention (optional) — 100 µW • Automatic power-down when deselected • TTL-compatible inputs and outputs Enable (CE), an active LOW Output Enable (OE), and three-state drivers. These devices have an automatic power-down feature that reduces power consumption by more than 65% when the devices are deselected. Writing to the devices is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the four I/O pins (I/O0 through I/O3) is then written into the location specified on the address pins (A0 through A17). Reading from the devices is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the four I/O pins. The four input/output pins (I/O0 through I/O3) are placed in a high-impedance state when the devices are deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE and WE LOW). The CY7C106B is available in a standard 400-mil-wide SOJ; the CY7C1006B is available in a standard 300-mil-wide SOJ.
Functional Description
The CY7C106B and CY7C1006B are high-performance CMOS static RAMs organized as 262,144 words by 4 bits. Easy memory expansion is provided by an active LOW Chip
Logic Block Diagram
Pin Configuration
SOJ Top View A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 CE OE GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15
INPUT BUFFER
A1 A2 A3 A4 A5 A6 A7 A8 A9
ROW DECODER
SENSE AMPS
I/O3 I/O2 I/O1 I/O0
VCC A17 A16 A15 A14 A13 A12 A11 NC I/O3 I/O2 I/O1 I/O0 WE
C106B–2
512 x 512 x 4 ARRAY
COLUMN DECODER
POWER DOWN
CE WE OE
C106B–1
Selection Guide
7C106B-12 7C1006B-12 Maximum Access Time (ns) Maximum Operating Current (mA) Maximum Standby Current (mA) 12 90 50 7C106B-15 7C1006B-15 15 80 30 7C106B-20 7C1006B-20 20 75 30 7C106B-25 7C1006B-25 25 70 30 7C106B-35 35 60 25
Cypress Semiconductor Corporation Document #: 38-05037 Rev. **
A0 A 10 A 11 A 12 A 13 A 14 A 15 A 16 A 17
•
3901 North First Street
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San Jose
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CA 95134 • 408-943-2600 Revised August 24, 2001
CY7C106B CY7C1006B
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied ............................................. –55°C to +125°C Supply Voltage on VCC Relative to GND[1] .... –0.5V to +7.0V DC Voltage Applied to Outputs in High Z State[1] ....................................–0.5V to VCC + 0.5V DC Input Voltage[1] .................................–0.5V to VCC + 0.5V Range Commercial Industrial Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage .......................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current..................................................... >200 mA
Operating Range
Ambient Temperature[2] 0°C to +70°C –45°C to +85°C VCC 5V ± 10%
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CY7C106B CY7C1006B
Electrical Characteristics Over the Operating Range
7C106B-12 7C1006B-12 Parameter VOH VOL VIH VIL IIX IOZ IOS ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[1] Input Load Current Output Leakage Current Output Short Circuit Current[3] VCC Operating Supply Current Automatic CE Power-Down Current —TTL Inputs Automatic CE Power-Down Current —CMOS Inputs Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[1] Input Load Current Output Leakage Current Output Short Circuit Current[3] VCC Operating Supply Current Automatic CE Power-Down Current —TTL Inputs Automatic CE Power-Down Current —CMOS Inputs GND < VI < VCC GND < VI < VCC, Output Disabled VCC = Max., VOUT = GND VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC Max. VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fMAX Max. VCC, CE > VCC – 0.3V, VIN > VCC – 0.3V or VIN < 0.3V, f = 0 Com’l GND < VI < VCC GND < VI < VCC, Output Disabled VCC = Max., VOUT = GND VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC Max. VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fMAX Max. VCC, CE > VCC – 0.3V, VIN > VCC – 0.3V or VIN < 0.3V, f=0 VCC = Min., IOH = –4.0 mA VCC = Min., IOL = 8.0 mA 2.2 –0.3 –1 –5 Com’l Test Conditions VCC = Min., IOH = – 4.0 mA VCC = Min., IOL = 8.0 mA 2.2 –0.3 –1 –5 Min. 2.4 0.4 VCC +0.3 0.8 +1 +5 –300 90 2.2 –0.3 –1 –5 Max. 7C106B-15 7C1006B-15 Min. 2.4 0.4 VCC +0.3 0.8 +1 +5 –300 80 2.2 –0.3 –1 –5 Max. 7C106B-20 7C1006B-20 Min. 2.4 0.4 VCC +0.3 0.8 +1 +5 –300 75 Max. Unit V V V V µA µA mA mA
ISB1
50
30
30
mA
ISB2
10
10
10
mA
VOH VOL VIH VIL IIX IOZ IOS ICC
2.4 0.4 VCC + 0.3 0.8 +1 +5 –300 70
2.4 0.4 2.2 –0.3 –1 –5 VCC + 0.3 0.8 +1 +5 –300 60
V V V V µA µA mA mA
ISB1
30
25
mA
ISB2
10
10
mA
Notes: 1. VIL (min.) = –2.0V for pulse durations of less than 20 ns. 2. TA is the “instant on” case temperature. 3. Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
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CY7C106B CY7C1006B
Capacitance[4]
Parameter CIN: Addresses CIN: Controls COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V Max. 7 10 10 Unit pF pF pF
AC Test Loads and Waveforms
R1 480 Ω 5V OUTPUT 30 pF INCLUDING JIG AND SCOPE R2 255Ω 5V OUTPUT 5 pF INCLUDING JIG AND SCOPE R2 GND 255Ω
Rise Time < 1V/ns
R1 480 Ω 3.0V
ALL INPUT PULSES 90% 10% 90% 10%
Fall Time < 1V/ns
(a)
Equivalent to: OUTPUT THÉVENIN EQUIVALENT 167Ω 1.73V
(b)
C106B–3
C106B–4
Note: 4. Tested initially and after any design or process changes that may affect these parameters.
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CY7C106B CY7C1006B
Switching Characteristics Over the Operating Range[5]
7C106B-12 7C106B-15 7C106B-20 7C106B-25 7C1006B-12 7C1006B-15 7C1006B-20 7C1006B-25 Parameter READ CYCLE tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z OE HIGH to High Z[6, 7] CE LOW to Low Z[7] Z[6, 7] 0 12 12 10 10 0 0 10 7 0 2 6 15 12 12 0 0 12 8 0 3 7 3 6 0 15 20 15 15 0 0 15 10 0 3 8 CE HIGH to High 0 6 3 7 0 20 25 20 20 0 0 20 15 0 3 10 3 12 6 0 7 3 8 0 25 35 25 25 0 0 25 20 0 3 10 12 12 3 15 7 0 8 3 10 0 35 15 15 3 20 8 0 10 3 10 20 20 3 25 10 0 10 25 25 3 35 10 35 35 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description Min. Max. Min. Max. Min. Max. Min. Max. 7C106B-35 Min. Max. Unit
CE LOW to Power-Up CE HIGH to Power-Down Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low WE LOW to High Z[7] Z[6, 7]
WRITE CYCLE[8, 9]
Notes: 5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30–pF load capacitance. 6. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage. 7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 8. The internal write time of the memory is defined by the overlap of CE and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 9. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
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CY7C106B CY7C1006B
Data Retention Characteristics Over the Operating Range
Parameter VDR ICCDR tCDR[4] tR[4] Description VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time VCC = VDR = 2.0V, CE > VCC – 0.3V, VIN > VCC – 0.3V or VIN < 0.3V Conditions[10] Min. 2.0 250 0 200 Max. Unit V µA ns µs
Data Retention Waveform
DATA RETENTION MODE VCC 4.5V tCDR CE
C106B–5
VDR > 2V
4.5V tR
Switching Waveforms
Read Cycle No.1[11, 12] 1
tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID
C106B–6
Read Cycle No. 2 (OE Controlled)
[12, 13]
ADDRESS tRC CE tACE OE tDOE tLZOE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% tHZOE tHZCE DATA VALID tPD 50% ISB
C106B–7
HIGH IMPEDANCE
DATA OUT
ICC
Notes: 10. No input may exceed VCC +0.5V. 11. Device is continuously selected, OE and CE = VIL. 12. WE is HIGH for read cycle. 13. Address valid prior to or coincident with CE transition LOW.
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CY7C106B CY7C1006B
Switching Waveforms (continued)
Write Cycle No. 1 (CE Controlled)[14, 15]
tWC ADDRESS tSCE CE tSA tAW tPWE WE tSD DATA I/O DATA VALID
C106B–8
tHA
tHD
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[14, 15]
tWC ADDRESS tSCE CE
tAW tSA WE tPWE
tHA
OE tSD DATA I/O tHZOE
C106B–9
tHD
DATA VALID
Notes: 14. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. 15. Data I/O is high impedance if OE = VIH.
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CY7C106B CY7C1006B
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, OE LOW)[9, 15]
tWC ADDRESS tSCE CE
tAW tSA WE tSD DATA I/O tHZWE DATA VALID tPWE
tHA
tHD
tLZWE
C106B–10
Truth Table
CE H L L L OE X L X H WE X H L H Input/Output High Z Data Out Data In High Z Power-Down Read Write Selected, Outputs Disabled Mode Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC)
Ordering Information
Speed (ns) 12 15 Ordering Code CY7C106B-12VC CY7C1006B-12VC CY7C106B-15VC CY7C1006B-15VC CY7C106B-15VI CY7C1006B-15VI CY7C106B-20VC CY7C1006B-20VC CY7C106B-20VI CY7C1006B-20VI CY7C106B-25VC CY7C1006B-25VC CY7C106B-25VI CY7C1006B-25VI CY7C106B-35VC CY7C106B-35VI Package Name V28 V21 V28 V21 V28 V21 V28 V21 V28 V21 V28 V21 V28 V21 V28 V28 Package Type 28-Lead (400-Mil) Molded SOJ 28-Lead (300-Mil) Molded SOJ 28-Lead (400-Mil) Molded SOJ 28-Lead (300-Mil) Molded SOJ 28-Lead (400-Mil) Molded SOJ 28-Lead (300-Mil) Molded SOJ 28-Lead (400-Mil) Molded SOJ 28-Lead (300-Mil) Molded SOJ 28-Lead (400-Mil) Molded SOJ 28-Lead (300-Mil) Molded SOJ 28-Lead (400-Mil) Molded SOJ 28-Lead (300-Mil) Molded SOJ 28-Lead (400-Mil) Molded SOJ 28-Lead (300-Mil) Molded SOJ 28-Lead (400-Mil) Molded SOJ 28-Lead (400-Mil) Molded SOJ Operating Range Commercial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial
20
25
35
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CY7C106B CY7C1006B
Package Diagrams
28-Lead (300-Mil) Molded SOJ V21
51-85031-B
28-Lead (400-Mil) Molded SOJ V28
51-85032-A
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© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C106B CY7C1006B
Document Title: CY7C106B, CY7C1006B 256K x 4 Static RAM Document Number: 38-05037 REV. ** ECN NO. 106831 Issue Date 09/17/01 Orig. of Change SZV Description of Change Change from Spec number: 38-00955 to 38-05037
Document #: 38-05037 Rev. **
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