CY7C107-15VI

CY7C107 CY7C1007 1M x 1 Static RAM Features • High speed — tAA = 12 ns • CMOS for optimum speed/power • Low active power — 825 mW • Low standby power — 275 mW • 2.0V data retention (optional) — 100 µW • Automatic power-down when deselected • TTL-compatible inputs and outputs memory expansion is provided by an active LOW Chip Enable (CE) and three-state drivers. These devices have an automatic power-down feature that reduces power consumption by more than 65% when deselected. Writing to the devices is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the input pin (DIN) is written into the memory location specified on the address pins (A0 through A19). Reading from the devices is accomplished by taking Chip Enable (CE) LOW while Write Enable (WE) remains HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the data output (DOUT) pin. The output pin (D OUT) is placed in a high-impedance state when the device is deselected (CE HIGH) or during a write operation (CE and WE LOW). The CY7C107 is available in a standard 400-mil-wide SOJ; the CY7C1007 is available in a standard 300-mil-wide SOJ. Functional Description The CY7C107 and CY7C1007 are high-performance CMOS static RAMs organized as 1,048,576 words by 1 bit. Easy Logic Block Diagram DIN Pin Configuration SOJ Top View A10 A11 A12 A13 A14 A15 NC A16 A17 A18 A19 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 INPUT BUFFER A0 A1 A2 A3 A4 A5 A6 A7 A8 ROW DECODER 512x2048 ARRA Y DOUT DOUT WE GND VCC A9 A8 A7 A6 A5 A4 NC A3 A2 A1 A0 DIN CE 107-2 COLUMN DECODER A9 A 10 A 11 A12 A 13 A14 A15 A16 A 17 A 18 A 19 POWER DOWN SENSE AMPS CE WE 107-1 Selection Guide 7C107-12 7C1007-12 Maximum Access Time (ns) Maximum Operating Current (mA) Maximum Standby Current (mA) 12 150 50 7C107-15 7C1007-15 15 135 40 7C107-20 7C1007-20 20 125 30 7C107-25 7C1007-25 25 120 30 7C107-35 35 110 25 Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 December 1992 – Revised September 3, 1999 CY7C107 CY7C1007 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ..................................... −65°C to +150°C Ambient Temperature with Power Applied .................................................. −55°C to +125°C Supply Voltage on VCC Relative to GND [1] Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage ........................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current ..................................................... >200 mA Operating Range Range Commercial Industrial Ambient Temperature[2] 0°C to +70°C −40°C to +85°C VCC 5V ± 10% 5V ± 10% .....−0.5V to +7.0V DC Voltage Applied to Outputs in High Z State[1] ....................................... −0.5V to VCC + 0.5V DC Input Voltage[1] .................................... −0.5V to VCC + 0.5V Electrical Characteristics Over the Operating Range 7C107-12 7C1007-12 Parameter VOH VOL VIH VIL IIX IOZ IOS ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[1] Input Load Current Output Leakage Current Output Short Circuit Current[3] VCC Operating Supply Current Automatic CE Power-Down Current— TTL Inputs Automatic CE Power-Down Current— CMOS Inputs GND < VI < VCC GND < VI < VCC, Output Disabled VCC = Max., VOUT = GND VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC Max. VCC, CE > VIH, VIN >VIH or VIN < VIL, f = f MAX Max. VCC, CE > VCC – 0.3V, VIN > VCC – 0.3V or VIN < 0.3V, f = 0 Test Conditions VCC = Min., IOH = −4.0 mA VCC = Min., IOL = 8.0 mA 2.2 −0.3 −1 –5 Min. 2.4 0.4 VCC+ 0.3 0.8 +1 +5 −300 150 2.2 −0.3 −1 –5 Max. 7C107-15 7C1007-15 Min. 2.4 0.4 VCC+ 0.3 0.8 +1 +5 −300 135 2.2 −0.3 −1 –5 Max. 7C107-20 7C1007-20 Min. 2.4 0.4 VCC+ 0.3 0.8 +1 +5 −300 125 Max. Unit V V V V µA µA mA mA ISB1 50 40 30 mA ISB2 2 2 2 mA Notes: 1. VIL (min.) = – 2.0V for pulse durations of less than 20 ns. 2. TA is the “instant on” case temperature. 3. Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. 2 CY7C107 CY7C1007 Electrical Characteristics Over the Operating Range (continued) 7C107-25 7C1007-25 Parameter VOH VOL VIH VIL IIX IOZ IOS ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current Output Leakage Current Output Short Circuit Current[3] VCC Operating Supply Current Automatic CE Power-Down Current—TTL Inputs Automatic CE Power-Down Current—CMOS Inputs [1] 7C107-35 Min. 2.4 Max. Unit V 0.4 2.2 −0.3 −1 −5 VCC + 0.3 0.8 +1 +5 −300 110 V V V µA µA mA mA Test Conditions VCC = Min., IOH = −4.0 mA VCC = Min., IOL = 8.0 mA Min. 2.4 Max. 0.4 2.2 −0.3 VCC + 0.3 0.8 +1 +5 −300 120 GND < VI < VCC GND < VI < VCC, Output Disabled VCC = Max., VOUT = GND VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC Max. V CC, CE > VIH, VIN >VIH or VIN < VIL, f = f MAX Max. V CC, CE > VCC – 0.3V, VIN > VCC – 0.3V or VIN < 0.3V, f = 0 −1 −5 ISB1 30 25 mA ISB2 2 2 mA Capacitance[4] Parameter CIN: Addresses CIN: Controls COUT Output Capacitance Description Input Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V Max. 7 10 10 Unit pF pF pF Note: 4. Tested initially and after any design or process changes that may affect these parameters. 3 CY7C107 CY7C1007 AC Test Loads and Waveforms 5V OUTPUT 30 pF INCLUDING JIG AND SCOPE (a) R2 255Ω R1 480Ω 5V OUTPUT 5 pF INCLUDING JIG AND SCOPE (b) R2 255Ω R1 480Ω 3.0V GND 10% ≤ 3 ns ALL INPUT PULSES 90% 90% 10% ≤ 3 ns 107-4 107-3 Equivalent to: OUTPUT THÉVENIN EQUIVALENT 167Ω 1.73V Switching Characteristics[5] Over the Operating Range 7C107-12 7C1007-12 Parameter READ CYCLE tRC tAA tOHA tACE tLZCE tHZCE tPU tPD tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid CE LOW to Low Z[6] CE HIGH to High Z [6, 7] CE LOW to Power-Up CE HIGH to Power-Down Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low Z [6] 7C107-15 7C1007-15 Min. 15 Max. 7C107-20 7C1007-20 Min. 20 Max. 7C107-25 7C1007-25 Min. 25 Max. 7C107-35 Min. 35 Max. Unit ns 35 3 ns ns 35 3 10 0 35 35 25 25 0 0 25 20 0 3 ns ns ns ns ns ns ns ns ns ns ns ns ns ns 10 ns Description Min. 12 Max. 12 3 12 3 6 0 12 12 10 10 0 0 10 7 0 3 6 15 12 12 0 0 12 8 0 3 0 3 3 15 3 15 3 7 0 15 20 15 15 0 0 15 10 0 3 7 20 3 20 3 8 0 20 25 20 20 0 0 20 15 0 3 8 25 25 10 25 WRITE CYCLE[8] WE LOW to High Z[6, 7] 10 Notes: 5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 6. At any given temperature and voltage condition, tHZCE is less than tLZCE and tHZWE is less than tLZWE for any given device. 7. tHZCE and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage. 8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 4 CY7C107 CY7C1007 Data Retention Characteristics Over the Operating Range (L Version Only) Parameter VDR ICCDR tCDR[4] tR[4] Description VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time VCC = VDR = 2.0V, CE > VCC – 0.3V, VIN > VCC – 0.3 or VIN < 0.3V Conditions[9] Min. 2.0 50 0 tRC Max. Unit V µA ns ns Data Retention Waveform DATA RETENTION MODE VCC 4.5V tCDR CE 107-5 VDR > 2V 4.5V tR Switching Waveforms Read Cycle No. 1[10, 11] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID 107-6 Read Cycle No. 2[11, 12] ADDRESS tRC CE tACE tLZCE DATA OUT HIGH IMPEDANCE DATA VALID tPD ICC 50% 50% ISB 107-7 tHZCE HIGH IMPEDANCE VCC SUPPLY CURRENT tPU Notes: 9. No input may exceed VCC + 0.5V. 10. Device is continuously selected, CE = VIL. 11. WE is HIGH for read cycle. 12. Address valid prior to or coincident with CE transition LOW. 5 CY7C107 CY7C1007 Switching Waveforms (continued) Write Cycle No. 1 (CE Controlled)[13] tWC ADDRESS tSA CE tAW WE tPWE tSD DATA IN DATA VALID tHD tHA tSCE DATA OUT HIGH IMPEDANCE 107-8 Write Cycle No. 2 (WE Controlled)[13] tWC ADDRESS tSCE CE tSA WE tSD DATA IN DATA VALID tHZWE DATA OUT DATA UNDEFINED 107-9 tAW tPWE tHA tHD tLZWE HIGH IMPEDANCE Note: 13. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. 6 CY7C107 CY7C1007 Truth Table CE H L L WE X H L High Z Data Out High Z DOUT Read Write Mode Power-Down Standby (ISB) Active (ICC) Active (ICC) Power Ordering Information Speed (ns) 12 15 15 20 25 Ordering Code CY7C107-12VC CY7C1007-12VC CY7C107-15VC CY7C1007-15VC CY7C107-15VI CY7C1007-15VI CY7C107-20VC CY7C1007-20VC CY7C107-25VC CY7C1007-25VC Package Name V28 V21 V28 V21 V28 V21 V28 V21 V28 V21 Package Type 28-Lead (400-Mil) Molded SOJ 28-Lead (300-Mil) Molded SOJ 28-Lead (400-Mil) Molded SOJ 28-Lead (300-Mil) Molded SOJ 28-Lead (400-Mil) Molded SOJ 28-Lead (300-Mil) Molded SOJ 28-Lead (400-Mil) Molded SOJ 28-Lead (300-Mil) Molded SOJ 28-Lead (400-Mil) Molded SOJ 28-Lead (300-Mil) Molded SOJ Operating Range Commercial Commercial Industrial Commercial Commercial Contact factory for “L” version availability. Document #: 38-00232-C Package Diagrams 28-Lead (300-Mil) Molded SOJ V21 51-85031-B 7 CY7C107 CY7C1007 Package Diagrams (continued) 28-Lead (400-Mil) Molded SOJ V28 51-85032-A © Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.