CY7C1072AV33-10BBC

PRELIMINARY CY7C1072AV33 32-Mbit (1M x 32) Static RAM Features • High density 32-Mbit SRAM • High speed — tAA = 10 ns • Low active power • • • • — ICC = 450 mA Operating voltages of 3.3 ± 0.3V 2.0V data retention Automatic power-down when deselected TTL compatible inputs and outputs specified on the address pins (A0 through A19). If Byte Enable B (BB) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A19). Likewise, BC and BD correspond with the I/O pins I/O16 to I/O23 and I/O24 to I/O31, respectively. Reading from the device is accomplished by enabling the chip by taking CE1 LOW and CE2 HIGH while forcing the Output Enable (OE) LOW and the Write Enable (WE) HIGH. If the first Byte Enable (BA) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte Enable B (BB) is LOW, then data from memory will appear on I/O8 to I/O15. Similarly, Bc and BD correspond to the third and fourth bytes. See the truth table at the back of this data sheet for a complete description of read and write modes. The input/output pins (I/O0 through I/O31) are placed in a high-impedance state when the device is deselected (CE1 HIGH/CE2 LOW), the outputs are disabled (OE HIGH), the byte selects are disabled (BA-D HIGH), or during a Write operation (CE1 LOW, CE2 HIGH, and WE LOW). The CY7C1072AV33 is available in a 119-ball grid array (FBGA) package. • Available in standard 119-ball FBGA Functional Description The CYM1072AV33 is a 3.3V high-performance 32-Megabit static RAM organized as 1M words by 32 bits. Writing to the device is accomplished by enabling the chip (CE1 LOW and CE2 HIGH) while forcing the Write Enable (WE) input LOW. If Byte Enable A (BA) is LOW, then data from the I/O pins (I/O0 through I/O7), is written into the location Logic Block Diagram INPUT BUFFERS CONTROL LOGIC WE CE1 CE2 OE BA BB BC BD I/O0–I/O31 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 ROW DECODER 1024K x 32 ARRAY COLUMN DECODER Selection Guide CY7C1072AV33-10 Maximum Access Time Maximum Operating Current Maximum Standby Current 10 450 100 CY7C1072AV33-12 12 400 100 Unit ns mA mA A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 OUTPUT BUFFERS SENSE AMPS Cypress Semiconductor Corporation Document #: 38-05635 Rev. *A • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised September 1, 2005 PRELIMINARY Pin Configurations 119 BGA CY7C1072AV33 (Top View) 1 A B C D E F G H J K L M N P R T U I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 NC I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 2 A A Bc VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD A A A 3 A A CE2 VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS Bd A A 4 A CE1 A VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC WE OE 5 A A NC VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS Bb A A 6 A A Ba VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD A A A 7 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 DNU I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 Document #: 38-05635 Rev. *A Page 2 of 9 PRELIMINARY Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage on VCC to Relative GND [1] CY7C1072AV33 DC Input Voltage [1] ............................... –0.3V to VCC + 0.3V Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage............................................ >2001V (per MIL-STD-883, Method 3015) Latch-Up Current ..................................................... >200 mA Operating Range Range Commercial Industrial Ambient Temperature 0°C to +70°C –40°C to +85°C VCC 3.3V ± 0.3V ...... –0.5V to 4.6V DC Voltage Applied to Outputs in High Z State [1] ...................................–0.3V to VCC + 0.3V Electrical Characteristics Over the Operating Range -10 Parameter VOH VOL VIH VIL IIX IOZ ICC ISB1 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[1] Input Load Current Output Leakage Current VCC Operating Supply Current Automatic CE Power-Down Current —TTL Inputs Automatic CE Power-Down Current —CMOS Inputs GND < VI < VCC GND < VI < VCC, Output Disabled VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC Max. VCC, CE1 > VIH,CE2< VIL; VIN > VIH or VIN < VIL, f = fMAX Max. VCC, CE1> VCC – 0.3V, CE2 < 0.3V, VIN > VCC – 0.3V, or VIN < 0.3V, f = 0 Com’l / Ind’l Com’l / Ind’l Test Conditions VCC = Min., IOH = –4.0 mA VCC = Min., IOL = 8.0 mA 2.0 –0.3 –2 –2 Min. 2.4 0.4 VCC + 0.3 0.8 +2 +2 450 140 2.0 –0.3 –2 –2 Max. Min. 2.4 0.4 VCC + 0.3 0.8 +2 +2 400 140 -12 Max. Unit V V V V μA μA mA mA ISB2 100 100 mA Capacitance[2] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 3.3V Max. 12 15 Unit pF pF Thermal Resistance[2] Parameter ΘJA ΘJC Description Thermal Resistance (Junction to Ambient) [3] [2] Test Conditions Still Air, soldered on a 3 × 4.5 inch, two-layer printed circuit board All-Packages TBD TBD Unit °C/W °C/W Thermal Resistance (Junction to Case)[2] 50Ω AC Test Loads and Waveforms OUTPUT Z0 = 50Ω VTH = 1.5V 30 pF* * Capacitive Load consists of all components of the Test environment R1 317Ω 3.3V OUTPUT 5 pF ALL INPUT PULSES R2 351Ω 3.3V (a) GND Rise time > 1 V/ns 90% 10% 90% 10% INCLUDING JIG AND SCOPE (b) (c) Fall time > 1 V/ns Notes: 1. VIL (min.) = –2.0V and VIH(max) = VCC + 0.5V for pulse durations of less than 20 ns. 2. Tested initially and after any design or process changes that may affect these parameters. 3. Valid SRAM operation does not occur until the power supplies have reached the minimum operating VDD (3.0V). As soon as 1ms (Tpower) after reaching the minimum operating VDD, normal SRAM operation can begin including reduction in VDD to the data retention (VCCDR, 2.0V) voltage. Document #: 38-05635 Rev. *A Page 3 of 9 PRELIMINARY Switching Characteristics[4,5] Over the Operating Range -10 Parameter Read Cycle tpower tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE Write Cycle[9, 10] tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE tBW Write Cycle Time CE active to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low WE LOW to High Z[7] Z[7] 7 Conditions[12] Com’l / Ind’l 10 7 7 0 0 7 5.5 0 3 5 8 12 8 8 0 0 8 6 0 3 VCC(typical) to the first access[6] Read Cycle Time Address to Data Valid Data Hold from Address Change CE active to Data Valid OE LOW to Data Valid OE LOW to Low Z OE HIGH to High Z[7] CE active to Low Z [7] CY7C1072AV33 -12 Max. Min. 1 12 10 12 3 10 5 12 6 1 5 6 3 5 6 0 10 10 12 12 1 5 6 Max. Unit ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 6 ns ns Description Min. 1 10 3 1 3 0 CE inactive to High CE inactive to Z[7] CE active to Power-Up[8] Power-Down[8] Byte Enable to Data Valid Byte Enable to Low-Z Byte Disable to High-Z 1 Byte Enable to End of Write Data Retention Characteristics Over the Operating Range Parameter VDR ICCDR tCDR[2] tR[11] Description VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time VCC = VDR = 2.0V, CE > VCC – 0.3V VIN > VCC – 0.3V or VIN < 0.3V Min. 2.0 100 0 Max Unit V mA ns μs Notes: 4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and specified transmission line loads. Test conditions for the Read cycle use output loading shown in part a) of the AC test loads, unless specified otherwise. 5. CE indicates a combination of both chip enables. When ACTIVE LOW, CE indicates the CE1 is LOW and CE2 is HIGH. 6. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed. 7. tHZOE, tHZCE, tHZWE, tHZBE and tLZOE, tLZCE, t\LZWE, tLZBE are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured ±200 mV from steady-state voltage. 8. These parameters are guaranteed by design and are not tested. 9. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 10. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. 11. Test conditions assume tr < 3 ns. 12. No input may exceed VCC + 0.3V. Document #: 38-05635 Rev. *A Page 4 of 9 PRELIMINARY Data Retention Waveform DATA RETENTION MODE VCC 3.0V tCDR CE VDR > 2V 3.0V tR CY7C1072AV33 Switching Waveforms Read Cycle No. 1[13, 14] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Read Cycle No. 2 (OE Controlled)[14, 15] ADDRESS tRC CE1 CE2 tACE OE tDOE BA, BB, BC, BD tLZOE tDBE tLZBE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% tHZCE tHZBE DATA VALID tPD 50% ISB IICC CC tHZOE HIGH IMPEDANCE DATA OUT Notes: 13. Device is continuously selected. OE, CE1, BA, BB, BC, BD = VIL, CE2 = VIH 14. WE is HIGH for read cycle. 15. Address valid prior to or coincident with CE transition LOW, CE2 transition HIGH. Document #: 38-05635 Rev. *A Page 5 of 9 PRELIMINARY Switching Waveforms (continued) Write Cycle No. 1 (CE Controlled)[5, 16, 17] tWC ADDRESS CY7C1072AV33 CE tSA tSCE tAW tPWE WE tBW BA, BB, BC , BD tSD DATA I/O tHD tHA Write Cycle No. 2 (BA, BB, BC, BD Controlled)[5, 16, 17] tWC ADDRESS tSA BA, BB, BC , BD tAW tBW tHA tPWE WE tSCE CE tSD DATA I/O tHD Notes: 16. Data I/O is high impedance if OE = VIH or BA/BB/BC/BD = VIH 17. If CE goes HIGH or CE2 goes LOW simultaneously with WE going HIGH, the output remains in a high-impedance state. Document #: 38-05635 Rev. *A Page 6 of 9 PRELIMINARY Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled, OE LOW)[5, 16, 17] tWC ADDRESS CY7C1072AV33 CE tSCE tAW tSA tPWE tHA WE tBW BA, BB, BC, BD tHZWE DATA I/O tLZWE tSD tHD Truth Table CE1 H X L L L L L L L L L L L CE2 X L H H H H H H H H H H H OE X X L L L L L X X X X X H WE X X H H H H H L L L L L H BA X X L L H H H L L H H H X BB X X L H L H H L H L H H X Bc X X L H H L H L H H L H X BD X X L H H H L L H H H L X I/O0– I/O7 High-Z High-Z Data Out Data Out High-Z High-Z High-Z Data In Data In High-Z High-Z High-Z High-Z I/O8– I/O15 High-Z High-Z Data Out High-Z Data Out High-Z High-Z Data In High-Z Data In High-Z High-Z High-Z I/O16– I/O23 High-Z High-Z Data Out High-Z High-Z Data Out High-Z Data In High-Z High-Z Data In High-Z High-Z I/O24– I/O31 High-Z High-Z Data Out High-Z High-Z High-Z Data Out Data In High-Z High-Z High-Z Data In High-Z Mode Power Down Power Down Read All Bits Power (ISB) (ISB) (ICC) Read Byte A Bits (ICC) Only Read Byte B Bits (ICC) Only Read Byte C Bits (ICC) Only Read Byte D Bits (ICC) Only Write All Bits (ICC) Write Byte A Bits (ICC) Only Write Byte B Bits (ICC) Only Write Byte C Bits (ICC) Only Write Byte D Bits (ICC) Only Selected, Outputs (ICC) Disabled Document #: 38-05635 Rev. *A Page 7 of 9 PRELIMINARY Ordering Information Speed (ns) 10 12 Ordering Code CY7C1072AV33-10 BBC CY7C1072AV33-10 BBI CY7C1072AV33-12 BBC CY7C1072AV33-12 BBI BB119 119-Ball (14 x 22 x 2.02 mm) FBGA Package Name BB119 Package Type 119-Ball (14 x 22 x 2.02 mm) FBGA CY7C1072AV33 Operating Range Commercial Industrial Commercial Industrial Package Diagrams 119 FBGA (14 x 22 x 2.02 MM) BB119B 51-85210-** Document #: 38-05635 Rev. *A Page 8 of 9 © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. PRELIMINARY Document History Page Document Title: CY7C1072AV33 32-Mbit (1M x 32) Static RAM Module Document Number: 38-05635 REV . ** *A ECN NO. Issue Date Orig. of Change RKF SYT Description of Change New Data Sheet CY7C1072AV33 278072 See ECN 397700 See ECN Converted from “Advance Information” to “Preliminary” Changed the MPN from CYM1072AV33 to CY7C1072AV33 Changed Title from “CY7C1072AV33 32-Mbit (1M x 32) Static RAM Module” to “CY7C1072AV33 32-Mbit (1M x 32) Static RAM“ Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901 North First Street” to “198 Champion Court” Removed redundant information from the “Features” and “Functional Description” sections Changed Package offering from 119 PBGA (BG119) to 119 FBGA (BB119) Changed the DC Voltage Applied to Outputs in High-Z State and DC Input Voltage from “-0.5V to VCC + 0.5V” to “-0.3V to VCC + 0.3V” in the Maximum Ratings on Page # 3 Changed VCC from “3.3V +5%” to “3.3V + 0.3V” in the Operating Range table on Page # 3 Edited Test Conditions for ISB1 and ISB2 in the Electrical Characteristics table on Page # 3 Changed tDBE from 5 ns to 10 ns and 6 ns to 12 ns for -10 and -12 speed bins respectively on Page # 4 Moved footnote #15 to footnote # 5 Included spec for ICCDR = 100 mA in the Data Retention Characteristics table on Page# 5 Edited footnote # 12 from “VCC + 0.5V” to “VCC + 0.3V” Edited footnote # 13 to include “CE2 = VIH “ Edited footnote # 15 to include “CE2 transition HIGH” Edited footnote # 16 to include “BA/BB/BC/BD = VIH “ Edited footnote # 17 to include “CE2 goes LOW” Corrected typo on footnote #16 Referenced Footnotes # 5, 16 and 17 on to the Write Cycle No.3 on Page # 7 Corrected Truth table on Page #9 Updated the Ordering Information to include the BB119 Package Document #: 38-05635 Rev. *A Page 9 of 9