CY7C107BN-15VC

CY7C107BN 1M x 1 Static RAM Features Functional Description ■ High speed ❐ tAA = 15 ns ■ CMOS for optimum speed/power ■ Automatic power down when deselected ■ TTL-compatible inputs and outputs The CY7C107BN is a high performance CMOS static RAMs organized as 1,048,576 words by 1 bit. Easy memory expansion is provided by an active LOW Chip Enable (CE) and tristate drivers. The devices has an automatic power down feature that reduces power consumption by more than 65% when deselected. Writing to the devices is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the input pin (DIN) is written into the memory location specified on the address pins (A0 through A19). Reading from the devices is accomplished by taking Chip Enable (CE) LOW while Write Enable (WE) remains HIGH. Under these conditions, the contents of the memory location specified by the address pins appear on the data output (DOUT) pin. The output pin (DOUT) is placed in a high impedance state when the device is deselected (CE HIGH) or during a write operation (CE and WE LOW). The CY7C107BN is available in a standard 400-mil-wide SOJ. Logic Block Diagram DIN 512 x 2048 ARRAY DOUT POWER DOWN CE WE A9 A 10 A 11 A 12 A 13 A 14 A 15 A 16 A 17 A 18 A 19 COLUMN DECODER SENSE AMPS ROW DECODER INPUT BUFFER A0 A1 A2 A3 A4 A5 A6 A7 A8 Cypress Semiconductor Corporation Document #: 001-06426 Rev. *A • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised March 15, 2010 [+] Feedback CY7C107BN Pin Configuration Figure 1. 28-Pin SOJ (Top View) A10 A11 A12 A13 A14 A15 NC A16 A17 A18 A19 DOUT WE GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC A9 A8 A7 A6 A5 A4 NC A3 A2 A1 A0 DIN CE Selection Guide Description Maximum Access Time (ns) Maximum Operating Current (mA) Maximum CMOS Standby Current ISB2 (mA) Document #: 001-06426 Rev. *A 7C107BN-15 15 80 2 Page 2 of 8 [+] Feedback CY7C107BN DC Input Voltage[1]..................................-0.5V to VCC + 0.5V Maximum Ratings Exceeding the maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature .................................. -65°C to +150°C Ambient Temperature with Power Applied ............................................. -55°C to +125°C Supply Voltage on VCC Relative to GND[1] ..... -0.5V to +7.0V DC Voltage Applied to Outputs in High Z State[1] .....................................-0.5V to VCC + 0.5V Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage............................................ >2001V (per MIL-STD-883, Method 3015) Latch Up Current ..................................................... >200 mA Operating Range Range Commercial Ambient Temperature[2] 0°C to +70°C VCC 5V ± 10% Electrical Characteristics Over the Operating Range Parameter Description Test Conditions VOH Output HIGH Voltage VCC = Min, IOH = –4.0 mA VOL Output LOW Voltage VCC = Min, IOL = 8.0 mA VIH Input HIGH Voltage Voltage[1] 7C107BN-15 Min Max Unit 2.4 V 0.4 V 2.2 VCC + 0.3 V -0.3 0.8 V VIL Input LOW IIX Input Leakage Current GND < VI < VCC -1 +1 mA IOZ Output Leakage Current GND < VI < VCC, Output Disabled –5 +5 mA IOS Output Short Circuit Current[3] VCC = Max, VOUT = GND -300 mA ICC VCC Operating Supply Current VCC = Max, IOUT = 0 mA, f = fMAX = 1/tRC 80 mA ISB1 Automatic CE Power Down Current— TTL Inputs Max VCC, CE > VIH, VIN >VIH or VIN < VIL, f = f MAX 20 mA ISB2 Automatic CE Power Down Current — CMOS Inputs Max VCC, CE > VCC – 0.3V, VIN > VCC – 0.3V or VIN < 0.3V, f = 0 2 mA Capacitance[4] Parameter CIN: Addresses Description Input Capacitance CIN: Controls COUT Test Conditions TA = 25 × C, f = 1 MHz, VCC = 5.0V Output Capacitance Max Unit 7 pF 10 pF 10 pF Notes 1. VIL (min.) = –2.0V for pulse durations of less than 20 ns. 2. TA is the “Instant On” case temperature. 3. Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. 4. Tested initially and after any design or process changes that may affect these parameters. Document #: 001-06426 Rev. *A Page 3 of 8 [+] Feedback CY7C107BN Figure 2. AC Test Loads and Waveforms R1 480Ω 5V R1 480Ω 5V OUTPUT R2 255Ω 30 pF INCLUDING JIG AND SCOPE (a) Equivalent to: OUTPUT ALL INPUT PULSES 3.0V OUTPUT 5 pF R2 255Ω INCLUDING JIG AND SCOPE (b) 10% GND 90% 90% 10% ≤ 3 ns ≤ 3 ns THÉVENIN EQUIVALENT 167Ω 1.73V Switching Characteristics[5] Over the Operating Range Parameter Description 7C107BN-15 Min Max Unit READ CYCLE tRC Read Cycle Time tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE LOW to Data Valid tLZCE CE LOW to Low 15 Z[6] CE HIGH to High tPU CE LOW to Power Up tPD WRITE 15 3 3 ns ns 7 0 CE HIGH to Power Down ns ns 15 Z[6, 7] tHZCE ns ns ns 15 ns CYCLE[8] tWC Write Cycle Time 15 ns tSCE CE LOW to Write End 12 ns tAW Address Setup to Write End 12 ns tHA Address Hold from Write End 0 ns tSA Address Setup to Write Start 0 ns tPWE WE Pulse Width 12 ns tSD Data Setup to Write End 8 ns tHD Data Hold from Write End 0 ns Z[6] tLZWE WE HIGH to Low tHZWE WE LOW to High Z[6, 7] 3 ns 7 ns Notes 5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 6. At any given temperature and voltage condition, tHZCE is less than tLZCE and tHZWE is less than tLZWE for any given device. 7. tHZCE and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage. 8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these signals can terminate the write. The input data setup and hold timing should be referenced to the leading edge of the signal that terminates the write. Document #: 001-06426 Rev. *A Page 4 of 8 [+] Feedback CY7C107BN Switching Waveforms Figure 3. Read Cycle No. 1[10, 11] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Figure 4. Read Cycle No. 2[11, 12] ADDRESS tRC CE tACE tHZCE tLZCE DATA OUT VCC SUPPLY CURRENT HIGH IMPEDANCE HIGH IMPEDANCE DATA VALID tPD tPU 50% 50% ICC ISB Figure 5. Write Cycle No. 1 (CE Controlled)[13] tWC ADDRESS tSA tSCE CE tHA tAW tPWE WE tSD DATA IN DATA OUT tHD DATA VALID HIGH IMPEDANCE Notes 9. No input may exceed VCC + 0.5V. 10. Device is continuously selected, CE = VIL. 11. WE is HIGH for read cycle. 12. Address valid prior to or coincident with CE transition LOW. 13. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state. Document #: 001-06426 Rev. *A Page 5 of 8 [+] Feedback CY7C107BN Switching Waveforms (continued) Figure 6. Write Cycle No. 2 (WE Controlled)[13] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE tSD DATA IN tHD DATA VALID tHZWE DATA OUT tLZWE HIGH IMPEDANCE DATA UNDEFINED Truth Table CE WE DOUT Mode Power H X High Z Power Down Standby (ISB) L H Data Out Read Active (ICC) L L High Z Write Active (ICC) Ordering Information Speed (ns) 15 Ordering Code CY7C107BN-15VC Package Diagram 51-85032 Package Type 28-Pin (400-Mil) Molded SOJ Operating Range Commercial Contact your local sales representative regarding availability of these parts Document #: 001-06426 Rev. *A Page 6 of 8 [+] Feedback CY7C107BN Package Diagrams Figure 7. 28-Pin (400 Mil) Molded SOJ (51-85032) PIN 1 I.D 14 1 .435 .445 .395 .405 15 DIMENSIONS IN INCHES MIN. MAX. 28 .720 .730 SEATING PLANE NO CHAMFER .128 .148 .026 .032 .050 TYP. .015 .020 0.004 .025 MIN. .007 .013 .360 .380 NOTES : 1. PACKAGE WEIGHT : 1.24g 2. JEDEC REFERENCE : MS-027 Document #: 001-06426 Rev. *A 51-85032.*D Page 7 of 8 [+] Feedback CY7C107BN Document History Page Document Title: CY7C107BN 1M x 1 Static RAM Document Number: 001-06426 REV. ECN NO. Submission Date Orig. of Change Description of Change ** 423847 See ECN NXR New Data Sheet *A 2891262 03/12/2010 VKN Removed CY7C1007BN from the datasheet, Removed Industrial operating grade, Removed 28-Pin (300-Mil) Molded SOJ package, Updated 28-Pin (400-Mil) Molded SOJ POD Updated Ordering Infomation table Updated URLs in Sales, Solutions, and Legal Information Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. 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