CY7C11611KV18, CY7C11761KV18
CY7C11631KV18, CY7C11651KV18
®
18-Mbit QDR II+ SRAM 4-Word Burst
Architecture (2.5 Cycle Read Latency)
18-Mbit QDR® II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency)
Features
Functional Description
■
Separate independent read and write data ports
❐ Supports concurrent transactions
■
550 MHz clock for high bandwidth
■
4-word burst for reducing address bus frequency
■
Double Data Rate (DDR) interfaces on both read and write ports
(data transferred at 1100 MHz) at 550 MHz
■
Available in 2.5 clock cycle latency
■
Two input clocks (K and K) for precise DDR timing
❐ SRAM uses rising edges only
■
Echo clocks (CQ and CQ) simplify data capture in high speed
systems
■
Data valid pin (QVLD) to indicate valid data on the output
■
Single multiplexed address input bus latches address inputs
for read and write ports
■
Separate port selects for depth expansion
■
Synchronous internally self timed writes
■
QDR® II+ operates with 2.5 cycle read latency when DOFF is
asserted HIGH
The CY7C11611KV18, CY7C11761KV18, CY7C11631KV18,
and CY7C11651KV18 are 1.8V Synchronous Pipelined SRAMs,
equipped with QDR II+ architecture. Similar to QDR II architecture, QDR II+ architecture consists of two separate ports: the
read port and the write port to access the memory array. The
read port has dedicated data outputs to support read operations
and the write port has dedicated data inputs to support write
operations. QDR II+ architecture has separate data inputs and
data outputs to completely eliminate the need to “turn around”
the data bus that exists with common I/O devices. Each port is
accessed through a common address bus. Addresses for read
and write are latched on alternate rising edges of the input (K)
clock. Accesses to the QDR II+ read and write ports are
completely independent of one another. To maximize data
throughput, both read and write ports are equipped with DDR
interfaces. Each address location is associated with four 8-bit
words (CY7C11611KV18), 9-bit words (CY7C11761KV18),
18-bit
words
(CY7C11631KV18),
or
36-bit
words
(CY7C11651KV18) that burst sequentially into or out of the
device. Because data is transferred into and out of the device on
every rising edge of both input clocks (K and K), memory
bandwidth is maximized while simplifying system design by
eliminating bus “turn arounds”.
■
Operates similar to QDR I device with 1 cycle read latency when
DOFF is asserted LOW
Depth expansion is accomplished with port selects, which
enables each port to operate independently.
■
Available in x8, x9, x18, and x36 configurations
■
Full data coherency, providing most current data
■
Core VDD = 1.8V± 0.1V; I/O VDDQ = 1.4V to VDD [1]
❐ Supports both 1.5V and 1.8V I/O supply
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the K or K input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
■
HSTL inputs and variable drive HSTL output buffers
■
Available in 165-ball FBGA package (13 x 15 x 1.4 mm)
■
Offered in both Pb-free and non Pb-free packages
■
JTAG 1149.1 compatible test access port
■
Phase Locked Loop (PLL) for accurate data placement
These devices are down bonded from the 65 nm 72M
QDRII+/DDRII+ devices and hence have the same IDD/ISB1
values and JTAG ID code as the equivalent 72M device options.
For details refer to the application note AN53189, 65 nm
Technology Interim QDRII+/DDRII+ SRAM Device Family
Description.
Table 1. Selection Guide
Description
Configurations
550 500 450 400
MHz MHz MHz MHz Unit
Maximum Operating
Frequency
550
Maximum Operating
Current
x8 900
830
x9 900
830
CY7C11631KV18 – 1M x 18
x18 920
850
780
710
CY7C11651KV18 – 512K x 36
x36 1310 1210 1100 1000
With Read cycle latency of 2.5 cycles:
CY7C11611KV18 – 2M x 8
CY7C11761KV18 – 2M x 9
Cypress Semiconductor Corporation
Document Number: 001-53197 Rev. *B
•
198 Champion Court
•
500
San Jose, CA 95134-1709
450
400
MHz
760
690
mA
760
690
•
408-943-2600
Revised May 13, 2010
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CY7C11611KV18, CY7C11761KV18
CY7C11631KV18, CY7C11651KV18
Logic Block Diagram (CY7C11611KV18)
DOFF
Write
Reg
Address
Register
Read Add. Decode
512K x 8 Array
K
CLK
Gen.
Write
Reg
512K x 8 Array
K
Write
Reg
512K x 8 Array
Address
Register
Write
Reg
512K x 8 Array
A(18:0)
19
8
Write Add. Decode
D[7:0]
19
A(18:0)
RPS
Control
Logic
Read Data Reg.
CQ
32
VREF
WPS
16
Control
Logic
Reg.
16
NWS[1:0]
Reg.
CQ
Reg. 8
8
8
8
8
Q[7:0]
QVLD
Logic Block Diagram (CY7C11761KV18)
DOFF
Write
Reg
Address
Register
Read Add. Decode
512K x 9 Array
K
CLK
Gen.
Write
Reg
512K x 9 Array
K
Write
Reg
512K x 9 Array
Address
Register
Write
Reg
512K x 9 Array
A(18:0)
19
9
Write Add. Decode
D[8:0]
19
A(18:0)
RPS
Control
Logic
Read Data Reg.
CQ
36
VREF
WPS
18
Control
Logic
BWS[0]
18
Reg.
Reg.
Reg. 9
9
9
9
CQ
9
Q[8:0]
QVLD
Note
1. The Cypress QDR II+ devices surpass the QDR consortium specification and can support VDDQ = 1.4V to VDD.
Document Number: 001-53197 Rev. *B
Page 2 of 28
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CY7C11611KV18, CY7C11761KV18
CY7C11631KV18, CY7C11651KV18
Logic Block Diagram (CY7C11631KV18)
DOFF
Write
Reg
Address
Register
Read Add. Decode
256K x 18 Array
K
CLK
Gen.
Write
Reg
256K x 18 Array
K
Write
Reg
256K x 18 Array
Address
Register
Write
Reg
256K x 18 Array
A(17:0)
18
18
Write Add. Decode
D[17:0]
18
A(17:0)
RPS
Control
Logic
Read Data Reg.
CQ
72
VREF
WPS
36
Control
Logic
Reg.
36
BWS[1:0]
Reg.
CQ
Reg. 18
18
18
18
18
Q[17:0]
QVLD
Logic Block Diagram (CY7C11651KV18)
DOFF
Write
Reg
Address
Register
Read Add. Decode
128K x 36 Array
K
CLK
Gen.
Write
Reg
128K x 36 Array
K
Write
Reg
128K x 36 Array
Address
Register
Write
Reg
128K x 36 Array
A(16:0)
17
36
Write Add. Decode
D[35:0]
17
A(16:0)
RPS
Control
Logic
Read Data Reg.
CQ
144
VREF
WPS
72
Control
Logic
BWS[3:0]
72
Reg.
Reg.
Reg. 36
36
36
36
CQ
36
Q[35:0]
QVLD
Document Number: 001-53197 Rev. *B
Page 3 of 28
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CY7C11611KV18, CY7C11761KV18
CY7C11631KV18, CY7C11651KV18
Contents
18-Mbit QDR® II+ SRAM 4-Word Burst Architecture
(2.5 Cycle Read Latency) ................................................. 1
Features ............................................................................. 1
Configurations .................................................................. 1
Functional Description ..................................................... 1
Logic Block Diagram (CY7C11611KV18) ........................ 2
Logic Block Diagram (CY7C11761KV18) ........................ 2
Logic Block Diagram (CY7C11631KV18) ........................ 3
Logic Block Diagram (CY7C11651KV18) ........................ 3
Contents ............................................................................ 4
Pin Configuration ............................................................. 5
165-Ball FBGA (13 x 15 x 1.4 mm) Pinout .................. 5
Functional Overview ........................................................ 9
Read Operations ......................................................... 9
Write Operations ......................................................... 9
Byte Write Operations ................................................. 9
Concurrent Transactions ............................................. 9
Depth Expansion ....................................................... 10
Programmable Impedance ........................................ 10
Echo Clocks .............................................................. 10
Valid Data Indicator (QVLD) ...................................... 10
PLL ............................................................................ 10
Application Example ...................................................... 10
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 13
Disabling the JTAG Feature ...................................... 13
Test Access Port—Test Clock ................................... 13
Test Mode Select (TMS) ........................................... 13
Test Data-In (TDI) ..................................................... 13
Document Number: 001-53197 Rev. *B
Test Data-Out (TDO) ................................................. 13
Performing a TAP Reset ........................................... 13
TAP Registers ........................................................... 13
TAP Instruction Set ................................................... 13
TAP Electrical Characteristics ...................................... 16
TAP AC Switching Characteristics ............................... 17
TAP Timing and Test Conditions .................................. 17
Power Up Sequence in QDR II+ SRAM ......................... 20
Power Up Sequence ................................................. 20
PLL Constraints ......................................................... 20
Maximum Ratings ........................................................... 21
Operating Range ............................................................. 21
Neutron Soft Error Immunity ......................................... 21
DC Electrical Characteristics ..................................... 21
AC Electrical Characteristics ..................................... 22
Capacitance .................................................................... 23
Thermal Resistance ........................................................ 23
Switching Characteristics .............................................. 24
Switching Waveforms .................................................... 25
Read/Write/Deselect Sequence [31, 32, 33] ................. 25
Ordering Information ...................................................... 26
Package Diagram ............................................................ 26
Document History Page ................................................. 27
Sales, Solutions, and Legal Information ...................... 28
Worldwide Sales and Design Support ....................... 28
Products .................................................................... 28
PSoC Solutions ......................................................... 28
Page 4 of 28
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CY7C11611KV18, CY7C11761KV18
CY7C11631KV18, CY7C11651KV18
Pin Configuration
The pin configuration for CY7C11611KV18, CY7C11761KV18, CY7C11631KV18, and CY7C11651KV18 follows.[2]
165-Ball FBGA (13 x 15 x 1.4 mm) Pinout
CY7C11611KV18 (2M x 8)
1
2
3
4
A
CQ
B
NC
NC/72M
A
WPS
NC
NC
A
C
NC
NC
NC
VSS
D
NC
D4
NC
VSS
5
6
7
8
9
10
11
NWS1
K
NC/144M
NC/288M
K
NWS0
RPS
A
NC/36M
CQ
A
NC
NC
Q3
A
NC
A
VSS
NC
NC
D3
VSS
VSS
VSS
VSS
NC
NC
NC
E
NC
NC
Q4
VDDQ
VSS
VSS
VSS
VDDQ
NC
D2
Q2
F
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
G
NC
D5
Q5
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
H
DOFF
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
Q1
D1
K
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
L
NC
Q6
D6
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
Q0
M
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
NC
NC
D0
N
NC
D7
NC
VSS
A
A
A
VSS
NC
NC
NC
P
NC
NC
Q7
A
A
QVLD
A
A
NC
NC
NC
R
TDO
TCK
A
A
A
NC
A
A
A
TMS
TDI
1
2
3
4
5
6
7
8
9
10
11
A
CQ
NC/72M
A
WPS
NC
K
NC/144M
RPS
A
NC/36M
CQ
B
NC
NC
NC
A
NC/288M
K
BWS0
A
NC
NC
Q4
C
NC
NC
NC
VSS
A
NC
A
VSS
NC
NC
D4
D
NC
D5
NC
VSS
VSS
VSS
VSS
VSS
NC
NC
NC
E
NC
NC
Q5
VDDQ
VSS
VSS
VSS
VDDQ
NC
D3
Q3
F
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
CY7C11761KV18 (2M x 9)
G
NC
D6
Q6
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
H
DOFF
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
Q2
D2
K
NC
NC
NC
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
NC
L
NC
Q7
D7
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
Q1
M
NC
NC
NC
VSS
VSS
VSS
VSS
VSS
NC
NC
D1
N
NC
D8
NC
VSS
A
A
A
VSS
NC
NC
NC
P
NC
NC
Q8
A
A
QVLD
A
A
NC
D0
Q0
R
TDO
TCK
A
A
A
NC
A
A
A
TMS
TDI
Note
2. NC/36M, NC/72M, NC/144M, and NC/288M are not connected to the die and can be tied to any voltage level.
Document Number: 001-53197 Rev. *B
Page 5 of 28
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CY7C11611KV18, CY7C11761KV18
CY7C11631KV18, CY7C11651KV18
Pin Configuration
(continued)
The pin configuration for CY7C11611KV18, CY7C11761KV18, CY7C11631KV18, and CY7C11651KV18 follows.[2]
165-Ball FBGA (13 x 15 x 1.4 mm) Pinout
CY7C11631KV18 (1M x 18)
1
2
3
NC/144M NC/36M
4
5
6
7
8
9
10
11
A
CQ
WPS
BWS1
K
NC/288M
RPS
A
NC/72M
CQ
B
NC
Q9
D9
A
NC
K
BWS0
A
NC
NC
Q8
C
NC
NC
D10
VSS
A
NC
A
VSS
NC
Q7
D8
D
NC
D11
Q10
VSS
VSS
VSS
VSS
VSS
NC
NC
D7
E
NC
NC
Q11
VDDQ
VSS
VSS
VSS
VDDQ
NC
D6
Q6
F
NC
Q12
D12
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
Q5
G
NC
D13
Q13
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
D5
H
DOFF
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
NC
NC
D14
VDDQ
VDD
VSS
VDD
VDDQ
NC
Q4
D4
K
NC
NC
Q14
VDDQ
VDD
VSS
VDD
VDDQ
NC
D3
Q3
L
NC
Q15
D15
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
Q2
M
NC
NC
D16
VSS
VSS
VSS
VSS
VSS
NC
Q1
D2
N
NC
D17
Q16
VSS
A
A
A
VSS
NC
NC
D1
P
NC
NC
Q17
A
A
QVLD
A
A
NC
D0
Q0
R
TDO
TCK
A
A
A
NC
A
A
A
TMS
TDI
1
2
3
4
5
6
7
8
9
10
11
WPS
BWS2
K
BWS1
RPS
D18
A
BWS3
K
BWS0
A
CY7C11651KV18 (512K x 36)
A
CQ
NC/288M NC/72M
B
Q27
Q18
C
D27
Q28
D19
VSS
A
NC
A
VSS
D
D28
D20
Q19
VSS
VSS
VSS
VSS
VSS
E
Q29
D29
Q20
VDDQ
VSS
VSS
VSS
VDDQ
F
Q30
Q21
D21
VDDQ
VDD
VSS
VDD
VDDQ
NC/36M NC/144M
D17
CQ
Q17
Q8
D16
Q7
D8
Q16
D15
D7
Q15
D6
Q6
D14
Q14
Q5
G
D30
D22
Q22
VDDQ
VDD
VSS
VDD
VDDQ
Q13
D13
D5
H
DOFF
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
D31
Q31
D23
VDDQ
VDD
VSS
VDD
VDDQ
D12
Q4
D4
K
Q32
D32
Q23
VDDQ
VDD
VSS
VDD
VDDQ
Q12
D3
Q3
L
Q33
Q24
D24
VDDQ
VSS
VSS
VSS
VDDQ
D11
Q11
Q2
M
D33
Q34
D25
VSS
VSS
VSS
VSS
VSS
D10
Q1
D2
N
D34
D26
Q25
VSS
A
A
A
VSS
Q10
D9
D1
P
Q35
D35
Q26
A
A
QVLD
A
A
Q9
D0
Q0
R
TDO
TCK
A
A
A
NC
A
A
A
TMS
TDI
Document Number: 001-53197 Rev. *B
Page 6 of 28
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CY7C11611KV18, CY7C11761KV18
CY7C11631KV18, CY7C11651KV18
Table 2. Pin Definitions
Pin Name
I/O
Pin Description
D[x:0]
InputData Input Signals. Sampled on the rising edge of K and K clocks when valid write operations are active.
Synchronous CY7C11611KV18 − D[7:0]
CY7C11761KV18 − D[8:0]
CY7C11631KV18 − D[17:0]
CY7C11651KV18 − D[35:0]
WPS
InputWrite Port Select − Active LOW. Sampled on the rising edge of the K clock. When asserted active, a
Synchronous write operation is initiated. Deasserting deselects the write port. Deselecting the write port ignores D[x:0].
NWS0,
NWS1,
InputNibble Write Select 0, 1 − Active LOW (CY7C11611KV18 Only). Sampled on the rising edge of the K
Synchronous and K clocks when write operations are active. Used to select which nibble is written into the device
during the current portion of the write operations. NWS0 controls D[3:0] and NWS1 controls D[7:4].
All the Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble Write Select
ignores the corresponding nibble of data and it is not written into the device.
BWS0,
BWS1,
BWS2,
BWS3
InputByte Write Select 0, 1, 2 and 3 − Active LOW. Sampled on the rising edge of the K and K clocks when
Synchronous write operations are active. Used to select which byte is written into the device during the current portion
of the write operations. Bytes not written remain unaltered.
CY7C11761KV18 − BWS0 controls D[8:0]
CY7C11631KV18 − BWS0 controls D[8:0] and BWS1 controls D[17:9].
CY7C11651KV18 − BWS0 controls D[8:0], BWS1 controls D[17:9],
BWS2 controls D[26:18] and BWS3 controls D[35:27].
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select
ignores the corresponding byte of data and it is not written into the device.
A
InputAddress Inputs. Sampled on the rising edge of the K clock during active read and write operations. These
Synchronous address inputs are multiplexed for both read and write operations. Internally, the device is organized as
2M x 8 (4 arrays each of 512K x 8) for CY7C11611KV18, 2M x 9 (4 arrays each of 512K x 9) for
CY7C11761KV18, 1M x 18 (4 arrays each of 256K x 18) for CY7C11631KV18 and 512K x 36 (4 arrays
each of 128K x 36) for CY7C11651KV18. Therefore, only 19 address inputs are needed to access the
entire memory array of CY7C11611KV18 and CY7C11761KV18, 18 address inputs for CY7C11631KV18
and 17 address inputs for CY7C11651KV18. These inputs are ignored when the appropriate port is
deselected.
Q[x:0]
OutputsData Output Signals. These pins drive out the requested data when the read operation is active. Valid
Synchronous data is driven out on the rising edge of the K and K clocks during read operations. On deselecting the
read port, Q[x:0] are automatically tristated.
CY7C11611KV18 − Q[7:0]
CY7C11761KV18 − Q[8:0]
CY7C11631KV18 − Q[17:0]
CY7C11651KV18 − Q[35:0]
RPS
InputRead Port Select − Active LOW. Sampled on the rising edge of positive input clock (K). When active, a
Synchronous read operation is initiated. Deasserting deselects the read port. When deselected, the pending access is
allowed to complete and the output drivers are automatically tristated following the next rising edge of the
K clock. Each read access consists of a burst of four sequential transfers.
QVLD
Valid output
indicator
Valid Output Indicator. The Q Valid indicates valid output data. QVLD is edge aligned with CQ and CQ.
K
Input Clock
Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device
and to drive out data through Q[x:0]. All accesses are initiated on the rising edge of K.
K
Input Clock
Negative Input Clock Input. K is used to capture synchronous inputs being presented to the device and
to drive out data through Q[x:0].
CQ
Echo Clock
Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input clock
(K) of the QDR II+. The timings for the echo clocks are shown in the Switching Characteristics on page 24.
CQ
Echo Clock
Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input clock
(K) of the QDR II+.The timings for the echo clocks are shown in the Switching Characteristics on page 24.
Document Number: 001-53197 Rev. *B
Page 7 of 28
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CY7C11611KV18, CY7C11761KV18
CY7C11631KV18, CY7C11651KV18
Table 2. Pin Definitions (continued)
Pin Name
I/O
Pin Description
ZQ
Input
Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus
impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 x RQ, where RQ is a resistor connected
between ZQ and ground. Alternatively, this pin can be connected directly to VDDQ, which enables the
minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.
DOFF
Input
PLL Turn Off − Active LOW. Connecting this pin to ground turns off the PLL inside the device. The timings
in the PLL turned off operation differs from those listed in this data sheet. For normal operation, this pin
can be connected to a pull up through a 10 KΩ or less pull up resistor. The device behaves in QDR I
mode when the PLL is turned off. In this mode, the device can be operated at a frequency of up to 167
MHz with QDR I timing.
TDO
Output
TCK
Input
TCK Pin for JTAG.
TDI
Input
TDI Pin for JTAG.
TMS
Input
TMS Pin for JTAG.
NC
N/A
Not Connected to the Die. Can be tied to any voltage level.
NC/144M
N/A
Not Connected to the Die. Can be tied to any voltage level.
NC/288M
N/A
Not Connected to the Die. Can be tied to any voltage level.
VREF
VDD
VSS
VDDQ
InputReference
TDO for JTAG.
Reference Voltage Input. Static input used to set the reference level for HSTL inputs, outputs, and AC
measurement points.
Power Supply Power Supply Inputs to the Core of the Device.
Ground
Ground for the Device.
Power Supply Power Supply Inputs for the Outputs of the Device.
Document Number: 001-53197 Rev. *B
Page 8 of 28
[+] Feedback
CY7C11611KV18, CY7C11761KV18
CY7C11631KV18, CY7C11651KV18
Functional Overview
The CY7C11611KV18, CY7C11761KV18, CY7C11631KV18,
CY7C11651KV18 are synchronous pipelined Burst SRAMs
equipped with a read port and a write port. The read port is
dedicated to read operations and the write port is dedicated to
write operations. Data flows into the SRAM through the write port
and flows out through the read port. These devices multiplex the
address inputs to minimize the number of address pins required.
By having separate read and write ports, the QDR II+ completely
eliminates the need to “turn around” the data bus and avoids any
possible data contention, thereby simplifying system design.
Each access consists of four 8-bit data transfers in the case of
CY7C11611KV18, four 9-bit data transfers in the case of
CY7C11761KV18, four 18-bit data transfers in the case of
CY7C11631KV18, and four 36-bit data transfers in the case of
CY7C11651KV18, in two clock cycles.
These devices operate with a read latency of two and half cycles
when DOFF pin is tied HIGH. When DOFF pin is set LOW or
connected to VSS, then device behaves in QDR I mode with a
read latency of one clock cycle.
Accesses for both ports are initiated on the positive input clock
(K). All synchronous input and output timing are referenced from
the rising edge of the input clocks (K and K).
All synchronous data inputs (D[x:0]) pass through input registers
controlled by the input clocks (K and K). All synchronous data
outputs (Q[x:0]) also pass through output registers controlled by
the rising edge of the input clocks (K and K).
transferred out of the device on every rising edge of the input
clocks (K and K).
When the read port is deselected, the CY7C11631KV18 first
completes the pending read transactions. Synchronous internal
circuitry automatically tristates the outputs following the next
rising edge of the negative input clock (K). This enables a
seamless transition between devices without the insertion of wait
states in a depth expanded memory.
Write Operations
Write operations are initiated by asserting WPS active at the
rising edge of the positive input clock (K). On the following K
clock rise, the data presented to D[17:0] is latched and stored into
the lower 18-bit write data register, provided BWS[1:0] are both
asserted active. On the subsequent rising edge of the negative
input clock (K) the information presented to D[17:0] is also stored
into the write data register, provided BWS[1:0] are both asserted
active. This process continues for one more cycle until four 18-bit
words (a total of 72 bits) of data are stored in the SRAM. The 72
bits of data are then written into the memory array at the specified
location. Therefore, write accesses to the device cannot be
initiated on two consecutive K clock rises. The internal logic of
the device ignores the second write request. Write accesses can
be initiated on every other rising edge of the positive input clock
(K). Doing so pipelines the data flow such that 18 bits of data can
be transferred into the device on every rising edge of the input
clocks (K and K).
All synchronous control (RPS, WPS, NWS[x:0], BWS[x:0]) inputs
pass through input registers controlled by the rising edge of the
input clocks (K and K).
When deselected, the write port ignores all inputs after the
pending write operations have been completed.
CY7C11631KV18 is described in the following sections. The
same basic descriptions apply to CY7C11611KV18,
CY7C11761KV18 and CY7C11651KV18.
Byte Write Operations
Read Operations
The CY7C11631KV18 is organized internally as four arrays of
256K x 18. Accesses are completed in a burst of four sequential
18-bit data words. Read operations are initiated by asserting
RPS active at the rising edge of the positive input clock (K). The
address presented to the address inputs is stored in the read
address register. Following the next two K clock rise, the corresponding lowest order 18-bit word of data is driven onto the
Q[17:0] using K as the output timing reference. On the subsequent rising edge of K, the next 18-bit data word is driven onto
the Q[17:0]. This process continues until all four 18-bit data words
have been driven out onto Q[17:0]. The requested data is valid
0.45 ns from the rising edge of the input clock (K or K). To
maintain the internal logic, each read access must be allowed to
complete. Each read access consists of four 18-bit data words
and takes two clock cycles to complete. Therefore, read
accesses to the device cannot be initiated on two consecutive K
clock rises. The internal logic of the device ignores the second
read request. Read accesses can be initiated on every other K
clock rise. Doing so pipelines the data flow such that data is
Document Number: 001-53197 Rev. *B
Byte write operations are supported by the CY7C11631KV18. A
write operation is initiated as described in the Write Operations
section. The bytes that are written are determined by BWS0 and
BWS1, which are sampled with each set of 18-bit data words.
Asserting the appropriate Byte Write Select input during the data
portion of a write latches the data being presented and writes it
into the device. Deasserting the Byte Write Select input during
the data portion of a write enables the data stored in the device
for that byte to remain unaltered. This feature can be used to
simplify read, modify, or write operations to a byte write
operation.
Concurrent Transactions
The read and write ports on the CY7C11631KV18 operates
completely independently of one another. As each port latches
the address inputs on different clock edges, the user can read or
write to any location, regardless of the transaction on the other
port. If the ports access the same location when a read follows a
write in successive clock cycles, the SRAM delivers the most
recent information associated with the specified address
location. This includes forwarding data from a write cycle that
was initiated on the previous K clock rise.
Page 9 of 28
[+] Feedback
CY7C11611KV18, CY7C11761KV18
CY7C11631KV18, CY7C11651KV18
Read access and write access must be scheduled such that one
transaction is initiated on any clock cycle. If both ports are
selected on the same K clock rise, the arbitration depends on the
previous state of the SRAM. If both ports are deselected, the
read port takes priority. If a read was initiated on the previous
cycle, the write port takes priority (as read operations cannot be
initiated on consecutive cycles). If a write was initiated on the
previous cycle, the read port takes priority (as write operations
cannot be initiated on consecutive cycles). Therefore, asserting
both port selects active from a deselected state results in alternating read or write operations being initiated, with the first
access being a read.
Depth Expansion
The CY7C11631KV18 has a port select input for each port. This
enables easy depth expansion. Both port selects are sampled on
the rising edge of the positive input clock only (K). Each port
select input can deselect the specified port. Deselecting a port
does not affect the other port. All pending transactions (read and
write) are completed before the device is deselected.
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin
on the SRAM and VSS to allow the SRAM to adjust its output
driver impedance. The value of RQ must be 5X the value of the
intended line impedance driven by the SRAM, the allowable
range of RQ to guarantee impedance matching with a tolerance
of ±15% is between 175Ω and 350Ω, with VDDQ = 1.5V. The
output impedance is adjusted every 1024 cycles upon power up
to account for drifts in supply voltage and temperature.
Echo Clocks
Echo clocks are provided on the QDR II+ to simplify data capture
on high speed systems. Two echo clocks are generated by the
QDR II+. CQ is referenced with respect to K and CQ is referenced with respect to K. These are free-running clocks and are
synchronized to the input clock of the QDR II+. The timing for the
echo clocks is shown in the Switching Characteristics on page
24.
Valid Data Indicator (QVLD)
QVLD is provided on the QDR II+ to simplify data capture on high
speed systems. The QVLD is generated by the QDR II+ device
along with data output. This signal is also edge-aligned with the
echo clock and follows the timing of any data pin. This signal is
asserted half a cycle before valid data arrives.
PLL
These chips use a PLL that is designed to function between 120
MHz and the specified maximum clock frequency. During power
up, when the DOFF is tied HIGH, the PLL is locked after 20 μs
of stable clock. The PLL can also be reset by slowing or stopping
the input clocks K and K for a minimum of 30 ns. However, it is
not necessary to reset the PLL to lock to the desired frequency.
The PLL automatically locks 20 μs after a stable clock is
presented. The PLL may be disabled by applying ground to the
DOFF pin. When the PLL is turned off, the device behaves in
QDR I mode (with one cycle latency and a longer access time).
For more information, refer to the application note, PLL Considerations in QDRII/DDRII/QDRII+/DDRII+.
Application Example
Figure 1
shows two QDR II+ used in an application.
Figure 1. Application Example
Vt
R
DATA IN
DATA OUT
Address
ZQ
SRAM #1 CQ/CQ
Q
D
A RPS WPS BWS K K
RQ = 250 ohms
SRAM #2
RQ = 250 ohms
CQ/CQ
Q
RPS WPS BWS K K
D
A
R
R
BUS MASTER RPS
(CPU or ASIC) WPS
ZQ
Vt
Vt
BWS
CLKIN1/CLKIN1
CLKIN2/CLKIN2
Source K
Source K
R
Document Number: 001-53197 Rev. *B
R = 50ohms, Vt = VDDQ /2
Page 10 of 28
[+] Feedback
CY7C11611KV18, CY7C11761KV18
CY7C11631KV18, CY7C11651KV18
The truth table for CY7C11611KV18, CY7C11761KV18, CY7C11631KV18, and CY7C11651KV18 follows. [3, 4, 5, 6, 7, 8]
Table 3. Truth Table
Operation
K
RPS WPS
[9]
DQ
DQ
DQ
DQ
[10]
D(A) at K(t + 1)↑ D(A + 1) at K(t + 1)↑ D(A + 2) at K(t + 2)↑ D(A + 3) at K(t + 2)↑
Write Cycle:
Load address on the rising
edge of K; input write data
on two consecutive K and
K rising edges.
L-H
H
Read Cycle:
(2.5 cycle Latency)
Load address on the rising
edge of K; wait two and
half cycles; read data on
two consecutive K and K
rising edges.
L-H
L [10]
X
Q(A) at K(t + 2)↑ Q(A + 1) at K(t + 3)↑ Q(A + 2) at K(t + 3)↑ Q(A + 3) at K(t + 4)↑
NOP: No Operation
L-H
H
H
D=X
Q = High Z
D=X
Q = High Z
D=X
Q = High Z
D=X
Q = High Z
Stopped
X
X
Previous State
Previous State
Previous State
Previous State
Standby: Clock Stopped
L
The write cycle description table for CY7C11611KV18 and CY7C11631KV18 follows. [3, 11]
Table 4. Write Cycle Descriptions
BWS0/ BWS1/
K
K
L
L–H
–
L
L
–
L
H
L–H
L
H
–
H
L
L–H
H
L
–
H
H
L–H
H
H
–
NWS0
NWS1
L
Comments
During the data portion of a write sequence:
CY7C11611KV18 − both nibbles (D[7:0]) are written into the device.
CY7C11631KV18 − both bytes (D[17:0]) are written into the device.
L-H During the data portion of a write sequence:
CY7C11611KV18 − both nibbles (D[7:0]) are written into the device.
CY7C11631KV18 − both bytes (D[17:0]) are written into the device.
–
During the data portion of a write sequence:
CY7C11611KV18 − only the lower nibble (D[3:0]) is written into the device, D[7:4] remains unaltered.
CY7C11631KV18 − only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered.
L–H During the data portion of a write sequence:
CY7C11611KV18 − only the lower nibble (D[3:0]) is written into the device, D[7:4] remains unaltered.
CY7C11631KV18 − only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered.
–
During the data portion of a write sequence:
CY7C11611KV18 − only the upper nibble (D[7:4]) is written into the device, D[3:0] remains unaltered.
CY7C11631KV18 − only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.
L–H During the data portion of a write sequence:
CY7C11611KV18 − only the upper nibble (D[7:4]) is written into the device, D[3:0] remains unaltered.
CY7C11631KV18 − only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.
–
No data is written into the devices during this portion of a write operation.
L–H No data is written into the devices during this portion of a write operation.
Notes
3. X = “Don't Care,” H = Logic HIGH, L = Logic LOW, ↑represents rising edge.
4. Device powers up deselected with the outputs in a tristate condition.
5. “A” represents address location latched by the devices when transaction was initiated. A + 1, A + 2, and A + 3 represents the address sequence in the burst.
6. “t” represents the cycle at which a read/write operation is started. t + 1, t + 2, and t + 3 are the first, second and third clock cycles respectively succeeding the “t” clock cycle.
7. Data inputs are registered at K and K rising edges. Data outputs are delivered on K and K rising edges as well.
8. It is recommended that K = K = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically.
9. If this signal was LOW to initiate the previous cycle, this signal becomes a “Don’t Care” for this operation.
10. This signal was HIGH on previous K clock rise. Initiating consecutive read or write operations on consecutive K clock rises is not permitted. The device ignores the
second read or write request.
11. Is based on a write cycle that was initiated in accordance with Table 4. NWS0, NWS1, BWS0, BWS1, BWS2, and BWS3 can be altered on different portions of a write
cycle, as long as the setup and hold requirements are achieved.
Document Number: 001-53197 Rev. *B
Page 11 of 28
[+] Feedback
CY7C11611KV18, CY7C11761KV18
CY7C11631KV18, CY7C11651KV18
The write cycle description table for CY7C11761KV18 follows. [3, 11]
Table 5. Write Cycle Descriptions
BWS0
K
K
Comments
L
L–H
–
During the data portion of a write sequence, the single byte (D[8:0]) is written into the device.
L
–
L–H
During the data portion of a write sequence, the single byte (D[8:0]) is written into the device.
H
L–H
–
No data is written into the device during this portion of a write operation.
H
–
L–H
No data is written into the device during this portion of a write operation.
The write cycle description table for CY7C11651KV18 follows. [3, 11]
Table 6. Write Cycle Descriptions
BWS0
BWS1
BWS2
BWS3
K
K
Comments
L
L
L
L
L–H
–
During the data portion of a write sequence, all four bytes (D[35:0]) are written into
the device.
L
L
L
L
–
L
H
H
H
L–H
L
H
H
H
–
H
L
H
H
L–H
H
L
H
H
–
H
H
L
H
L–H
H
H
L
H
–
H
H
H
L
L–H
H
H
H
L
–
H
H
H
H
L–H
H
H
H
H
–
Document Number: 001-53197 Rev. *B
L–H During the data portion of a write sequence, all four bytes (D[35:0]) are written into
the device.
–
During the data portion of a write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] remains unaltered.
L–H During the data portion of a write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] remains unaltered.
–
During the data portion of a write sequence, only the byte (D[17:9]) is written into
the device. D[8:0] and D[35:18] remains unaltered.
L–H During the data portion of a write sequence, only the byte (D[17:9]) is written into
the device. D[8:0] and D[35:18] remains unaltered.
–
During the data portion of a write sequence, only the byte (D[26:18]) is written into
the device. D[17:0] and D[35:27] remains unaltered.
L–H During the data portion of a write sequence, only the byte (D[26:18]) is written into
the device. D[17:0] and D[35:27] remains unaltered.
–
During the data portion of a write sequence, only the byte (D[35:27]) is written into
the device. D[26:0] remains unaltered.
L–H During the data portion of a write sequence, only the byte (D[35:27]) is written into
the device. D[26:0] remains unaltered.
–
No data is written into the device during this portion of a write operation.
L–H No data is written into the device during this portion of a write operation.
Page 12 of 28
[+] Feedback
CY7C11611KV18, CY7C11761KV18
CY7C11631KV18, CY7C11651KV18
IEEE 1149.1 Serial Boundary Scan (JTAG)
Instruction Register
These SRAMs incorporate a serial boundary scan Test Access
Port (TAP) in the FBGA package. This part is fully compliant with
IEEE Standard #1149.1-2001. The TAP operates using JEDEC
standard 1.8V I/O logic levels.
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO pins, as shown in Figure 3 on page 16. Upon power up,
the instruction register is loaded with the IDCODE instruction. It
is also loaded with the IDCODE instruction if the controller is
placed in a reset state, as described in the previous section.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternatively
be connected to VDD through a pull up resistor. TDO must be left
unconnected. Upon power up, the device comes up in a reset
state, which does not interfere with the operation of the device.
Test Access Port—Test Clock
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. This pin may be left
unconnected if the TAP is not used. The pin is pulled up internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI pin is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. For information on
loading the instruction register, see Figure 2 on page 15. TDI is
internally pulled up and can be unconnected if the TAP is unused
in an application. TDI is connected to the most significant bit
(MSB) on any register.
Test Data-Out (TDO)
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary “01” pattern to allow for
fault isolation of the board level serial test path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This enables shifting of data through the SRAM
with minimal delay. The bypass register is set LOW (VSS) when
the BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all of the input and
output pins on the SRAM. Several No Connect (NC) pins are also
included in the scan register to reserve pins for higher density
devices.
The boundary scan register is loaded with the contents of the
RAM input and output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and TDO
pins when the controller is moved to the Shift-DR state. The
EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions can
be used to capture the contents of the input and output ring.
Table 10 on page 19 shows the order in which the bits are
connected. Each bit corresponds to one of the bumps on the
SRAM package. The MSB of the register is connected to TDI,
and the LSB is connected to TDO.
Identification (ID) Register
The TDO output pin is used to serially clock data out from the
registers. The output is active, depending upon the current state
of the TAP state machine (see Table 9 on page 18). The output
changes on the falling edge of TCK. TDO is connected to the
least significant bit (LSB) of any register.
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in Table 7 on page 18.
Performing a TAP Reset
TAP Instruction Set
A Reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This Reset does not affect the operation of the
SRAM and can be performed while the SRAM is operating. At
power up, the TAP is reset internally to ensure that TDO comes
up in a High Z state.
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in Table 9 on page
18. Three of these instructions are listed as RESERVED and
must not be used. The other five instructions are described in this
section in detail.
TAP Registers
Registers are connected between the TDI and TDO pins to scan
the data in and out of the SRAM test circuitry. Only one register
can be selected at a time through the instruction registers. Data
is serially loaded into the TDI pin on the rising edge of TCK. Data
is output on the TDO pin on the falling edge of TCK.
Document Number: 001-53197 Rev. *B
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO pins. To execute
the instruction after it is shifted in, the TAP controller must be
moved into the Update-IR state.
Page 13 of 28
[+] Feedback
CY7C11611KV18, CY7C11761KV18
CY7C11631KV18, CY7C11651KV18
IDCODE
The IDCODE instruction loads a vendor-specific, 32-bit code into
the instruction register. It also places the instruction register
between the TDI and TDO pins and shifts the IDCODE out of the
device when the TAP controller enters the Shift-DR state. The
IDCODE instruction is loaded into the instruction register at
power up or whenever the TAP controller is supplied a
Test-Logic-Reset state.
SAMPLE Z
The SAMPLE Z instruction connects the boundary scan register
between the TDI and TDO pins when the TAP controller is in a
Shift-DR state. The SAMPLE Z command puts the output bus
into a High Z state until the next command is supplied during the
Update IR state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the input and output pins is captured
in the boundary scan register.
PRELOAD places an initial data pattern at the latched parallel
outputs of the boundary scan register cells before the selection
of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required, that is, while the data
captured is shifted out, the preloaded data can be shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO pins. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
EXTEST
The EXTEST instruction drives the preloaded data out through
the system output pins. This instruction also connects the
boundary scan register for serial access between the TDI and
TDO in the Shift-DR controller state.
EXTEST OUTPUT BUS TRISTATE
IEEE Standard 1149.1 mandates that the TAP controller be able
to put the output bus into a tristate mode.
The user must be aware that the TAP controller clock can only
operate at a frequency up to 20 MHz, while the SRAM clock
operates more than an order of magnitude faster. Because there
is a large difference in the clock frequencies, it is possible that
during the Capture-DR state, an input or output undergoes a
transition. The TAP may then try to capture a signal while in
transition (metastable state). This does not harm the device, but
there is no guarantee as to the value that is captured.
Repeatable results may not be possible.
The boundary scan register has a special bit located at bit #108.
When this scan cell, called the “extest output bus tristate,” is
latched into the preload register during the Update-DR state in
the TAP controller, it directly controls the state of the output
(Q-bus) pins, when the EXTEST is entered as the current
instruction. When HIGH, it enables the output buffers to drive the
output bus. When LOW, this bit places the output bus into a High
Z condition.
To guarantee that the boundary scan register captures the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture setup plus hold
times (tCS and tCH). The SRAM clock input might not be captured
correctly if there is no way in a design to stop (or slow) the clock
during a SAMPLE/PRELOAD instruction. If this is an issue, it is
still possible to capture all other signals and simply ignore the
value of the CK and CK captured in the boundary scan register.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that cell,
during the Shift-DR state. During Update-DR, the value loaded
into that shift-register cell latches into the preload register. When
the EXTEST instruction is entered, this bit directly controls the
output Q-bus pins. Note that this bit is preset HIGH to enable the
output when the device is powered up, and also when the TAP
controller is in the Test-Logic-Reset state.
After the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.
Reserved
Document Number: 001-53197 Rev. *B
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Page 14 of 28
[+] Feedback
CY7C11611KV18, CY7C11761KV18
CY7C11631KV18, CY7C11651KV18
The state diagram for the TAP controller follows. [12]
Figure 2. TAP Controller State Diagram
1
TEST-LOGIC
RESET
0
0
TEST-LOGIC/
IDLE
1
SELECT
DR-SCAN
1
1
SELECT
IR-SCAN
0
0
1
1
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
0
SHIFT-IR
1
1
EXIT1-DR
1
EXIT1-IR
0
1
0
PAUSE-DR
0
PAUSE-IR
1
0
1
0
EXIT2-DR
0
EXIT2-IR
1
1
UPDATE-IR
UPDATE-DR
1
0
0
1
0
Note
12. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
Document Number: 001-53197 Rev. *B
Page 15 of 28
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Figure 3. TAP Controller Block Diagram
0
Bypass Register
2
Selection
Circuitry
TDI
1
0
Selection
Circuitry
Instruction Register
31
30
29
.
.
2
1
0
1
0
TDO
Identification Register
108
.
.
.
.
2
Boundary Scan Register
TCK
TAP Controller
TMS
TAP Electrical Characteristics
Over the Operating Range [13, 14, 15]
Parameter
Description
Test Conditions
Min
Max
Unit
VOH1
Output HIGH Voltage
IOH = −2.0 mA
1.4
V
VOH2
Output HIGH Voltage
IOH = −100 μA
1.6
V
VOL1
Output LOW Voltage
IOL = 2.0 mA
0.4
V
VOL2
Output LOW Voltage
IOL = 100 μA
0.2
V
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
IX
Input and Output Load Current
0.65VDD VDD + 0.3
GND ≤ VI ≤ VDD
V
–0.3
0.35VDD
V
–5
5
μA
Notes
13. These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the DC Electrical Characteristics Table.
14. Overshoot: VIH(AC) < VDDQ + 0.35V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > −0.3V (Pulse width less than tCYC/2).
15. All Voltage referenced to Ground.
Document Number: 001-53197 Rev. *B
Page 16 of 28
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CY7C11631KV18, CY7C11651KV18
TAP AC Switching Characteristics
Over the Operating Range [16, 17]
Parameter
Description
Min
Max
Unit
tTCYC
TCK Clock Cycle Time
tTF
TCK Clock Frequency
tTH
TCK Clock HIGH
20
ns
tTL
TCK Clock LOW
20
ns
tTMSS
TMS Setup to TCK Clock Rise
5
ns
tTDIS
TDI Setup to TCK Clock Rise
5
ns
tCS
Capture Setup to TCK Rise
5
ns
tTMSH
TMS Hold after TCK Clock Rise
5
ns
tTDIH
TDI Hold after Clock Rise
5
ns
tCH
Capture Hold after Clock Rise
5
ns
50
ns
20
MHz
Setup Times
Hold Times
Output Times
tTDOV
TCK Clock LOW to TDO Valid
tTDOX
TCK Clock LOW to TDO Invalid
10
0
ns
ns
TAP Timing and Test Conditions
Figure 4 shows the TAP timing and test conditions. [17]
Figure 4. TAP Timing and Test Conditions
0.9V
ALL INPUT PULSES
1.8V
50Ω
0.9V
TDO
0V
Z0 = 50Ω
(a)
CL = 20 pF
tTH
GND
tTL
Test Clock
TCK
tTCYC
tTMSH
tTMSS
Test Mode Select
TMS
tTDIS
tTDIH
Test Data In
TDI
Test Data Out
TDO
tTDOV
tTDOX
Notes
16. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.
17. Test conditions are specified using the load in TAP AC Test Conditions. tR/tF = 1 ns.
Document Number: 001-53197 Rev. *B
Page 17 of 28
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Table 7. Identification Register Definitions
Instruction Field
Value
CY7C11611KV18
CY7C11761KV18
CY7C11631KV18
CY7C11651KV18
000
000
000
000
Revision Number
(31:29)
Description
Version number.
Cypress Device ID 11010010001000100 11010010001001100 11010010001010100 11010010001100100 Defines the type of
(28:12)
SRAM.
Cypress JEDEC ID
(11:1)
00000110100
00000110100
00000110100
00000110100
1
1
1
1
ID Register
Presence (0)
Allows unique
identification of
SRAM vendor.
Indicates the
presence of an ID
register.
Table 8. Scan Register Sizes
Register Name
Bit Size
Instruction
3
Bypass
1
ID
32
Boundary Scan
109
Table 9. Instruction Codes
Instruction
Code
Description
EXTEST
000
Captures the input and output ring contents.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operation.
SAMPLE Z
010
Captures the input and output contents. Places the boundary scan register between TDI and
TDO. Forces all SRAM output drivers to a High Z state.
RESERVED
011
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
100
Captures the input and output ring contents. Places the boundary scan register between TDI
and TDO. Does not affect the SRAM operation.
RESERVED
101
Do Not Use: This instruction is reserved for future use.
RESERVED
110
Do Not Use: This instruction is reserved for future use.
BYPASS
111
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operation.
Document Number: 001-53197 Rev. *B
Page 18 of 28
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Table 10. Boundary Scan Order
Bit #
Bump ID
Bit #
Bump ID
Bit #
Bump ID
Bit #
Bump ID
0
6R
28
10G
56
6A
84
1J
1
6P
29
9G
57
5B
85
2J
2
6N
30
11F
58
5A
86
3K
3
7P
31
11G
59
4A
87
3J
4
7N
32
9F
60
5C
88
2K
5
7R
33
10F
61
4B
89
1K
6
8R
34
11E
62
3A
90
2L
7
8P
35
10E
63
2A
91
3L
8
9R
36
10D
64
1A
92
1M
9
11P
37
9E
65
2B
93
1L
10
10P
38
10C
66
3B
94
3N
11
10N
39
11D
67
1C
95
3M
12
9P
40
9C
68
1B
96
1N
13
10M
41
9D
69
3D
97
2M
14
11N
42
11B
70
3C
98
3P
15
9M
43
11C
71
1D
99
2N
16
9N
44
9B
72
2C
100
2P
17
11L
45
10B
73
3E
101
1P
18
11M
46
11A
74
2D
102
3R
19
9L
47
10A
75
2E
103
4R
20
10L
48
9A
76
1E
104
4P
21
11K
49
8B
77
2F
105
5P
22
10K
50
7C
78
3F
106
5N
23
9J
51
6C
79
1G
107
5R
108
Internal
24
9K
52
8A
80
1F
25
10J
53
7A
81
3G
26
11J
54
7B
82
2G
27
11H
55
6B
83
1H
Document Number: 001-53197 Rev. *B
Page 19 of 28
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Power Up Sequence in QDR II+ SRAM
QDR II+ SRAMs must be powered up and initialized in a
predefined manner to prevent undefined operations.
Power Up Sequence
■
Apply power and drive DOFF either HIGH or LOW (All other
inputs can be HIGH or LOW).
❐ Apply VDD before VDDQ.
❐ Apply VDDQ before VREF or at the same time as VREF.
❐ Drive DOFF HIGH.
■
Provide stable DOFF (HIGH), power and clock (K, K) for 20 μs
to lock the PLL.
PLL Constraints
■
PLL uses K clock as its synchronizing input. The input must
have low phase jitter, which is specified as tKC Var.
■
The PLL functions at frequencies down to 120 MHz.
■
If the input clock is unstable and the PLL is enabled, then the
PLL may lock onto an incorrect frequency, causing unstable
SRAM behavior. To avoid this, provide 20 μs of stable clock to
relock to the desired clock frequency.
~
~
Figure 5. Power Up Waveforms
K
K
~
~
Unstable Clock
> 20Ps Stable clock
Start Normal
Operation
Clock Start (Clock Starts after V DD / V DDQ Stable)
VDD / VDDQ
DOFF
Document Number: 001-53197 Rev. *B
V DD / V DDQ Stable (< +/- 0.1V DC per 50ns )
Fix HIGH (or tie to VDDQ)
Page 20 of 28
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Maximum Ratings
Neutron Soft Error Immunity
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Test
Parameter Description Conditions
Typ Max*
Unit
Storage Temperature ................................. –65°C to +150°C
LSBU
Logical
Single-Bit
Upsets
25°C
197
216
FIT/
Mb
LMBU
Logical
Multi-Bit
Upsets
25°C
0
0.01
FIT/
Mb
Single Event
Latch up
85°C
0
0.1
FIT/
Dev
Ambient Temperature with Power Applied.. –55°C to +125°C
Supply Voltage on VDD Relative to GND ........–0.5V to +2.9V
Supply Voltage on VDDQ Relative to GND ...... –0.5V to +VDD
DC Applied to Outputs in High Z ........ –0.5V to VDDQ + 0.3V
DC Input Voltage [14] .............................. –0.5V to VDD + 0.3V
SEL
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage (MIL-STD-883, M. 3015).. > 2001V
Latch Up Current ................................................... > 200 mA
* No LMBU or SEL events occurred during testing; this column represents a
statistical χ2, 95% confidence limit calculation. For more details refer to Application Note AN 54908 “Accelerated Neutron SER Testing and Calculation of
Terrestrial Failure Rates”
Operating Range
Range
Commercial
Industrial
Ambient
Temperature (TA)
VDD [18]
VDDQ [18]
0°C to +70°C
1.8 ± 0.1V
1.4V to
VDD
–40°C to +85°C
Electrical Characteristics
DC Electrical Characteristics
Over the Operating Range [15]
Parameter
VDD
VDDQ
VOH
VOL
VOH(LOW)
VOL(LOW)
VIH
VIL
IX
IOZ
VREF
Description
Power Supply Voltage
I/O Supply Voltage
Output HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage Current
Output Leakage Current
Input Reference Voltage [21]
Test Conditions
Note 19
Note 20
IOH = −0.1 mA, Nominal Impedance
IOL = 0.1 mA, Nominal Impedance
GND ≤ VI ≤ VDDQ
GND ≤ VI ≤ VDDQ, Output Disabled
Typical Value = 0.75V
Min
Typ
Max
Unit
1.7
1.8
1.9
V
1.4
1.5
VDD
V
VDDQ/2 – 0.12
VDDQ/2 + 0.12 V
VDDQ/2 – 0.12
VDDQ/2 + 0.12 V
VDDQ – 0.2
VDDQ
V
VSS
0.2
V
VREF + 0.1
VDDQ + 0.15
V
–0.15
VREF – 0.1
V
−2
2
μA
−2
2
μA
0.68
0.75
0.95
V
Notes
18. Power up: Assumes a linear ramp from 0V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
19. Output are impedance controlled. IOH = −(VDDQ/2)/(RQ/5) for values of 175 ohms
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