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CY7C1263XV18
CY7C1265XV18
36-Mbit QDR® II+ Xtreme SRAM Four-Word
Burst Architecture (2.5 Cycle Read Latency)
36-Mbit QDR® II+ Xtreme SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency)
Features
Configurations
Separate Independent Read and Write Data Ports
❐ Supports concurrent transactions
With Read Cycle Latency of 2.5 cycles:
■
633 MHz Clock for High Bandwidth
CY7C1265XV18 – 1 M × 36
■
Four-word Burst for Reducing Address Bus Frequency
Functional Description
■
Double Data Rate (DDR) Interfaces on both Read and Write
Ports (data transferred at 1266 MHz) at 633 MHz
■
Available in 2.5 Clock Cycle Latency
■
Two Input Clocks (K and K) for precise DDR Timing
❐ SRAM uses rising edges only
■
Echo Clocks (CQ and CQ) simplify Data Capture in High Speed
Systems
■
Data Valid Pin (QVLD) to indicate Valid Data on the Output
■
Single Multiplexed Address Input Bus latches Address Inputs
for Read and Write Ports
■
Separate Port selects for Depth Expansion
■
Synchronous Internally Self-timed Writes
■
QDR® II+ Xtreme operates with 2.5 cycle read latency when
DOFF is asserted HIGH
■
CY7C1263XV18 – 2 M × 18
The CY7C1263XV18, and CY7C1265XV18 are 1.8 V
Synchronous Pipelined SRAMs, equipped with QDR II+
architecture. Similar to QDR II architecture, QDR II+ architecture
consists of two separate ports: the read port and the write port to
access the memory array. The read port has dedicated data
outputs to support read operations and the write port has
dedicated data inputs to support write operations. QDR II+
architecture has separate data inputs and data outputs to
completely eliminate the need to “turnaround” the data bus that
exists with common I/O devices. Each port is accessed through
a common address bus. Addresses for read and write addresses
are latched on alternate rising edges of the input (K) clock.
Accesses to the QDR II+ Xtreme read and write ports are
completely independent of one another. To maximize data
throughput, both read and write ports are equipped with DDR
interfaces. Each address location is associated with four 18-bit
words (CY7C1263XV18), or 36-bit words (CY7C1265XV18) that
burst sequentially into or out of the device. Because data is
transferred into and out of the device on every rising edge of both
input clocks (K and K), memory bandwidth is maximized while
simplifying system design by eliminating bus “turnarounds”.
■
Operates similar to QDR I Device with one Cycle Read Latency
when DOFF is asserted LOW
■
Available in × 18 and × 36 Configurations
■
Full Data Coherency, providing Most Current Data
■
Core VDD = 1.8 V ± 0.1 V; I/O VDDQ = 1.4 V to 1.6 V
❐ Supports 1.5 V I/O supply
■
HSTL Inputs and Variable Drive HSTL Output Buffers
■
Available in 165-ball FBGA Package (13 × 15 × 1.4 mm)
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the K or K input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
■
Offered in Pb-free Packages
For a complete list of related documentation, click here.
■
JTAG 1149.1 compatible Test Access Port
■
Phase-Locked Loop (PLL) for Accurate Data Placement
Depth expansion is accomplished with port selects, which
enables each port to operate independently.
Selection Guide
Description
633 MHz
Maximum Operating Frequency
Maximum Operating Current
Cypress Semiconductor Corporation
Document Number: 001-70328 Rev. *F
•
198 Champion Court
•
600 MHz
Unit
633
600
MHz
× 18
1165
1100
mA
× 36
1660
1570
San Jose, CA 95134-1709
•
408-943-2600
Revised January 3, 2018
CY7C1263XV18
CY7C1265XV18
Logic Block Diagram – CY7C1263XV18
DOFF
Write
Reg
Address
Register
Read Add. Decode
512K x 18 Array
K
CLK
Gen.
Write
Reg
512K x 18 Array
K
Write
Reg
512K x 18 Array
Address
Register
Write
Reg
512K x 18 Array
A(18:0)
19
18
Write Add. Decode
D[17:0]
Control
Logic
19
A(18:0)
RPS
Read Data Reg.
CQ
72
VREF
WPS
BWS[1:0]
36
Control
Logic
Reg.
36
Reg.
CQ
Reg. 18
18
18
18
18
Q[17:0]
QVLD
Logic Block Diagram – CY7C1265XV18
DOFF
Address
Register
Read Add. Decode
Write
Reg
256K x 36 Array
K
CLK
Gen.
Write
Reg
256K x 36 Array
K
Write
Reg
256K x 36 Array
Address
Register
Write
Reg
256K x 36 Array
A(17:0)
18
36
Write Add. Decode
D[35:0]
Control
Logic
18
A(17:0)
RPS
Read Data Reg.
CQ
144
VREF
WPS
BWS[3:0]
72
Control
Logic
72
Reg.
Reg.
Reg. 36
36
36
36
CQ
36
Q[35:0]
QVLD
Document Number: 001-70328 Rev. *F
Page 2 of 30
CY7C1263XV18
CY7C1265XV18
Contents
Pin Configurations ........................................................... 4
Pin Definitions .................................................................. 5
Functional Overview ........................................................ 6
Read Operations ......................................................... 6
Write Operations ......................................................... 6
Byte Write Operations ................................................. 7
Concurrent Transactions ............................................. 7
Depth Expansion ......................................................... 7
Programmable Impedance .......................................... 7
Echo Clocks ................................................................ 7
Valid Data Indicator (QVLD) ........................................ 7
PLL .............................................................................. 7
Application Example ........................................................ 8
Truth Table ........................................................................ 9
Write Cycle Descriptions ............................................... 10
Write Cycle Descriptions ............................................... 11
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 12
Disabling the JTAG Feature ...................................... 12
Test Access Port ....................................................... 12
Performing a TAP Reset ........................................... 12
TAP Registers ........................................................... 12
TAP Instruction Set ................................................... 12
TAP Controller State Diagram ....................................... 14
TAP Controller Block Diagram ...................................... 15
TAP Electrical Characteristics ...................................... 15
TAP AC Switching Characteristics ............................... 16
TAP Timing and Test Conditions .................................. 17
Identification Register Definitions ................................ 18
Scan Register Sizes ....................................................... 18
Instruction Codes ........................................................... 18
Document Number: 001-70328 Rev. *F
Boundary Scan Order .................................................... 19
Power Up Sequence in QDR II+ Xtreme SRAM ............ 20
Power Up Sequence ................................................. 20
PLL Constraints ......................................................... 20
Maximum Ratings ........................................................... 21
Neutron Soft Error Immunity ......................................... 21
Operating Range ............................................................. 21
Electrical Characteristics ............................................... 21
DC Electrical Characteristics ..................................... 21
AC Electrical Characteristics ..................................... 22
Capacitance .................................................................... 22
Thermal Resistance ........................................................ 22
AC Test Loads and Waveforms ..................................... 23
Switching Characteristics .............................................. 24
Switching Waveforms .................................................... 25
Read/Write/Deselect Sequence ................................ 25
Ordering Information ...................................................... 26
Ordering Code Definitions ......................................... 26
Package Diagram ............................................................ 27
Acronyms ........................................................................ 28
Document Conventions ................................................. 28
Units of Measures ..................................................... 28
Document History Page ................................................. 29
Sales, Solutions, and Legal Information ...................... 30
Worldwide Sales and Design Support ....................... 30
Products .................................................................... 30
PSoC® Solutions ...................................................... 30
Cypress Developer Community ................................. 30
Technical Support ..................................................... 30
Page 3 of 30
CY7C1263XV18
CY7C1265XV18
Pin Configurations
The pin configurations for CY7C1263XV18, and CY7C1265XV18 follow. [1]
Figure 1. 165-ball FBGA (13 × 15 × 1.4 mm) pinout
CY7C1263XV18 (2 M × 18)
1
2
3
4
5
6
7
8
9
10
11
A
CQ
NC/144M
A
WPS
BWS1
K
NC/288M
RPS
A
NC/72M
CQ
B
NC
Q9
D9
A
NC
K
BWS0
A
NC
NC
Q8
C
NC
NC
D10
VSS
A
NC
A
VSS
NC
Q7
D8
D
NC
D11
Q10
VSS
VSS
VSS
VSS
VSS
NC
NC
D7
E
NC
NC
Q11
VDDQ
VSS
VSS
VSS
VDDQ
NC
D6
Q6
F
NC
Q12
D12
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
Q5
G
NC
D13
Q13
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
D5
H
DOFF
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
NC
NC
D14
VDDQ
VDD
VSS
VDD
VDDQ
NC
Q4
D4
K
NC
NC
Q14
VDDQ
VDD
VSS
VDD
VDDQ
NC
D3
Q3
L
NC
Q15
D15
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
Q2
M
NC
NC
D16
VSS
VSS
VSS
VSS
VSS
NC
Q1
D2
N
NC
D17
Q16
VSS
A
A
A
VSS
NC
NC
D1
P
NC
NC
Q17
A
A
QVLD
A
A
NC
D0
Q0
R
TDO
TCK
A
A
A
NC
A
A
A
TMS
TDI
CY7C1265XV18 (1 M × 36)
1
2
3
NC/288M NC/72M
4
5
6
7
8
9
10
11
WPS
BWS2
K
BWS1
RPS
A
NC/144M
CQ
A
CQ
B
Q27
Q18
D18
A
BWS3
K
BWS0
A
D17
Q17
Q8
C
D27
Q28
D19
VSS
A
NC
A
VSS
D16
Q7
D8
D
D28
D20
Q19
VSS
VSS
VSS
VSS
VSS
Q16
D15
D7
E
Q29
D29
Q20
VDDQ
VSS
VSS
VSS
VDDQ
Q15
D6
Q6
F
Q30
Q21
D21
VDDQ
VDD
VSS
VDD
VDDQ
D14
Q14
Q5
G
D30
D22
Q22
VDDQ
VDD
VSS
VDD
VDDQ
Q13
D13
D5
H
DOFF
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
D31
Q31
D23
VDDQ
VDD
VSS
VDD
VDDQ
D12
Q4
D4
K
Q32
D32
Q23
VDDQ
VDD
VSS
VDD
VDDQ
Q12
D3
Q3
L
Q33
Q24
D24
VDDQ
VSS
VSS
VSS
VDDQ
D11
Q11
Q2
M
D33
Q34
D25
VSS
VSS
VSS
VSS
VSS
D10
Q1
D2
N
D34
D26
Q25
VSS
A
A
A
VSS
Q10
D9
D1
P
Q35
D35
Q26
A
A
QVLD
A
A
Q9
D0
Q0
R
TDO
TCK
A
A
A
NC
A
A
A
TMS
TDI
Note
1. NC/72M, NC/144M and NC/288M are not connected to the die and can be tied to any voltage level.
Document Number: 001-70328 Rev. *F
Page 4 of 30
CY7C1263XV18
CY7C1265XV18
Pin Definitions
Pin Name
I/O
Pin Description
D[x:0]
InputData Input Signals. Sampled on the rising edge of K and K clocks when valid write operations are active.
Synchronous CY7C1263XV18 D[17:0]
CY7C1265XV18 D[35:0]
WPS
InputWrite Port Select Active LOW. Sampled on the rising edge of the K clock. When asserted active, a
Synchronous write operation is initiated. Deasserting deselects the write port. Deselecting the write port ignores D[x:0].
BWS0,
BWS1,
BWS2,
BWS3
InputByte Write Select 0, 1, 2 and 3 Active LOW. Sampled on the rising edge of the K and K clocks when
Synchronous write operations are active. Used to select which byte is written into the device during the current portion
of the write operations. Bytes not written remain unaltered.
CY7C1263XV18 BWS0 controls D[8:0] and BWS1 controls D[17:9].
CY7C1265XV18 BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18] and BWS3 controls
D[35:27].
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select
ignores the corresponding byte of data and it is not written into the device.
A
InputAddress Inputs. Sampled on the rising edge of the K clock during active read and write operations. These
Synchronous address inputs are multiplexed for both read and write operations. Internally, the device is organized as
2 M × 18 (4 arrays each of 512 K × 18) for CY7C1263XV18 and 1 M × 36 (4 arrays each of 256 K × 36)
for CY7C1265XV18. Therefore, only 19 address inputs are needed to access the entire memory array for
CY7C1263XV18 and 18 address inputs for CY7C1265XV18. These inputs are ignored when the
appropriate port is deselected. The address pins (A) can be assigned any bit order.
Q[x:0]
OutputsData Output Signals. These pins drive out the requested data when the read operation is active. Valid
Synchronous data is driven out on the rising edge of the K and K clocks during read operations. On deselecting the
read port, Q[x:0] are automatically tristated.
CY7C1263XV18 Q[17:0]
CY7C1265XV18 Q[35:0]
RPS
InputRead Port Select Active LOW. Sampled on the rising edge of positive input clock (K). When active, a
Synchronous read operation is initiated. Deasserting deselects the read port. When deselected, the pending access is
allowed to complete and the output drivers are automatically tristated following the next rising edge of the
K clock. Each read access consists of a burst of four sequential transfers.
QVLD
Valid output Valid Output Indicator. The Q Valid indicates valid output data. QVLD is edge aligned with CQ and CQ.
indicator
K
Input Clock
Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device
and to drive out data through Q[x:0]. All accesses are initiated on the rising edge of K.
K
Input Clock
Negative Input Clock Input. K is used to capture synchronous inputs being presented to the device and
to drive out data through Q[x:0].
CQ
Echo Clock
Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input clock
(K) of the QDR II+ Xtreme. The timings for the echo clocks are shown in the Switching Characteristics on
page 24.
CQ
Echo Clock
Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input clock
(K) of the QDR II+ Xtreme.The timings for the echo clocks are shown in the Switching Characteristics on
page 24.
ZQ
Input
Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus
impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 × RQ, where RQ is a resistor connected
between ZQ and ground. Alternatively, this pin can be connected directly to VDDQ, which enables the
minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.
DOFF
Input
PLL Turn Off Active LOW. Connecting this pin to ground turns off the PLL inside the device. The timings
in the PLL turned off operation differs from those listed in this data sheet. For normal operation, this pin
can be connected to a pull up through a 10 K or less pull up resistor. The device behaves in QDR I mode
when the PLL is turned off. In this mode, the device can be operated at a frequency of up to 167 MHz
with QDR I timing.
Document Number: 001-70328 Rev. *F
Page 5 of 30
CY7C1263XV18
CY7C1265XV18
Pin Definitions (continued)
Pin Name
I/O
Pin Description
TDO
Output
TDO Pin for JTAG
TCK
Input
TCK Pin for JTAG
TDI
Input
TDI Pin for JTAG
TMS
Input
TMS Pin for JTAG
NC
N/A
Not Connected to the Die. Can be tied to any voltage level.
NC/72M
N/A
Not Connected to the Die. Can be tied to any voltage level.
NC/144M
N/A
Not Connected to the Die. Can be tied to any voltage level.
NC/288M
N/A
Not Connected to the Die. Can be tied to any voltage level.
VREF
VDD
VSS
VDDQ
InputReference
Reference Voltage Input. Static input used to set the reference level for HSTL inputs, outputs, and AC
measurement points.
Power Supply Power Supply Inputs to the Core of the Device
Ground
Ground for the Device
Power Supply Power Supply Inputs for the Outputs of the Device
Functional Overview
The CY7C1263XV18 and CY7C1265XV18 are synchronous
pipelined Burst SRAMs equipped with a read port and a write
port. The read port is dedicated to read operations and the write
port is dedicated to write operations. Data flows into the SRAM
through the write port and flows out through the read port. These
devices multiplex the address inputs to minimize the number of
address pins required. By having separate read and write ports,
the QDR II+ Xtreme completely eliminates the need to
“turnaround” the data bus and avoids any possible data
contention, thereby simplifying system design. Each access
consists of four 18-bit data transfers in the case of
CY7C1263XV18, and four 36-bit data transfers in the case of
CY7C1265XV18, in two clock cycles.
These devices operate with a read latency of two and half cycles
when DOFF pin is tied HIGH. When DOFF pin is set LOW or
connected to VSS then device behaves in QDR I mode with a
read latency of one clock cycle.
Accesses for both ports are initiated on the positive input clock
(K). All synchronous input and output timing are referenced from
the rising edge of the input clocks (K and K).
All synchronous data inputs (D[x:0]) pass through input registers
controlled by the input clocks (K and K). All synchronous data
outputs (Q[x:0]) outputs pass through output registers controlled
by the rising edge of the input clocks (K and K) as well.
All synchronous control (RPS, WPS, BWS[x:0]) inputs pass
through input registers controlled by the rising edge of the input
clocks (K and K).
CY7C1263XV18 is described in the following sections. The
same basic descriptions apply to CY7C1265XV18.
Read Operations
The CY7C1263XV18 is organized internally as four arrays of
512 K × 18. Accesses are completed in a burst of four sequential
18-bit data words. Read operations are initiated by asserting
Document Number: 001-70328 Rev. *F
RPS active at the rising edge of the positive input clock (K). The
address presented to the address inputs is stored in the read
address register. Following the next two K clock rise, the
corresponding lowest order 18-bit word of data is driven onto the
Q[17:0] using K as the output timing reference. On the
subsequent rising edge of K, the next 18-bit data word is driven
onto the Q[17:0]. This process continues until all four 18-bit data
words have been driven out onto Q[17:0]. The requested data is
valid 0.45 ns from the rising edge of the input clock (K or K). To
maintain the internal logic, each read access must be allowed to
complete. Each read access consists of four 18-bit data words
and takes two clock cycles to complete. Therefore, read
accesses to the device can not be initiated on two consecutive
K clock rises. The internal logic of the device ignores the second
read request. Read accesses can be initiated on every other K
clock rise. Doing so pipelines the data flow such that data is
transferred out of the device on every rising edge of the input
clocks (K and K).
When the read port is deselected, the CY7C1263XV18 first
completes the pending read transactions. Synchronous internal
circuitry automatically tristates the outputs following the next
rising edge of the negative input clock (K). This enables for a
seamless transition between devices without the insertion of wait
states in a depth expanded memory.
Write Operations
Write operations are initiated by asserting WPS active at the
rising edge of the positive input clock (K). On the following K
clock rise the data presented to D[17:0] is latched and stored into
the lower 18-bit write data register, provided BWS[1:0] are both
asserted active. On the subsequent rising edge of the negative
input clock (K) the information presented to D[17:0] is also stored
into the write data register, provided BWS[1:0] are both asserted
active. This process continues for one more cycle until four 18-bit
words (a total of 72 bits) of data are stored in the SRAM. The
72 bits of data are then written into the memory array at the
specified location. Therefore, write accesses to the device can
not be initiated on two consecutive K clock rises. The internal
Page 6 of 30
CY7C1263XV18
CY7C1265XV18
logic of the device ignores the second write request. Write
accesses can be initiated on every other rising edge of the
positive input clock (K). Doing so pipelines the data flow such
that 18 bits of data can be transferred into the device on every
rising edge of the input clocks (K and K).
When deselected, the write port ignores all inputs after the
pending write operations have been completed.
Byte Write Operations
Byte write operations are supported by the CY7C1263XV18. A
write operation is initiated as described in the Write Operations
on page 6. The bytes that are written are determined by BWS0
and BWS1, which are sampled with each set of 18-bit data
words. Asserting the appropriate Byte Write Select input during
the data portion of a write latches the data being presented and
writes it into the device. Deasserting the Byte Write Select input
during the data portion of a write enables the data stored in the
device for that byte to remain unaltered. This feature can be used
to simplify read, modify, or write operations to a byte write
operation.
Concurrent Transactions
The read and write ports on the CY7C1263XV18 operates
completely independently of one another. As each port latches
the address inputs on different clock edges, the user can read or
write to any location, regardless of the transaction on the other
port. If the ports access the same location when a read follows a
write in successive clock cycles, the SRAM delivers the most
recent information associated with the specified address
location. This includes forwarding data from a write cycle that
was initiated on the previous K clock rise.
Read access and write access must be scheduled such that one
transaction is initiated on any clock cycle. If both ports are
selected on the same K clock rise, the arbitration depends on the
previous state of the SRAM. If both ports are deselected, the
read port takes priority. If a read was initiated on the previous
cycle, the write port takes priority (as read operations cannot be
initiated on consecutive cycles). If a write was initiated on the
previous cycle, the read port takes priority (as write operations
can not be initiated on consecutive cycles). Therefore, asserting
both port selects active from a deselected state results in
alternating read or write operations being initiated, with the first
access being a read.
does not affect the other port. All pending transactions (read and
write) are completed before the device is deselected.
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin
on the SRAM and VSS to allow the SRAM to adjust its output
driver impedance. The value of RQ must be 5 × the value of the
intended line impedance driven by the SRAM, the allowable
range of RQ to guarantee impedance matching with a tolerance
of ±15% is between 175 and 350 , with VDDQ = 1.5 V. The
output impedance is adjusted every 1024 cycles upon power up
to account for drifts in supply voltage and temperature.
Echo Clocks
Echo clocks are provided on the QDR II+ Xtreme to simplify data
capture on high-speed systems. Two echo clocks are generated
by the QDR II+ Xtreme. CQ is referenced with respect to K and
CQ is referenced with respect to K. These are free running clocks
and are synchronized to the input clock of the QDR II+ Xtreme.
The timing for the echo clocks is shown in the Switching
Characteristics on page 24.
Valid Data Indicator (QVLD)
QVLD is provided on the QDR II+ Xtreme to simplify data capture
on high speed systems. The QVLD is generated by the QDR II+
Xtreme device along with data output. This signal is also
edge-aligned with the echo clock and follows the timing of any
data pin. This signal is asserted half a cycle before valid data
arrives.
PLL
These chips use a PLL that is designed to function between
120 MHz and the specified maximum clock frequency. During
power up, when the DOFF is tied HIGH, the PLL is locked after
100 s of stable clock. The PLL can also be reset by slowing or
stopping the input clocks K and K for a minimum of 30 ns.
However, it is not necessary to reset the PLL to lock to the
desired frequency. The PLL automatically locks 100 s after a
stable clock is presented. The PLL may be disabled by applying
ground to the DOFF pin. When the PLL is turned off, the device
behaves in QDR I mode (with one cycle latency and a longer
access time). For information, refer to the application note, PLL
Considerations in QDRII/DDRII/QDRII+/DDRII+.
Depth Expansion
The CY7C1263XV18 has a port select input for each port. This
enables for easy depth expansion. Both port selects are sampled
on the rising edge of the positive input clock only (K). Each port
select input can deselect the specified port. Deselecting a port
Document Number: 001-70328 Rev. *F
Page 7 of 30
CY7C1263XV18
CY7C1265XV18
Application Example
Figure 2 shows two QDR II+ Xtreme used in an application.
Figure 2. Application Example (Width Expansion)
SRAM#1
D[x:0]
A
RPS
WPS
ZQ
CQ/CQ
Q[x:0]
BWS K K
RQ
SRAM#2
D[x:0]
A
RPS
WPS
ZQ
CQ/CQ
Q[x:0]
BWS K K
RQ
DATA IN[2x:0]
DATA OUT [2x:0]
ADDRESS
RPS
WPS
BWS
CLKIN1/CLKIN1
CLKIN2/CLKIN2
SOURCE K
SOURCE K
FPGA / ASIC
Document Number: 001-70328 Rev. *F
Page 8 of 30
CY7C1263XV18
CY7C1265XV18
Truth Table
The truth table for CY7C1263XV18, and CY7C1265XV18 follows. [2, 3, 4, 5, 6, 7]
Operation
K
RPS WPS
[8]
DQ
DQ
DQ
DQ
Write Cycle:
Load address on the rising
edge of K; input write data
on two consecutive K and
K rising edges.
L–H
H
Read Cycle:
(2.5 cycle Latency)
Load address on the rising
edge of K; wait two and half
cycles; read data on two
consecutive K and K rising
edges.
L–H
L [9]
X
Q(A) at K(t + 2) Q(A + 1) at K(t + 3) Q(A + 2) at K(t + 3) Q(A + 3) at K(t + 4)
NOP: No Operation
L–H
H
H
D=X
Q = High Z
D=X
Q = High Z
D=X
Q = High Z
D=X
Q = High Z
Stopped
X
X
Previous State
Previous State
Previous State
Previous State
Standby: Clock Stopped
L
[9]
D(A) at K(t + 1) D(A + 1) at K(t + 1) D(A + 2) at K(t + 2) D(A + 3) at K(t + 2)
Notes
2. X = “Don't Care,” H = Logic HIGH, L = Logic LOW, represents rising edge.
3. Device powers up deselected with the outputs in a tristate condition.
4. “A” represents address location latched by the devices when transaction was initiated. A + 1, A + 2, and A + 3 represents the address sequence in the burst.
5. “t” represents the cycle at which a read/write operation is started. t + 1, t + 2, and t + 3 are the first, second and third clock cycles respectively succeeding the “t” clock
cycle.
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on K and K rising edges as well.
7. It is recommended that K = K = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically.
8. If this signal was LOW to initiate the previous cycle, this signal becomes a “Don’t Care” for this operation.
9. This signal was HIGH on previous K clock rise. Initiating consecutive read or write operations on consecutive K clock rises is not permitted. The device ignores the
second read or write request.
Document Number: 001-70328 Rev. *F
Page 9 of 30
CY7C1263XV18
CY7C1265XV18
Write Cycle Descriptions
The write cycle description table for CY7C1263XV18 follows. [10, 11]
BWS0
BWS1
K
K
L
L
L–H
–
L
L
–
L
H
L–H
L
H
–
H
L
L–H
H
L
–
H
H
L–H
H
H
–
Comments
During the data portion of a write sequence
CY7C1263XV18 both bytes (D[17:0]) are written into the device.
L–H During the data portion of a write sequence:
CY7C1263XV18 both bytes (D[17:0]) are written into the device.
–
During the data portion of a write sequence:
CY7C1263XV18 only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered.
L–H During the data portion of a write sequence
CY7C1263XV18 only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered.
–
During the data portion of a write sequence
CY7C1263XV18 only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.
L–H During the data portion of a write sequence
CY7C1263XV18 only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.
–
No data is written into the devices during this portion of a write operation.
L–H No data is written into the devices during this portion of a write operation.
Notes
10. X = “Don't Care,” H = Logic HIGH, L = Logic LOW, represents rising edge.
11. Is based on a write cycle that was initiated in accordance with above Truth Table on page 9. BWS0, BWS1,BWS2, BWS3 can be altered on different portions of a write
cycle, as long as the setup and hold requirements are achieved.
Document Number: 001-70328 Rev. *F
Page 10 of 30
CY7C1263XV18
CY7C1265XV18
Write Cycle Descriptions
The write cycle description table for CY7C1265XV18 follows. [12, 13]
BWS0
BWS1
BWS2
BWS3
K
K
Comments
L
L
L
L
L–H
–
During the data portion of a write sequence, all four bytes (D[35:0]) are written into
the device.
L
L
L
L
–
L
H
H
H
L–H
L
H
H
H
–
H
L
H
H
L–H
H
L
H
H
–
H
H
L
H
L–H
H
H
L
H
–
H
H
H
L
L–H
H
H
H
L
–
H
H
H
H
L–H
H
H
H
H
–
L–H During the data portion of a write sequence, all four bytes (D[35:0]) are written into
the device.
–
During the data portion of a write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] remains unaltered.
L–H During the data portion of a write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] remains unaltered.
–
During the data portion of a write sequence, only the byte (D[17:9]) is written into the
device. D[8:0] and D[35:18] remains unaltered.
L–H During the data portion of a write sequence, only the byte (D[17:9]) is written into the
device. D[8:0] and D[35:18] remains unaltered.
–
During the data portion of a write sequence, only the byte (D[26:18]) is written into
the device. D[17:0] and D[35:27] remains unaltered.
L–H During the data portion of a write sequence, only the byte (D[26:18]) is written into
the device. D[17:0] and D[35:27] remains unaltered.
–
During the data portion of a write sequence, only the byte (D[35:27]) is written into
the device. D[26:0] remains unaltered.
L–H During the data portion of a write sequence, only the byte (D[35:27]) is written into
the device. D[26:0] remains unaltered.
–
No data is written into the device during this portion of a write operation.
L–H No data is written into the device during this portion of a write operation.
Notes
12. X = “Don't Care,” H = Logic HIGH, L = Logic LOW, represents rising edge.
13. Is based on a write cycle that was initiated in accordance with above Truth Table on page 9. BWS0, BWS1,BWS2, BWS3 can be altered on different portions of a write
cycle, as long as the setup and hold requirements are achieved.
Document Number: 001-70328 Rev. *F
Page 11 of 30
CY7C1263XV18
CY7C1265XV18
IEEE 1149.1 Serial Boundary Scan (JTAG)
These SRAMs incorporate a serial boundary scan Test Access
Port (TAP) in the FBGA package. This part is fully compliant with
IEEE Standard #1149.1-2001. The TAP operates using JEDEC
standard 1.8 V I/O logic levels.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are
internally pulled up and may be unconnected. They may
alternatively be connected to VDD through a pull up resistor. TDO
must be left unconnected. Upon power up, the device comes up
in a reset state, which does not interfere with the operation of the
device.
Test Access Port
Test Clock
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. This pin may be left
unconnected if the TAP is not used. The pin is pulled up
internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI pin is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. For information on
loading the instruction register, see TAP Controller State
Diagram on page 14. TDI is internally pulled up and can be
unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) on any register.
Test Data-Out (TDO)
The TDO output pin is used to serially clock data out from the
registers. The output is active, depending upon the current state
of the TAP state machine (see Instruction Codes on page 18).
The output changes on the falling edge of TCK. TDO is
connected to the least significant bit (LSB) of any register.
Performing a TAP Reset
A Reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This Reset does not affect the operation of the
SRAM and can be performed while the SRAM is operating. At
power up, the TAP is reset internally to ensure that TDO comes
up in a High Z state.
TAP Registers
Registers are connected between the TDI and TDO pins to scan
the data in and out of the SRAM test circuitry. Only one register
can be selected at a time through the instruction registers. Data
is serially loaded into the TDI pin on the rising edge of TCK. Data
is output on the TDO pin on the falling edge of TCK.
Document Number: 001-70328 Rev. *F
Instruction Register
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO pins, as shown in TAP Controller Block Diagram on
page 15. Upon power up, the instruction register is loaded with
the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state, as described
in the previous section.
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary “01” pattern to allow for
fault isolation of the board level serial test path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This enables shifting of data through the SRAM
with minimal delay. The bypass register is set LOW (VSS) when
the BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all of the input and
output pins on the SRAM. Several No Connect (NC) pins are also
included in the scan register to reserve pins for higher density
devices.
The boundary scan register is loaded with the contents of the
RAM input and output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and TDO
pins when the controller is moved to the Shift-DR state. The
EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions can
be used to capture the contents of the input and output ring.
The section Boundary Scan Order on page 19 shows the order
in which the bits are connected. Each bit corresponds to one of
the bumps on the SRAM package. The MSB of the register is
connected to TDI, and the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in Identification Register Definitions on
page 18.
TAP Instruction Set
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in Instruction
Codes on page 18. Three of these instructions are listed as
RESERVED and must not be used. The other five instructions
are described in this section in detail.
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO pins. To execute
the instruction after it is shifted in, the TAP controller must be
moved into the Update-IR state.
Page 12 of 30
CY7C1263XV18
CY7C1265XV18
IDCODE
The IDCODE instruction loads a vendor-specific, 32-bit code into
the instruction register. It also places the instruction register
between the TDI and TDO pins and shifts the IDCODE out of the
device when the TAP controller enters the Shift-DR state. The
IDCODE instruction is loaded into the instruction register at
power up or whenever the TAP controller is supplied a
Test-Logic-Reset state.
SAMPLE Z
The SAMPLE Z instruction connects the boundary scan register
between the TDI and TDO pins when the TAP controller is in a
Shift-DR state. The SAMPLE Z command puts the output bus
into a High Z state until the next command is supplied during the
Update IR state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the input and output pins is captured
in the boundary scan register.
The TAP controller clock can only operate at a frequency up to
20 MHz, while the SRAM clock operates more than an order of
magnitude faster. Because there is a large difference in the clock
frequencies, it is possible that during the Capture-DR state, an
input or output undergoes a transition. The TAP may then try to
capture a signal while in transition (metastable state). This does
not harm the device, but there is no guarantee as to the value
that is captured. Repeatable results may not be possible.
To guarantee that the boundary scan register captures the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture setup plus hold
times (tCS and tCH). The SRAM clock input might not be captured
correctly if there is no way in a design to stop (or slow) the clock
during a SAMPLE/PRELOAD instruction. If this is an issue, it is
still possible to capture all other signals and simply ignore the
value of the CK and CK captured in the boundary scan register.
After the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.
Document Number: 001-70328 Rev. *F
PRELOAD places an initial data pattern at the latched parallel
outputs of the boundary scan register cells before the selection
of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required, that is, while the data
captured is shifted out, the preloaded data can be shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO pins. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
EXTEST
The EXTEST instruction drives the preloaded data out through
the system output pins. This instruction also connects the
boundary scan register for serial access between the TDI and
TDO in the Shift-DR controller state.
EXTEST OUTPUT BUS TRISTATE
IEEE Standard 1149.1 mandates that the TAP controller be able
to put the output bus into a tristate mode.
The boundary scan register has a special bit located at bit #108.
When this scan cell, called the “extest output bus tristate,” is
latched into the preload register during the Update-DR state in
the TAP controller, it directly controls the state of the output
(Q-bus) pins, when the EXTEST is entered as the current
instruction. When HIGH, it enables the output buffers to drive the
output bus. When LOW, this bit places the output bus into a
High Z condition.
This bit can be set by entering the SAMPLE/PRELOAD or
EXTEST command, and then shifting the desired bit into that cell,
during the Shift-DR state. During Update-DR, the value loaded
into that shift-register cell latches into the preload register. When
the EXTEST instruction is entered, this bit directly controls the
output Q-bus pins. Note that this bit is preset HIGH to enable the
output when the device is powered up, and also when the TAP
controller is in the Test-Logic-Reset state.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Page 13 of 30
CY7C1263XV18
CY7C1265XV18
TAP Controller State Diagram
The state diagram for the TAP controller follows. [14]
1
TEST-LOGIC
RESET
0
0
TEST-LOGIC/
IDLE
1
SELECT
DR-SCAN
1
1
SELECT
IR-SCAN
0
0
1
1
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
0
SHIFT-IR
1
1
EXIT1-DR
1
EXIT1-IR
0
0
PAUSE-IR
1
0
1
EXIT2-DR
0
EXIT2-IR
1
1
UPDATE-IR
UPDATE-DR
1
1
0
PAUSE-DR
0
0
0
1
0
Note
14. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
Document Number: 001-70328 Rev. *F
Page 14 of 30
CY7C1263XV18
CY7C1265XV18
TAP Controller Block Diagram
0
Bypass Register
2
Selection
Circuitry
TDI
1
0
Selection
Circuitry
Instruction Register
31
30
29
.
.
2
1
0
1
0
TDO
Identification Register
108
.
.
.
.
2
Boundary Scan Register
TCK
TAP Controller
TMS
TAP Electrical Characteristics
Over the Operating Range
Parameter [15, 16, 17]
Description
VOH1
Output HIGH Voltage
Test Conditions
Min
Max
Unit
IOH =2.0 mA
1.4
–
V
VOH2
Output HIGH Voltage
IOH =100 A
1.6
–
V
VOL1
Output LOW Voltage
IOL = 2.0 mA
–
0.4
V
VOL2
Output LOW Voltage
IOL = 100 A
–
0.2
V
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
IX
Input and Output Load Current
0.65 × VDD VDD + 0.3
GND VI VDD
V
–0.3
0.35 × VDD
V
–5
5
A
Notes
15. These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics on page 21.
16. Overshoot: VIH(AC) < VDD + 0.35 V (Pulse width less than tTCYC/2), Undershoot: VIL(AC) > 0.3 V (Pulse width less than tTCYC/2).
17. All Voltage referenced to Ground.
Document Number: 001-70328 Rev. *F
Page 15 of 30
CY7C1263XV18
CY7C1265XV18
TAP AC Switching Characteristics
Over the Operating Range
Parameter [18, 19]
Description
Min
Max
Unit
50
–
ns
tTCYC
TCK Clock Cycle Time
tTF
TCK Clock Frequency
–
20
MHz
tTH
TCK Clock HIGH
20
–
ns
tTL
TCK Clock LOW
20
–
ns
tTMSS
TMS Setup to TCK Clock Rise
5
–
ns
tTDIS
TDI Setup to TCK Clock Rise
5
–
ns
tCS
Capture Setup to TCK Rise
5
–
ns
tTMSH
TMS Hold after TCK Clock Rise
5
–
ns
tTDIH
TDI Hold after Clock Rise
5
–
ns
tCH
Capture Hold after Clock Rise
5
–
ns
tTDOV
TCK Clock LOW to TDO Valid
–
10
ns
tTDOX
TCK Clock LOW to TDO Invalid
0
–
ns
Setup Times
Hold Times
Output Times
Notes
18. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.
19. Test conditions are specified using the load in TAP AC Test Conditions. tR/tF = 1 V/ns.
Document Number: 001-70328 Rev. *F
Page 16 of 30
CY7C1263XV18
CY7C1265XV18
TAP Timing and Test Conditions
Figure 3 shows the TAP timing and test conditions. [20]
Figure 3. TAP Timing and Test Conditions
0.9 V
ALL INPUT PULSES
1.8 V
50
0.9 V
TDO
0V
Z0 = 50
(a)
Slew Rate = 1 V/ns
CL = 20 pF
tTH
GND
tTL
Test Clock
TCK
tTMSH
tTMSS
tTCYC
Test Mode Select
TMS
tTDIS
tTDIH
Test Data In
TDI
Test Data Out
TDO
tTDOV
tTDOX
Note
20. Test conditions are specified using the load in TAP AC Test Conditions. tR/tF = 1 V/ns.
Document Number: 001-70328 Rev. *F
Page 17 of 30
CY7C1263XV18
CY7C1265XV18
Identification Register Definitions
Value
Instruction Field
CY7C1263XV18
Revision Number (31:29)
Description
CY7C1265XV18
000
000
Cypress Device ID (28:12)
11010010001010100
11010010001100100
Version number.
Cypress JEDEC ID (11:1)
00000110100
00000110100
Allows unique identification of
SRAM vendor.
ID Register Presence (0)
1
1
Indicates the presence of an ID
register.
Defines the type of SRAM.
Scan Register Sizes
Register Name
Bit Size
Instruction
3
Bypass
1
ID
32
Boundary Scan
109
Instruction Codes
Instruction
Code
Description
EXTEST
000
Captures the input and output ring contents.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operation.
SAMPLE Z
010
Captures the input and output contents. Places the boundary scan register between TDI and
TDO. Forces all SRAM output drivers to a High Z state.
RESERVED
011
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
100
Captures the input and output ring contents. Places the boundary scan register between TDI
and TDO. Does not affect the SRAM operation.
RESERVED
101
Do Not Use: This instruction is reserved for future use.
RESERVED
110
Do Not Use: This instruction is reserved for future use.
BYPASS
111
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operation.
Document Number: 001-70328 Rev. *F
Page 18 of 30
CY7C1263XV18
CY7C1265XV18
Boundary Scan Order
Bit #
Bump ID
Bit #
Bump ID
Bit #
Bump ID
Bit #
Bump ID
0
6R
28
10G
56
6A
84
1J
1
6P
29
9G
57
5B
85
2J
2
6N
30
11F
58
5A
86
3K
3
7P
31
11G
59
4A
87
3J
4
7N
32
9F
60
5C
88
2K
5
7R
33
10F
61
4B
89
1K
6
8R
34
11E
62
3A
90
2L
7
8P
35
10E
63
2A
91
3L
8
9R
36
10D
64
1A
92
1M
9
11P
37
9E
65
2B
93
1L
10
10P
38
10C
66
3B
94
3N
11
10N
39
11D
67
1C
95
3M
12
9P
40
9C
68
1B
96
1N
13
10M
41
9D
69
3D
97
2M
14
11N
42
11B
70
3C
98
3P
15
9M
43
11C
71
1D
99
2N
16
9N
44
9B
72
2C
100
2P
17
11L
45
10B
73
3E
101
1P
18
11M
46
11A
74
2D
102
3R
19
9L
47
10A
75
2E
103
4R
20
10L
48
9A
76
1E
104
4P
21
11K
49
8B
77
2F
105
5P
22
10K
50
7C
78
3F
106
5N
23
9J
51
6C
79
1G
107
5R
24
9K
52
8A
80
1F
108
Internal
25
10J
53
7A
81
3G
26
11J
54
7B
82
2G
27
11H
55
6B
83
1H
Document Number: 001-70328 Rev. *F
Page 19 of 30
CY7C1263XV18
CY7C1265XV18
Power Up Sequence in QDR II+ Xtreme SRAM
PLL Constraints
QDR II+ Xtreme SRAMs must be powered up and initialized in a
predefined manner to prevent undefined operations.
■
PLL uses K clock as its synchronizing input. The input must
have low phase jitter, which is specified as tKC Var.
■
The PLL functions at frequencies down to 120 MHz.
■
If the input clock is unstable and the PLL is enabled, then the
PLL may lock onto an incorrect frequency, causing unstable
SRAM behavior. To avoid this, provide 100 s of stable clock
to relock to the desired clock frequency.
Power Up Sequence
■
Apply power and drive DOFF either HIGH or LOW (All other
inputs can be HIGH or LOW).
❐ Apply VDD before VDDQ.
❐ Apply VDDQ before VREF or at the same time as VREF.
❐ Drive DOFF HIGH.
■
Provide stable DOFF (HIGH), power and clock (K, K) for 100
s to lock the PLL.
Figure 4. Power Up Waveforms
Document Number: 001-70328 Rev. *F
Page 20 of 30
CY7C1263XV18
CY7C1265XV18
Maximum Ratings
Neutron Soft Error Immunity
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Parameter
Storage Temperature ............................... –65 °C to +150 °C
Supply Voltage on VDD Relative to GND .....–0.5 V to +2.9 V
Supply Voltage on VDDQ Relative to GND .... –0.5 V to +VDD
DC Applied to Outputs in High Z ...... –0.5 V to VDDQ + 0.3 V
271
FIT/M
b
25 °C
260
LMBU
Logical
Multi-Bit
Upsets
25 °C
0
0.01 FIT/M
b
Single Event
Latchup
85 °C
0
0.1
FIT/D
ev
* No LMBU or SEL events occurred during testing; this column represents a
statistical 2, 95% confidence limit calculation. For more details refer to
Application Note AN54908 “Accelerated Neutron SER Testing and Calculation of
Terrestrial Failure Rates”
Latch up Current .................................................... > 200 mA
Maximum Junction Temperature..................................125 °C
Unit
Logical
Single-Bit
Upsets
SEL
Static Discharge Voltage
(MIL-STD-883, M. 3015) ......................................... > 2,001V
Max*
LSBU
DC Input Voltage [21] ........................... –0.5 V to VDD + 0.3 V
Current into Outputs (LOW) ........................................ 20 mA
Test
Conditions Typ
Description
Operating Range
Range
Commercial
Ambient
Temperature (TA)
0 °C to +70 °C
VDD [22]
VDDQ [22]
1.8 ± 0.1 V 1.4 V to 1.6 V
Electrical Characteristics
Over the Operating Range
DC Electrical Characteristics
Over the Operating Range
Parameter [23]
Min
Typ
Max
Unit
VDD
Power Supply Voltage
1.7
1.8
1.9
V
VDDQ
I/O Supply Voltage
1.4
1.5
1.6
V
VOH
Output HIGH Voltage
Note 24
VDDQ/2 – 0.12
–
VDDQ/2 + 0.12
V
VOL
Output LOW Voltage
Note 25
VDDQ/2 – 0.12
–
VDDQ/2 + 0.12
V
VOH(LOW)
Output HIGH Voltage
IOH =0.1 mA, Nominal Impedance
VDDQ – 0.2
–
VDDQ
V
VOL(LOW)
Output LOW Voltage
IOL = 0.1 mA, Nominal Impedance
VSS
–
0.2
V
VIH
Input HIGH Voltage
VREF + 0.1
–
VDDQ + 0.15
V
VIL
Input LOW Voltage
–0.15
–
VREF – 0.1
V
IX
Input Leakage Current
GND VI VDDQ
2
–
2
A
IOZ
Output Leakage Current
GND VI VDDQ, Output Disabled
2
–
2
A
Input Reference Voltage
Typical Value = 0.75 V
0.68
0.75
0.86
V
VDD Operating Supply
VDD = Max, IOUT = 0 mA, 633 MHz (× 18)
f = fMAX = 1/tCYC
(× 36)
–
–
1165
mA
–
–
1660
600 MHz (× 18)
–
–
1100
(× 36)
–
–
1570
VREF
IDD
[26]
Description
Test Conditions
mA
Notes
21. Overshoot: VIH(AC) VDDQ + 0.35 V (Pulse width less than tCYC/2), Undershoot: VIL(AC) 0.3 V (Pulse width less than tCYC/2).
22. Power up: Assumes a linear ramp from 0V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
23. All Voltage referenced to Ground.
24. Outputs are impedance controlled. IOH = (VDDQ/2)/(RQ/5) for values of 175 ohms RQ 350 ohms.
25. Outputs are impedance controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175 ohms RQ 350 ohms.
26. The operation current is calculated with 50% read cycle and 50% write cycle.
Document Number: 001-70328 Rev. *F
Page 21 of 30
CY7C1263XV18
CY7C1265XV18
Electrical Characteristics (continued)
Over the Operating Range
DC Electrical Characteristics (continued)
Over the Operating Range
Parameter [23]
ISB1
Description
Automatic Power down
Current
Test Conditions
Min
Typ
Max
Unit
Max VDD,
633 MHz (× 18)
Both Ports Deselected,
(× 36)
VIN VIH or VIN VIL
600 MHz (× 18)
f = fMAX = 1/tCYC,
Inputs Static
(× 36)
–
–
1165
mA
–
–
1660
–
–
1100
–
–
1570
Test Conditions
Min
Typ
Max
Unit
mA
AC Electrical Characteristics
Over the Operating Range
Parameter [27]
Description
VIH
Input HIGH voltage
VREF + 0.2
–
VDDQ + 0.24
V
VIL
Input LOW voltage
–0.24
–
VREF – 0.2
V
Max
Unit
Capacitance
Parameter [28]
Description
CIN
Input capacitance
CO
Output capacitance
Test Conditions
TA = 25 C, f = 1 MHz, VDD = 1.8 V, VDDQ = 1.5 V
4
pF
4
pF
Thermal Resistance
Parameter [28]
JA (0 m/s)
JA (1 m/s)
Description
Thermal resistance
(junction to ambient)
Test Conditions
Socketed on a 170 x 220 x 2.35 mm, eight-layer printed circuit
board
JA (3 m/s)
165-ball FBGA Unit
Package
14.43
°C/W
13.40
°C/W
12.66
°C/W
JB
Thermal resistance
(junction to board)
11.38
°C/W
JC
Thermal resistance
(junction to case)
3.30
°C/W
Notes
27. Overshoot: VIH(AC) < VDDQ + 0.35 V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > 0.3 V (Pulse width less than tCYC/2).
28. Tested initially and after any design or process change that may affect these parameters.
Document Number: 001-70328 Rev. *F
Page 22 of 30
CY7C1263XV18
CY7C1265XV18
AC Test Loads and Waveforms
Figure 5. AC Test Loads and Waveforms
VREF = 0.75 V
VREF
0.75 V
VREF
OUTPUT
Z0 = 50
Device
Under
Test
ZQ
RL = 50
R = 50
ALL INPUT PULSES
1.25 V
0.75 V
OUTPUT
Device
Under
VREF = 0.75 V Test ZQ
RQ =
250
(a)
0.75 V
INCLUDING
JIG AND
SCOPE
5 pF
[29]
0.25 V
Slew Rate = 2 V/ns
RQ =
250
(b)
Note
29. Unless otherwise noted, test conditions are based on signal transition time of 2 V/ns, timing reference levels of 0.75 V, Vref = 0.75 V, RQ = 250 , VDDQ = 1.5 V, input
pulse levels of 0.25 V to 1.25 V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of Figure 5.
Document Number: 001-70328 Rev. *F
Page 23 of 30
CY7C1263XV18
CY7C1265XV18
Switching Characteristics
Over the Operating Range
Parameters [30, 31]
Cypress
Parameter
633 MHz
Description
Consortium
Parameter
VDD(Typical) to the First Access [32]
tPOWER
600 MHz
Unit
Min
Max
Min
Max
1
–
1
–
ms
tCYC
tKHKH
K Clock Cycle Time
1.58
8.4
1.66
8.4
ns
tKH
tKHKL
Input Clock (K/K) HIGH
0.4
–
0.4
–
ns
tKL
tKLKH
Input Clock (K/K) LOW
0.4
–
0.4
–
ns
tKHKH
tKHKH
K Clock Rise to K Clock Rise (rising edge to rising edge)
0.71
–
0.75
–
ns
tSA
tAVKH
Address Setup to K Clock Rise
0.23
–
0.23
–
ns
tSC
tIVKH
–
0.23
–
ns
tSCDDR
tIVKH
Control Setup to K Clock Rise (RPS, WPS)
Double Data Rate Control Setup to Clock (K/K) Rise (BWS0,
BWS1, BWS2, BWS3)
0.23
0.18
–
0.18
–
ns
tDVKH
D[X:0] Setup to Clock (K/K) Rise
0.18
–
0.18
–
ns
tHA
tKHAX
0.23
–
0.23
–
ns
tHC
tKHIX
Address Hold after K Clock Rise
Control Hold after K Clock Rise (RPS, WPS)
0.23
–
0.23
–
ns
tHCDDR
tKHIX
Double Data Rate Control Hold after Clock (K/K) Rise (BWS0,
BWS1, BWS2, BWS3)
0.18
–
0.18
–
ns
tHD
tKHDX
D[X:0] Hold after Clock (K/K) Rise
0.18
–
0.18
–
ns
tCCQO
tCHCQV
K/K Clock Rise to Echo Clock Valid
–
0.45
–
0.45
ns
tCQOH
tCHCQX
–
–0.45
tCQHQV
Echo Clock Hold after K/K Clock Rise
Echo Clock High to Data Valid
–0.45
tCQD
tCQDOH
tCQHQX
Echo Clock High to Data Invalid
–0.09
–
Setup Times
o
Ok
tSD
Hold Times
Output Times
–
ns
0.09
ns
–0.09
–
ns
0.09
[33]
tCQH
tCQHCQL
Output Clock (CQ/CQ) HIGH
0.71
–
0.75
–
ns
tCQHCQH
tCQHCQH
CQ Clock Rise to CQ Clock Rise (rising edge to rising edge) [33] 0.71
–
0.75
–
ns
tCHZ
tCHQZ
tCLZ
tCHQX1
tQVLD
tCQHQVLD
Clock (K/K) Rise to Low Z
Echo Clock High to QVLD Valid [36]
tKC Var
tKC Var
Clock Phase Jitter
tKC lock
tKC lock
PLL Lock Time (K)
Clock (K/K) Rise to High Z (Active to High Z)
[34, 35]
[34, 35]
–
0.45
–
0.45
ns
–0.45
–
–0.45
–
ns
–0.15
0.15
–0.15
0.15
ns
–
0.15
–
0.15
ns
100
–
100
–
s
30
–
30
–
ns
PLL Timing
tKC Reset
tKC Reset
K Static to PLL Reset
[37]
Notes
30. Unless otherwise noted, test conditions are based on signal transition time of 2 V/ns, timing reference levels of 0.75 V, Vref = 0.75 V, RQ = 250 , VDDQ = 1.5 V, input
pulse levels of 0.25 V to 1.25 V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of Figure 5 on page 23.
31. When a part with a maximum frequency above 600 MHz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is being
operated and outputs data with the output timings of that frequency range.
32. This part has a voltage regulator internally; tPOWER is the time that the power must be supplied above VDD(minimum) initially before a read or write operation can be
initiated.
33. These parameters are extrapolated from the input timing parameters (tCYC/2 – 80 ps, where 80 ps is the internal jitter). These parameters are only guaranteed by
design and are not tested in production.
34. tCHZ, tCLZ, are specified with a load capacitance of 5 pF as in (b) of Figure 5 on page 23. Transition is measured ± 100 mV from steady-state voltage.
35. At any voltage and temperature tCHZ is less than tCLZ .
36. tQVLD spec is applicable for both rising and falling edges of QVLD signal.
37. Hold to >VIH or
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