CY7C1292DV18-167BZC

CY7C1292DV18 CY7C1294DV18 9-Mbit QDR- II™ SRAM 2-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports The CY7C1292DV18 and CY7C1294DV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to support Read operations and the Write Port has dedicated Data Inputs to support Write operations. QDR-II architecture has separate data inputs and data outputs to completely eliminate the need to “turn-around” the data bus required with common I/O devices. Access to each port is accomplished through a common address bus. The Read address is latched on the rising edge of the K clock and the Write address is latched on the rising edge of the K clock. Accesses to the QDR-II Read and Write ports are completely independent of one another. In order to maximize data throughput, both Read and Write ports are equipped with Double Data Rate (DDR) interfaces. Each address location is associated with two 18-bit words (CY7C1292DV18) or 36-bit words (CY7C1294DV18) that burst sequentially into or out of the device. Since data can be transferred into and out of the device on every rising edge of both input clocks (K and K and C and C), memory bandwidth is maximized while simplifying system design by eliminating bus “turn-arounds.” — Supports concurrent transactions • 250-MHz clock for high bandwidth • 2-Word Burst on all accesses • Double Data Rate (DDR) interfaces on both Read and Write ports (data transferred at 500 MHz) @ 250 MHz • Two input clocks (K and K) for precise DDR timing — SRAM uses rising edges only • Two input clocks for output data (C and C) to minimize clock-skew and flight-time mismatches • Echo clocks (CQ and CQ) simplify data capture in high-speed systems • Single multiplexed address input bus latches address inputs for both Read and Write ports • Separate Port Selects for depth expansion • Synchronous internally self-timed writes • Available in x 18 and x 36 configurations • Full data coherency, providing most current data Depth expansion is accomplished with Port Selects for each port. Port selects allow each port to operate independently. • Core VDD = 1.8V (±0.1V); I/O VDDQ = 1.4V to VDD • Available in 165-ball FBGA package (13 x 15 x 1.4 mm) • Offered in both lead-free and non-lead free packages All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C (or K or K in a single clock domain) input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry. • Variable drive HSTL output buffers • JTAG 1149.1 compatible test access port • Delay Lock Loop (DLL) for accurate data placement Configurations CY7C1292DV18 – 512K x 18 CY7C1294DV18 – 256K x 36 Selection Guide 250 MHz 200 MHz 167 MHz Unit Maximum Operating Frequency 250 200 167 MHz Maximum Operating Current 600 550 500 mA Cypress Semiconductor Corporation Document #: 001-00350 Rev. *A • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised July 20, 2006 [+] Feedback CY7C1292DV18 CY7C1294DV18 Logic Block Diagram (CY7C1292DV18) D[17:0] K K CLK Gen. DOFF Address Register Read Add. Decode 18 Write Reg 256K x 18 Array A(17:0) Write Reg 256K x 18 Array Address Register Write Add. Decode 18 RPS Control Logic C C Read Data Reg. 36 VREF WPS BWS[1:0] CQ CQ 18 Reg. Control Logic A(17:0) 18 18 Reg. 18 18 Reg. Q[17:0] 18 Logic Block Diagram (CY7C1294DV18) K K CLK Gen. DOFF VREF WPS BWS[3:0] Address Register Read Add. Decode 17 Write Reg 128K x 36 Array Address Register Write Reg 128K x 36 Array A(16:0) 36 Write Add. Decode D[35:0] 17 RPS Control Logic C C Read Data Reg. 72 Control Logic Reg. Reg. 36 Reg. 36 36 Document #: 001-00350 Rev. *A CQ CQ 36 36 A(16:0) Q[35:0] Page 2 of 23 [+] Feedback CY7C1292DV18 CY7C1294DV18 Pin Configurations 165-ball FBGA (13 x 15 x 1.4 mm) Pinout CY7C1292DV18 (512K x 18) 1 A B C D E F G H J K L M N P R CQ 2 3 NC/144M NC/36M 4 5 6 7 8 9 10 11 WPS BWS1 K NC/288M NC/18M NC NC/72M CQ NC Q8 D8 D7 NC Q9 D9 A NC K BWS0 RPS A NC NC NC D11 D10 Q10 VSS VSS A A VSS VSS VSS NC VSS A VSS NC Q7 NC NC NC Q11 VDDQ VSS VSS VSS VDDQ NC D6 Q6 NC Q12 D12 VDDQ VDD VSS VDD VDDQ NC NC Q5 NC D13 VREF NC Q13 VDDQ D14 VDDQ VDDQ VDDQ VDD VDD VDD VSS VSS VSS VDD VDD VDD VDDQ VDDQ VDDQ NC VDDQ NC NC VREF Q4 D5 ZQ D4 NC NC Q14 VDDQ VDD VSS VDD VDDQ NC D3 Q3 NC Q15 D15 VDDQ VSS VSS VSS VDDQ NC NC Q2 NC NC NC D17 D16 Q16 VSS VSS VSS A VSS A VSS A VSS VSS NC NC Q1 NC D2 D1 NC NC Q17 A A C A A NC D0 Q0 TDO TCK A A A C A A A TMS TDI 9 10 11 DOFF NC CY7C1294DV18 (256K x 36) 1 A B C D E F G H J K L M N P R 2 3 5 6 7 8 RPS A WPS BWS2 K BWS1 Q18 D18 A D27 D28 Q28 D20 D19 BWS3 A Q19 VSS VSS VSS K NC/18M VSS BWS0 A VSS Q29 D29 Q20 VDDQ VSS VSS Q30 D30 Q21 D21 VDDQ VDD D22 VREF Q31 Q22 VDDQ D23 VDDQ VDDQ VDDQ VDD VDD VDD Q32 D32 Q23 VDDQ Q33 Q24 D24 VDDQ D33 D34 Q34 D26 D25 Q25 Q35 D35 TDO TCK CQ Q27 DOFF D31 NC/288M NC/72M 4 Document #: 001-00350 Rev. *A NC/36M NC/144M D17 Q17 D16 CQ Q8 VSS VSS Q16 Q7 D15 D8 D7 VSS VDDQ Q15 D6 Q6 VSS VDD VDDQ D14 Q14 Q5 VSS VSS VSS VDD VDD VDD VDDQ VDDQ VDDQ Q13 VDDQ D12 D13 VREF Q4 D5 ZQ D4 VDD VSS VDD VDDQ Q12 D3 Q3 VSS VSS VSS VDDQ D11 Q11 Q2 VSS VSS VSS A VSS A VSS A VSS VSS D10 Q10 Q1 D9 D2 D1 Q26 A A C A A Q9 D0 Q0 A A A C A A A TMS TDI Page 3 of 23 [+] Feedback CY7C1292DV18 CY7C1294DV18 Pin Definitions Pin Name I/O Pin Description D[x:0] InputData input signals, sampled on the rising edge of K and K clocks during valid write Synchronous operations. CY7C1292DV18 - D[17:0] CY7C1294DV18 - D[35:0] WPS InputWrite Port Select, active LOW. Sampled on the rising edge of the K clock. When asserted Synchronous active, a Write operation is initiated. Deasserting will deselect the Write port. Deselecting the Write port will cause D[x:0] to be ignored. BWS0, BWS1, BWS2, BWS3 InputByte Write Select 0, 1, 2 and 3 − active LOW. Sampled on the rising edge of the K and K clocks Synchronous during Write operations. Used to select which byte is written into the device during the current portion of the Write operations. Bytes not written remain unaltered. CY7C1292DV18 − BWS0 controls D[8:0], BWS1 controls D[17:9]. CY7C1294DV18 − BWS0 controls D[8:0], BWS1 controls D[17:9],BWS2 controls D[26:18] and BWS3 controls D[35:27]. All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select will cause the corresponding byte of data to be ignored and not written into the device. A InputAddress Inputs. Sampled on the rising edge of the K (Read address) and K (Write address) Synchronous clocks during active Read and Write operations. These address inputs are multiplexed for both Read and Write operations. Internally, the device is organized as 512K x 18 (2 arrays each of 256K x 18) for CY7C1292DV18 and 256K x 36 (2 arrays each of 128K x 36) for CY7C1294DV18. Therefore 18 address inputs for CY7C1292DV18 and 17 address inputs for CY7C1294DV18. These inputs are ignored when the appropriate port is deselected. Q[x:0] OutputsData Output signals. These pins drive out the requested data during a Read operation. Valid Synchronous data is driven out on the rising edge of both the C and C clocks during Read operations or K and K when in single clock mode. When the Read port is deselected, Q[x:0] are automatically tri-stated. CY7C1292DV18 − Q[17:0] CY7C1294DV18 − Q[35:0] RPS InputRead Port Select, active LOW. Sampled on the rising edge of Positive Input Clock (K). When Synchronous active, a Read operation is initiated. Deasserting will cause the Read port to be deselected. When deselected, the pending access is allowed to complete and the output drivers are automatically tri-stated following the next rising edge of the C clock. Each read access consists of a burst of two sequential transfers. C Input-Clock Positive Input Clock for Output Data. C is used in conjunction with C to clock out the Read data from the device. C and C can be used together to deskew the flight times of various devices on the board back to the controller. See application example for further details. C Input-Clock Negative Input Clock for Output Data. C is used in conjunction with C to clock out the Read data from the device. C and C can be used together to deskew the flight times of various devices on the board back to the controller. See application example for further details. K Input-Clock Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device and to drive out data through Q[x:0] when in single clock mode. All accesses are initiated on the rising edge of K. K Input-Clock Negative Input Clock Input. The rising edge of K is used to capture synchronous inputs being presented to the device and to drive out data through Q[x:0] when in single clock mode. CQ Echo Clock CQ is referenced with respect to C. This is a free running clock and is synchronized to the input clock for output data (C) of the QDR-II. In the single clock mode, CQ is generated with respect to K. The timings for the echo clocks are shown in the AC Timing table. CQ Echo Clock ZQ Input CQ is referenced with respect to C. This is a free running clock and is synchronized to the input clock for output data (C) of the QDR-II. In the single clock mode, CQ is generated with respect to K. The timings for the echo clocks are shown in the AC Timing table. Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 x RQ, where RQ is a resistor connected between ZQ and ground. Alternately, this pin can be connected directly to VDDQ, which enables the minimum impedance mode. This pin cannot be connected directly to GND or left unconnected. Document #: 001-00350 Rev. *A Page 4 of 23 [+] Feedback CY7C1292DV18 CY7C1294DV18 Pin Definitions (continued) Pin Name DOFF I/O Pin Description Input DLL Turn Off, active LOW. Connecting this pin to ground will turn off the DLL inside the device. The timings in the DLL turned off operation will be different from those listed in this data sheet. TDO Output TCK Input TDO for JTAG. TCK pin for JTAG. TDI Input TDI pin for JTAG. TMS Input TMS pin for JTAG. NC N/A Not connected to the die. Can be tied to any voltage level. NC/18M N/A Not connected to the die. Can be tied to any voltage level. NC/36M N/A Not connected to the die. Can be tied to any voltage level. NC/72M N/A Not connected to the die. Can be tied to any voltage level. NC/144M N/A Not connected to the die. Can be tied to any voltage level. NC/288M N/A Not connected to the die. Can be tied to any voltage level. VREF VDD VSS VDDQ InputReference Reference Voltage Input. Static input used to set the reference level for HSTL inputs and Outputs as well as AC measurement points. Power Supply Power supply inputs to the core of the device. Ground Ground for the device. Power Supply Power supply inputs for the outputs of the device. Functional Overview The CY7C1292DV18 and CY7C1294DV18 are synchronous pipelined Burst SRAMs equipped with both a Read port and a Write port. The Read port is dedicated to Read operations and the Write port is dedicated to Write operations. Data flows into the SRAM through the Write port and out through the Read port. These devices multiplex the address inputs in order to minimize the number of address pins required. By having separate Read and Write ports, the QDR-II completely eliminates the need to “turn-around” the data bus and avoids any possible data contention, thereby simplifying system design. Each access consists of two 18-bit data transfers in the case of CY7C1292DV18 and two 36-bit data transfers in the case of CY7C1294DV18 in one clock cycle. Accesses for both ports are initiated on the rising edge of the positive Input Clock (K). All synchronous input timings are referenced from the rising edge of the input clocks (K and K) and all output timings are referenced to the rising edge of output clocks (C and C or K and K when in single clock mode). All synchronous data inputs (D[x:0]) inputs pass through input registers controlled by the input clocks (K and K). All synchronous data outputs (Q[x:0]) outputs pass through output registers controlled by the rising edge of the output clocks (C and C or K and K when in single clock mode). All synchronous control (RPS, WPS, BWS[x:0]) inputs pass through input registers controlled by the rising edge of the input clocks (K and K). CY7C1292DV18 is described in the following sections. The same basic descriptions apply to CY7C1294DV18. Document #: 001-00350 Rev. *A Read Operations The CY7C1292DV18 is organized internally as 2 arrays of 256K x 18. Accesses are completed in a burst of two sequential 18-bit data words. Read operations are initiated by asserting RPS active at the rising edge of the Positive Input Clock (K). The address is latched on the rising edge of the K Clock. The address presented to Address inputs is stored in the Read address register. Following the next K clock rise the corresponding lowest order 18-bit word of data is driven onto the Q[17:0] using C as the output timing reference. On the subsequent rising edge of C, the next 18-bit data word is driven onto the Q[17:0]. The requested data will be valid 0.45 ns from the rising edge of the output clock (C and C or K and K when in single clock mode). Synchronous internal circuitry will automatically tri-state the outputs following the next rising edge of the Output Clocks (C/C). This will allow for a seamless transition between devices without the insertion of wait states in a depth expanded memory. Write Operations Write operations are initiated by asserting WPS active at the rising edge of the Positive Input Clock (K). On the same K clock rise, the data presented to D[17:0] is latched and stored into the lower 18-bit Write Data register provided BWS[1:0] are both asserted active. On the subsequent rising edge of the Negative Input Clock (K), the address is latched and the information presented to D[17:0] is stored into the Write Data register provided BWS[1:0] are both asserted active. The 36 bits of data are then written into the memory array at the specified location. When deselected, the write port will ignore all inputs after the pending Write operations have been completed. Page 5 of 23 [+] Feedback CY7C1292DV18 CY7C1294DV18 Byte Write Operations Programmable Impedance Byte Write operations are supported by the CY7C1292DV18. A Write operation is initiated as described in the Write Operations section above. The bytes that are written are determined by BWS0 and BWS1, which are sampled with each 18-bit data word. Asserting the appropriate Byte Write Select input during the data portion of a Write will allow the data being presented to be latched and written into the device. Deasserting the Byte Write Select input during the data portion of a write will allow the data stored in the device for that byte to remain unaltered. This feature can be used to simplify Read/Modify/Write operations to a Byte Write operation. An external resistor, RQ, must be connected between the ZQ pin on the SRAM and VSS to allow the SRAM to adjust its output driver impedance. The value of RQ must be 5x the value of the intended line impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching with a tolerance of ±15% is between 175Ω and 350Ω, with VDDQ = 1.5V.The output impedance is adjusted every 1024 cycles upon power-up to account for drifts in supply voltage and temperature. Single Clock Mode The CY7C1292DV18 can be used with a single clock that controls both the input and output registers. In this mode, the device will recognize only a single pair of input clocks (K and K) that control both the input and output registers. This operation is identical to the operation if the device had zero skew between the K/K and C/C clocks. All timing parameters remain the same in this mode. To use this mode of operation, the user must tie C and C HIGH at power on. This function is a strap option and not alterable during device operation. Concurrent Transactions The Read and Write ports on the CY7C1292DV18 operate completely independently of one another. Since each port latches the address inputs on different clock edges, the user can Read or Write to any location, regardless of the transaction on the other port. Also, reads and writes can be started in the same clock cycle. If the ports access the same location at the same time, the SRAM will deliver the most recent information associated with the specified address location. This includes forwarding data from a Write cycle that was initiated on the previous K clock rise. Echo Clocks Echo clocks are provided on the QDR-II to simplify data capture on high-speed systems. Two echo clocks are generated by the QDR-II. CQ is referenced with respect to C and CQ is referenced with respect to C. These are free-running clocks and are synchronized to the output clock (C/C) of the QDR-II. In the single clock mode, CQ is generated with respect to K and CQ is generated with respect to K. The timings for the echo clocks are shown in the AC Timing table. DLL These chips utilize a Delay Lock Loop (DLL) that is designed to function between 80 MHz and the specified maximum clock frequency. During power-up, when the DOFF is tied HIGH, the DLL gets locked after 1024 cycles of stable clock. The DLL can also be reset by slowing or stopping the input clock K and K for a minimum of 30 ns. However, it is not necessary for the DLL to be specifically reset in order to lock the DLL to the desired frequency. The DLL will automatically lock 1024 clock cycles after a stable clock is presented.the DLL may be disabled by applying ground to the DOFF pin. For information refer to the application note “DLL Considerations in QDRII/DDRII/QDRII+/DDRII+”. Depth Expansion The CY7C1292DV18 has a Port Select input for each port. This allows for easy depth expansion. Both Port Selects are sampled on the rising edge of the Positive Input Clock only (K). Each port select input can deselect the specified port. Deselecting a port will not affect the other port. All pending transactions (Read and Write) will be completed prior to the device being deselected. Document #: 001-00350 Rev. *A Page 6 of 23 [+] Feedback CY7C1292DV18 CY7C1294DV18 Application Example[1] R = 250οηµσ SRAM #1 Vt D A R R P S # W P S # SRAM #4 ZQ CQ/CQ# Q C C# K K# B W S # R P S # D A DATA IN DATA OUT Address RPS# BUS WPS# MASTER BWS# (CPU CLKIN/CLKIN# or Source K ASIC) Source K# R W P S # B W S # ZQ R = 250οηµσ CQ/CQ# Q C C# K K# Vt Vt Delayed K Delayed K# R Truth R = 50οηµσ Vt = Vddq/2 Table[2, 3, 4, 5, 6, 7] Operation K RPS WPS Write Cycle: Load address on the rising edge of K clock; input write data on K and K rising edges. L-H X L D(A + 0) at K(t) ↑ D(A + 1) at K(t) ↑ Read Cycle: Load address on the rising edge of K clock; wait one and a half cycle; read data on C and C rising edges. L-H L X Q(A + 0) at C(t + 1)↑ Q(A + 1) at C(t + 2) ↑ NOP: No Operation L-H H H D = X, Q = High-Z D = X, Q = High-Z Stopped X X Previous State Previous State Standby: Clock Stopped Write Cycle Descriptions (CY7C1292DV18) BWS0 L BWS1 L K L-H L L – L H L-H L H – H L L-H H L – H H L-H H H – K – DQ DQ [2, 8] Comments During the Data portion of a Write sequence: both bytes (D[17:0]) are written into the device. L-H During the Data portion of a Write sequence: both bytes (D[17:0]) are written into the device. – During the Data portion of a Write sequence: only the lower byte (D[8:0]) is written into the device. D[17:9] will remain unaltered. L-H During the Data portion of a Write sequence: only the lower byte (D[8:0]) is written into the device. D[17:9] will remain unaltered. – During the Data portion of a Write sequence: only the upper byte (D[17:9]) is written into the device. D[8:0] will remain unaltered. L-H During the Data portion of a Write sequence: only the upper byte (D[17:9]) is written into the device. D[8:0] will remain unaltered. – No data is written into the devices during this portion of a Write operation. L-H No data is written into the devices during this portion of a Write operation. Notes: 1. The above application shows four QDR-II being used. 2. X = “Don't Care,” H = Logic HIGH, L= Logic LOW, ↑represents rising edge. 3. Device will power-up deselected and the outputs in a tri-state condition. 4. “A” represents address location latched by the devices when transaction was initiated. A + 0, A + 1 represents the internal address sequence in the burst. 5. “t” represents the cycle at which a Read/Write operation is started. t + 1 and t + 2 are the first and second clock cycles respectively succeeding the “t” clock cycle. 6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode. 7. It is recommended that K = K and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically. 8. Assumes a Write cycle was initiated per the Write Port Cycle Description Truth Table. NWS0, NWS1, BWS0, BWS1, BWS2 and BWS3 can be altered on different portions of a Write cycle, as long as the set-up and hold requirements are achieved. Document #: 001-00350 Rev. *A Page 7 of 23 [+] Feedback CY7C1292DV18 CY7C1294DV18 Write Cycle Descriptions (CY7C1294DV18) BWS0 BWS1 BWS2 BWS3 L L L L K L-H L L L L - L H H H L-H L H H H - H L H H L-H H L H H - H H L H L-H H H L H - H H H L L-H H H H L - H H H H L-H H H H H - Document #: 001-00350 Rev. *A K - [2, 8] Comments During the Data portion of a Write sequence, all four bytes (D[35:0]) are written into the device. L-H During the Data portion of a Write sequence, all four bytes (D[35:0]) are written into the device. - During the Data portion of a Write sequence, only the lower byte (D[8:0]) is written into the device. D[35:9] will remain unaltered. L-H During the Data portion of a Write sequence, only the lower byte (D[8:0]) is written into the device. D[35:9] will remain unaltered. - During the Data portion of a Write sequence, only the byte (D[17:9]) is written into the device. D[8:0] and D[35:18] will remain unaltered. L-H During the Data portion of a Write sequence, only the byte (D[17:9]) is written into the device. D[8:0] and D[35:18] will remain unaltered. - During the Data portion of a Write sequence, only the byte (D[26:18]) is written into the device. D[17:0] and D[35:27] will remain unaltered. L-H During the Data portion of a Write sequence, only the byte (D[26:18]) is written into the device. D[17:0] and D[35:27] will remain unaltered. During the Data portion of a Write sequence, only the byte (D[35:27]) is written into the device. D[26:0] will remain unaltered. L-H During the Data portion of a Write sequence, only the byte (D[35:27]) is written into the device. D[26:0] will remain unaltered. - No data is written into the device during this portion of a Write operation. L-H No data is written into the device during this portion of a Write operation. Page 8 of 23 [+] Feedback CY7C1292DV18 CY7C1294DV18 IEEE 1149.1 Serial Boundary Scan (JTAG) These SRAMs incorporate a serial boundary scan test access port (TAP) in the FBGA package. This part is fully compliant with IEEE Standard #1149.1-1900. The TAP operates using JEDEC standard 1.8V I/O logic levels. Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be connected to VDD through a pull-up resistor. TDO should be left unconnected. Upon power-up, the device will come up in a reset state which will not interfere with the operation of the device. Test Access Port—Test Clock The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. Test Mode Select The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this pin unconnected if the TAP is not used. The pin is pulled up internally, resulting in a logic HIGH level. Test Data-In (TDI) The TDI pin is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see the TAP Controller State Diagram. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) on any register. Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO pins as shown in TAP Controller Block Diagram. Upon power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section. When the TAP controller is in the Capture IR state, the two least significant bits are loaded with a binary “01” pattern to allow for fault isolation of the board level serial test path. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between TDI and TDO pins. This allows data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. Boundary Scan Register The boundary scan register is connected to all of the input and output pins on the SRAM. Several no connect (NC) pins are also included in the scan register to reserve pins for higher density devices. The boundary scan register is loaded with the contents of the RAM Input and Output ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO pins when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the Input and Output ring. The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO. Test Data-Out (TDO) Identification (ID) Register The TDO output pin is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine (see Instruction codes). The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in the Identification Register Definitions table. Performing a TAP Reset A Reset is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating. At power-up, the TAP is reset internally to ensure that TDO comes up in a high-Z state. TAP Instruction Set TAP Registers Eight different instructions are possible with the three-bit instruction register. All combinations are listed in the Instruction Code table. Three of these instructions are listed as RESERVED and should not be used. The other five instructions are described in detail below. Registers are connected between the TDI and TDO pins and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction registers. Data is serially loaded into the TDI pin on the rising edge of TCK. Data is output on the TDO pin on the falling edge of TCK. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO pins. To execute the instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state. Document #: 001-00350 Rev. *A Page 9 of 23 [+] Feedback CY7C1292DV18 CY7C1294DV18 IDCODE The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO pins and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state. SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO pins when the TAP controller is in a Shift-DR state. The SAMPLE Z command puts the output bus into a High-Z state until the next command is given during the “Update IR” state. SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. The user must be aware that the TAP controller clock can only operate at a frequency up to 20 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output will undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This will not harm the device, but there is no guarantee as to the value that will be captured. Repeatable results may not be possible. To guarantee that the boundary scan register will capture the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller's capture set-up plus hold times (tCS and tCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK captured in the boundary scan register. Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required—that is, while data captured is shifted out, the preloaded data can be shifted in. BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. EXTEST The EXTEST instruction enables the preloaded data to be driven out through the system output pins. This instruction also selects the boundary scan register to be connected for serial access between the TDI and TDO in the shift-DR controller state. EXTEST OUTPUT BUS TRI-STATE IEEE Standard 1149.1 mandates that the TAP controller be able to put the output bus into a tri-state mode. The boundary scan register has a special bit located at bit #47. When this scan cell, called the “extest output bus tri-state,” is latched into the preload register during the “Update-DR” state in the TAP controller, it will directly control the state of the output (Q-bus) pins, when the EXTEST is entered as the current instruction. When HIGH, it will enable the output buffers to drive the output bus. When LOW, this bit will place the output bus into a High-Z condition. This bit can be set by entering the SAMPLE/PRELOAD or EXTEST command, and then shifting the desired bit into that cell, during the “Shift-DR” state. During “Update-DR”, the value loaded into that shift-register cell will latch into the preload register. When the EXTEST instruction is entered, this bit will directly control the output Q-bus pins. Note that this bit is pre-set LOW to enable the output when the device is powered-up, and also when the TAP controller is in the “Test-Logic-Reset” state. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions. PRELOAD allows an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells prior to the selection of another boundary scan test operation. Document #: 001-00350 Rev. *A Page 10 of 23 [+] Feedback CY7C1292DV18 CY7C1294DV18 TAP Controller State Diagram[9] 1 TEST-LOGIC RESET 0 0 TEST-LOGIC/ IDLE 1 1 1 SELECT DR-SCAN SELECT IR-SCAN 0 0 1 1 CAPTURE-DR CAPTURE-IR 0 0 0 SHIFT-DR 0 SHIFT-IR 1 1 1 EXIT1-DR 1 EXIT1-IR 0 0 PAUSE-DR 0 0 PAUSE-IR 1 1 0 0 EXIT2-DR EXIT2-IR 1 1 UPDATE-DR 1 0 UPDATE-IR 1 0 Note: 9. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document #: 001-00350 Rev. *A Page 11 of 23 [+] Feedback CY7C1292DV18 CY7C1294DV18 TAP Controller Block Diagram 0 Bypass Register Selection Circuitry 2 TDI 1 0 1 0 Selection Circuitry TDO Instruction Register 31 30 29 . . 2 Identification Register 106 . . . . 2 1 0 Boundary Scan Register TCK TAP Controller TMS TAP Electrical Characteristics Over the Operating Range [10, 11, 12] Parameter Description Test Conditions Min. VOH1 Output HIGH Voltage IOH = −2.0 mA 1.4 VOH2 Output HIGH Voltage IOH = −100 µA 1.6 VOL1 Output LOW Voltage IOL = 2.0 mA IOL = 100 µA VOL2 Output LOW Voltage VIH Input HIGH Voltage VIL Input LOW Voltage IX Input and OutputLoad Current GND ≤ VI ≤ VDD Max. Unit V V 0.4 V 0.2 V 0.65VDD VDD + 0.3 V –0.3 0.35VDD V −5 5 µA Notes: 10. These characteristic pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics table. 11. Overshoot: VIH(AC) < VDDQ +0.85V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > –1.5V (Pulse width less than tCYC/2). 12. All voltage referenced to Ground. Document #: 001-00350 Rev. *A Page 12 of 23 [+] Feedback CY7C1292DV18 CY7C1294DV18 TAP AC Switching Characteristics Over the Operating Range[13, 14] Parameter Description Min. Max. Unit 20 MHz tTCYC TCK Clock Cycle Time tTF TCK Clock Frequency tTH TCK Clock HIGH 20 ns tTL TCK Clock LOW 20 ns 50 ns Set-up Times tTMSS TMS Set-up to TCK Clock Rise 5 ns tTDIS TDI Set-up to TCK Clock Rise 5 ns tCS Capture Set-up to TCK Rise 5 ns tTMSH TMS Hold after TCK Clock Rise 5 ns tTDIH TDI Hold after Clock Rise 5 ns tCH Capture Hold after Clock Rise 5 ns Hold Times Output Times tTDOV TCK Clock LOW to TDO Valid tTDOX TCK Clock LOW to TDO Invalid 10 0 ns ns TAP Timing and Test Conditions[13] 0.9V 50Ω ALL INPUT PULSES 1.8V TDO 0.9V Z0 = 50Ω 0V CL = 20 pF tTH tTL GND (a) Test Clock TCK tTCYC tTMSS tTMSH Test Mode Select TMS tTDIS tTDIH Test Data-In TDI Test Data-Out TDO tTDOV tTDOX Notes: 13. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns. 14. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register. Document #: 001-00350 Rev. *A Page 13 of 23 [+] Feedback CY7C1292DV18 CY7C1294DV18 Identification Register Definitions Value Instruction Field CY7C1292DV18 CY7C1294DV18 000 000 Cypress Device ID (28:12) 11010011010010110 11010011010100110 Cypress JEDEC ID (11:1) 00000110100 00000110100 ID Register Presence (0) 1 1 Revision Number (31:29) Description Version number. Defines the type of SRAM. Unique identification of SRAM vendor. Indicates the presence of an ID register. Scan Register Sizes Register Name Bit Size Instruction 3 Bypass 1 ID 32 Boundary Scan Cells 107 Instruction Codes Instruction Code Description EXTEST 000 Captures the Input/Output ring contents. IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operation. SAMPLE Z 010 Captures the Input/Output contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High-Z state. RESERVED 011 Do Not Use: This instruction is reserved for future use. SAMPLE/PRELOAD 100 Captures the Input/Output ring contents. Places the boundary scan register between TDI and TDO. Does not affect the SRAM operation. RESERVED 101 Do Not Use: This instruction is reserved for future use. RESERVED 110 Do Not Use: This instruction is reserved for future use. BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operation. Document #: 001-00350 Rev. *A Page 14 of 23 [+] Feedback CY7C1292DV18 CY7C1294DV18 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID 0 6R 27 11H 54 7B 81 3G 1 6P 28 10G 55 6B 82 2G 2 6N 29 9G 56 6A 83 1J 3 7P 30 11F 57 5B 84 2J 4 7N 31 11G 58 5A 85 3K 5 7R 32 9F 59 4A 86 3J 6 8R 33 10F 60 5C 87 2K 7 8P 34 11E 61 4B 88 1K 8 9R 35 10E 62 3A 89 2L 9 11P 36 10D 63 1H 90 3L 10 10P 37 9E 64 1A 91 1M 11 10N 38 10C 65 2B 92 1L 12 9P 39 11D 66 3B 93 3N 13 10M 40 9C 67 1C 94 3M 14 11N 41 9D 68 1B 95 1N 15 9M 42 11B 69 3D 96 2M 16 9N 43 11C 70 3C 97 3P 17 11L 44 9B 71 1D 98 2N 18 11M 45 10B 72 2C 99 2P 19 9L 46 11A 73 3E 100 1P 20 10L 47 Internal 74 2D 101 3R 21 11K 48 9A 75 2E 102 4R 22 10K 49 8B 76 1E 103 4P 23 9J 50 7C 77 2F 104 5P 24 9K 51 6C 78 3F 105 5N 25 10J 52 8A 79 1G 106 5R 26 11J 53 7A 80 1F Document #: 001-00350 Rev. *A Page 15 of 23 [+] Feedback CY7C1292DV18 CY7C1294DV18 Power-Up Sequence in QDR-II SRAM[16] DLL Constraints QDR-II SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. • DLL uses K clock as its synchronizing input. The input should have low phase jitter, which is specified as tKC Var. Power-Up Sequence • The DLL will function at frequencies down to 80 MHz. • Apply power with DOFF tied HIGH (All other inputs can be HIGH or LOW) — Apply VDD before VDDQ — Apply VDDQ before VREF or at the same time as VREF • If the input clock is unstable and the DLL is enabled, then the DLL may lock onto an incorrect frequency, causing unstable SRAM behavior. To avoid this, provide 1024 cycles stable clock to relock to the desired clock frequency. • Provide stable power and clock (K, K) for 1024 cycles to lock the DLL. ~ ~ Power-up Waveforms K K ~ ~ Unstable Clock > 1024 Stable clock Start Normal Operation Clock Start (Clock Starts after V DD / V DDQ Stable) VDD / VDDQ DOFF V DD / V DDQ Stable (< +/- 0.1V DC per 50ns ) Fix High (or tied to VDDQ) Notes: 15. It is recommended that the DOFF pin be pulled HIGH via a pull up resistor of 1Kohm. 16. During Power-Up, when the DOFF is tied HIGH, the DLL gets locked after 1024 cycles of stable clock. Document #: 001-00350 Rev. *A Page 16 of 23 [+] Feedback CY7C1292DV18 CY7C1294DV18 Maximum Ratings Current into Outputs (LOW)......................................... 20 mA (Above which the useful life may be impaired.) Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Storage Temperature ................................. –65°C to +150°C Latch-up Current.................................................... > 200 mA Ambient Temperature with Power Applied............................................. –55°C to +125°C Operating Range Supply Voltage on VDD Relative to GND........ –0.5V to +2.9V Supply Voltage on VDDQ Relative to GND ...... –0.5V to +VDD DC Voltage Applied to Outputs in High-Z State .................................... –0.5V to VDDQ + 0.3V Range Ambient Temperature (TA) VDD[19] VDDQ[19] 0°C to +70°C 1.8 ± 0.1 V 1.4V to VDD Com’l Ind’l –40°C to +85°C DC Input Voltage[11] ...............................–0.5V to VDD + 0.3V Electrical Characteristics Over the Operating Range[12, 19] DC Electrical Characteristics Over the Operating Range Parameter Description VDD Power Supply Voltage VDDQ I/O Supply Voltage VOH Output HIGH Voltage VOL VOH(LOW) Test Conditions Min. Typ. Max. Unit 1.7 1.8 1.9 V 1.4 1.5 VDD V Note 17 VDDQ/2 – 0.12 VDDQ/2 + 0.12 V Output LOW Voltage Note 18 VDDQ/2 – 0.12 VDDQ/2 + 0.12 V Output HIGH Voltage IOH = −0.1 mA, Nominal Impedance VDDQ – 0.2 VDDQ V VOL(LOW) Output LOW Voltage IOL = 0.1 mA, Nominal Impedance VIH Input HIGH Voltage[11] VIL Input LOW Voltage[11] IX Input Leakage Current GND ≤ VI ≤ VDDQ IOZ Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled VREF Input Reference Voltage[20] Typical Value = 0.75V IDD VDD Operating Supply ISB1 Automatic Power-down Current VSS 0.2 V VREF + 0.1 VDDQ+0.3 V –0.3 VREF – 0.1 V −5 5 µA −5 0.68 0.75 VDD = Max., IOUT = 0 mA, 167 MHz f = fMAX = 1/tCYC 200 MHz 5 µA 0.95 V 500 mA 550 mA 250 MHz 600 mA Max. VDD, Both Ports 167 MHz Deselected, VIN ≥ VIH or 200 MHz VIN ≤ VIL f = fMAX = 1/tCYC, 250 MHz Inputs Static 240 mA 260 mA 280 mA Max. Unit AC Input Requirements Over the Operating Range Parameter Description Test Conditions Min. Typ. VIH Input HIGH Voltage VREF + 0.2 – – V VIL Input LOW Voltage – – VREF - 0.2 V Capacitance[21] Parameter Description CIN Input Capacitance CCLK Clock Input Capacitance CO Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VDD = 1.8V VDDQ = 1.5V Max. Unit 5 pF 6 pF 7 pF Notes: 17. Output are impedance controlled. IOH = –(VDDQ/2)/(RQ/5) for values of 175Ω