CY7C1298F-133AC

CY7C1298F 1-Mbit (64K x 18) Pipelined DCD Sync SRAM Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect) — Depth expansion without wait state • 64K × 18-bit common I/O architecture • 3.3V –5% and +10% core power supply (VDD) • 3.3V I/O supply (VDDQ) • Fast clock-to-output times — 3.5ns (for 166-MHz device) — 4.0ns (for 133-MHz device) • Provide high-performance 3-1-1-1 access rate • User-selectable burst counter supporting Intel Pentium interleaved or linear burst sequences • Separate processor and controller address strobes • Synchronous self-timed writes • Asynchronous Output Enable • JEDEC-standard 100-pin TQFP package and pinout • “ZZ” Sleep Mode option Functional Description[1] The CY7C1298F SRAM integrates 65,536x18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BW[A:B], and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin. Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor (ADSP) or Address Strobe Controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin (ADV). Address, data inputs, and write controls are registered on-chip to initiate a self-timed Write cycle.This part supports Byte Write operations (see Pin Descriptions and Truth Table for further details). Write cycles can be one to two bytes wide as controlled by the byte write control inputs. GW active LOW causes all bytes to be written. This device incorporates an additional pipelined enable register which delays turning off the output buffers an additional cycle when a deselect is executed.This feature allows depth expansion without penalizing system performance. The CY7C1298F operates from a +3.3V core power supply while all outputs operate with a +3.3V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible. Selection Guide 166 MHz Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 3.5 240 40 133 MHz 4.0 225 40 Unit ns mA mA Shaded areas contain advance information. Please contact your local CYpress sales representative for availability of these parts. Note: 1. . For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05417 Rev. *A • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised April 7, 2004 CY7C1298F Functional Block Diagram—64Kx18 A0, A1, A ADDRESS REGISTER 2 A[1:0] MODE ADV CLK Q1 BURST COUNTER AND LOGIC CLR Q0 ADSC ADSP DQB, DQPB BYTE WRITE REGISTER DQA , DQPA BYTE WRITE REGISTER ENABLE REGISTER DQB , DQPB BYTE WRITE DRIVER DQA, DQPA BYTE WRITE DRIVER MEMORY ARRAY SENSE AMPS BWB OUTPUT REGISTERS OUTPUT BUFFERS E DQs, DQPA DQPB BWA BWE GW CE1 CE2 CE3 OE PIPELINED ENABLE INPUT REGISTERS ZZ SLEEP CONTROL Document #: 38-05417 Rev. *A Page 2 of 15 CY7C1298F Pin Configurations 100-pin TQFP Top View VDDQ VSSQ NC NC DQB DQB VSSQ VDDQ DQB DQB NC VDD NC VSS DQB DQB VDDQ VSSQ DQB DQB DQPB NC VSSQ VDDQ NC NC NC NC NC NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A A CE1 CE2 NC NC BWB BWA CE3 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A CY7C1298F (64K x 18) A NC NC VDDQ VSSQ NC DQPA DQA DQA VSSQ VDDQ DQA DQA VSS NC VDD ZZ DQA DQA VDDQ VSSQ DQA DQA NC NC VSSQ VDDQ NC NC NC MODE A A A A A1 A0 NC NC VSS VDD NC NC Document #: 38-05417 Rev. *A A A A A NC NC A 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Page 3 of 15 CY7C1298F Pin Descriptions Pin A0, A1, A TQFP Type Description 37,36,32,33 InputAddress Inputs used to select one of the 64K address locations. Sampled at 34,35,44,45, Synchronous the rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 46,47,48,80, are sampled active. A[1:0] are fed to the two-bit counter. 81,82,99,100 93,94 88 InputByte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes Synchronous to the SRAM. Sampled on the rising edge of CLK. InputGlobal Write Enable Input, active LOW. When asserted LOW on the rising edge Synchronous of CLK, a global write is conducted (ALL bytes are written, regardless of the values on BW[A:B] and BWE). InputByte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This Synchronous signal must be asserted LOW to conduct a byte write. InputClock Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst counter when ADV is asserted LOW, during a burst operation. BW[A:B] GW BWE CLK CE1 CE2 CE3 OE 87 89 98 InputChip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in Synchronous conjunction with CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. InputChip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in Synchronous conjunction with CE1 and CE3 to select/deselect the device. InputChip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in Synchronous conjunction with CE1 and CE2 to select/deselect the device. InputOutput Enable, asynchronous input, active LOW. Controls the direction of the Asynchronous I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE is masked during the first clock of a read cycle when emerging from a deselected state. InputAdvance Input signal, sampled on the rising edge of CLK, active LOW. When Synchronous asserted, it automatically increments the address in a burst cycle. InputAddress Strobe from Processor, sampled on the rising edge of CLK, active Synchronous LOW. When asserted LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH. InputAddress Strobe from Controller, sampled on the rising edge of CLK, active Synchronous LOW. When asserted LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. InputZZ “sleep” Input, active HIGH. When asserted HIGH places the device in a Asynchronous non-time-critical “sleep” condition with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin has an internal pull-down. I/OBidirectional Data I/O lines. As inputs, they feed into an on-chip data register that Synchronous is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQP[A:B] are placed in a three-state condition. Power Supply Power supply inputs to the core of the device. Ground I/O Power Supply I/O Ground Ground for the core of the device. Power supply for the I/O circuitry. 97 92 86 ADV ADSP 83 84 ADSC 85 ZZ 64 DQs DQP[A:B] 8,9,12,13, 18,19,22, 23,24,58, 59,62,63, 68,69,72, 73,74 15,41,65, 91 17,40,67, 90 4,11,20,27, 54,61,70, 77 5,10,21,26, 55,60,71, 76 VDD VSS VDDQ VSSQ Ground for the I/O circuitry. Document #: 38-05417 Rev. *A Page 4 of 15 CY7C1298F Pin Descriptions (continued) Pin MODE 31 TQFP Type InputStatic Description Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD or left floating selects interleaved burst sequence. This is a strap pin and should remain static during device operation. Mode Pin has an internal pull-up. No Connects. Not internally connected to the die. NC 1,2,3,6,7,14, 16,25,28,29, 30,38,39,42, 43,49,50,51, 52,53,56,57, 66,75,78,79, 95,96 Functional Overview All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The CY7C1298F supports secondary cache in systems utilizing either a linear or interleaved burst sequence. The interleaved burst order supports Pentium and i486 processors. The linear burst sequence is suited for processors that utilize a linear burst sequence. The burst order is user selectable, and is determined by sampling the MODE input. Accesses can be initiated with either the Processor Address Strobe (ADSP) or the Controller Address Strobe (ADSC). Address advancement through the burst sequence is controlled by the ADV input. A two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. Byte write operations are qualified with the Byte Write Enable (BWE) and Byte Write Select (BW[A:B]) inputs. A Global Write Enable (GW) overrides all byte write inputs and writes data to all four bytes. All writes are simplified with on-chip synchronous self-timed write circuitry. Synchronous Chip Selects CE1, CE2, CE3 and an asynchronous Output Enable (OE) provide for easy bank selection and output three-state control. ADSP is ignored if CE1 is HIGH. Single Read Accesses This access is initiated when the following conditions are satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2) chip selects are all asserted active, and (3) the write signals (GW, BWE) are all deasserted HIGH. ADSP is ignored if CE1 is HIGH. The address presented to the address inputs is stored into the address advancement logic and the Address Register while being presented to the memory core. The corresponding data is allowed to propagate to the input of the Output Registers. At the rising edge of the next clock the data is allowed to propagate through the output register and onto the data bus within tco if OE is active LOW. The only exception occurs when the SRAM is emerging from a deselected state to a selected state, its outputs are always three-stated during the first cycle of the access. After the first cycle of the access, the outputs are controlled by the OE signal. Consecutive single read cycles are supported. The CY7C1298F is a double-cycle deselect part. Once the SRAM is deselected at clock rise by the chip select and either ADSP or ADSC signals, its output will three-state immediately after the next clock rise. Single Write Accesses Initiated by ADSP This access is initiated when both of the following conditions are satisfied at clock rise: (1) ADSP is asserted LOW, and (2) chip select is asserted active. The address presented is loaded into the address register and the address advancement logic while being delivered to the memory core. The write signals (GW, BWE, and BW[A:B]) and ADV inputs are ignored during this first cycle. ADSP triggered write accesses require two clock cycles to complete. If GW is asserted LOW on the second clock rise, the data presented to the DQx inputs is written into the corresponding address location in the memory core. If GW is HIGH, then the write operation is controlled by BWE and BW[A:B] signals. The CY7C1298F provides byte write capability that is described in the Write Cycle Description table. Asserting the Byte Write Enable input (BWE) with the selected Byte Write input will selectively write to only the desired bytes. Bytes not selected during a byte write operation will remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. Because the CY7C1298F is a common I/O device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQ inputs. Doing so will three-state the output drivers. As a safety precaution, DQ are automatically three-stated whenever a write cycle is detected, regardless of the state of OE. Single Write Accesses Initiated by ADSC ADSC write accesses are initiated when the following conditions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deasserted HIGH, (3) chip select is asserted active, and (4) the appropriate combination of the write inputs (GW, BWE, and BW[A:B]) are asserted active to conduct a write to the desired byte(s). ADSC triggered write accesses require a single clock cycle to complete. The address presented is loaded into the address register and the address advancement logic while being delivered to the memory core. The ADV input is ignored during this cycle. If a global write is conducted, the data presented to the DQX is written into the corresponding address location in the memory core. If a byte write is conducted, only the selected bytes are written. Bytes not selected during a byte write operation will remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. Page 5 of 15 Document #: 38-05417 Rev. *A CY7C1298F Because the CY7C1298F is a common I/O device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQX inputs. Doing so will three-state the output drivers. As a safety precaution, DQX are automatically three-stated whenever a write cycle is detected, regardless of the state of OE. considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the “sleep” mode. CEs, ADSP, and ADSC must remain inactive for the duration of tZZREC after the ZZ input returns LOW. Interleaved ‘Burst Address Table (MODE = Floating or VDD) First Address A1, A0 00 01 10 11 Second Address A1, A0 01 00 11 10 Third Address A1, A0 10 11 00 01 Fourth Address A1, A0 11 10 01 00 Burst Sequences The CY7C1298F provides a two-bit wraparound counter, fed by A[1:0], that implements either an interleaved or linear burst sequence. The interleaved burst sequence is designed specifically to support Intel Pentium applications. The linear burst sequence is designed to support processors that follow a linear burst sequence. The burst sequence is user selectable through the MODE input. Both read and write burst operations are supported Asserting ADV LOW at clock rise will automatically increment the burst counter to the next address in the burst sequence. Both read and write burst operations are supported. Linear Burst Address Table (MODE = GND) First Address A1, A0 00 01 10 11 Second Address A1, A0 01 10 11 00 Third Address A1, A0 10 11 00 01 Fourth Address A1, A0 11 00 01 10 Sleep Mode The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not Truth Table [2,3, 4, 5, 6] Address Used CE1 CE3 CE2 ZZ ADSP ADSC Deselected Cycle, Power-down None H X X L X L Operation Deselected Cycle, Power-down Deselected Cycle, Power-down Deselected Cycle, Power-down Deselected Cycle, Power-down ZZ Mode, Power-Down Read Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Begin Burst Read Cycle, Begin Burst Read Cycle, Begin Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Continue Burst Write Cycle, Continue Burst None None None None None External External External External External Next Next Next Next Next Next L L L L X L L L L L X X H H X H X H X H X L L L L L X X X X X X L X L X X H H H H H X X X X X X L L L L H L L L L L L L L L L L L L H H X L L H H H H H X X H X X X L L X X X L L L H H H H H H ADV X X X X X X X X X X X L L L L L L WRITE X X X X X X X X L H H H H H H L L OE X X X X X X L H X L H L H L H X X CLK L-H L-H L-H L-H L-H X L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H DQ three-state three-state three-state three-state three-state three-state Q three-state D Q three-state Q three-state Q three-state D D Notes: 2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. 3. WRITE =L when any one or more Byte Write enable signals (BWA,BWB) and BWE=L or GW=L. WRITE=H when all Byte write enable signals (BWA, BWB),BWE, GW=H. 4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock. 5. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW[A: B]. Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state. OE is a don't care for the remainder of the write cycle. 6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are three-state when OE is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW). Document #: 38-05417 Rev. *A Page 6 of 15 CY7C1298F Truth Table (continued)[2,3, 4, 5, 6] Operation Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Write Cycle, Suspend Burst Write Cycle, Suspend Burst Address Used CE1 CE3 CE2 ZZ ADSP ADSC Current X X X L H H Current Current Current Current Current X H H X H X X X X X X X X X X L L L L L H X X H X H H H H H ADV H H H H H H WRITE H H H H L L OE L H L H X X CLK L-H L-H L-H L-H L-H L-H DQ Q three-state Q three-state D D Truth Table for Read/Write[2,3] Function Read Read Write byte A – (DQA and DQPA) Write byte B – (DQB and DQPB) Write all bytes Write all bytes GW H H H H H L BWE H L L L L X BWA X H L H L X BWB X H H L L X ZZ Mode Electrical Characteristics Parameter IDDZZ tZZS tZZREC tZZI tRZZI Description Snooze mode standby current Device operation to ZZ ZZ recovery time ZZ Active to snooze current ZZ inactive to exit snooze current Test Conditions ZZ > VDD − 0.2V ZZ > VDD − 0.2V ZZ < 0.2V This parameter is sampled This parameter is sampled 0 2tCYC 2tCYC Min. Max. 40 2tCYC Unit mA ns ns ns ns Document #: 38-05417 Rev. *A Page 7 of 15 CY7C1298F Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature .................................... –65°C to +150° Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage on VDD Relative to GND........ –0.5V to +4.6V DC Voltage Applied to Outputs in three-state ........................................ –0.5V to VDDQ +0.5V DC Input Voltage......................................–0.5V to VDD+0.5V Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage........................................... > 2001V (per MIL-STD-883,Method 3015) Latch -up Current.................................................... > 200 mA Operating Range Range Com’l Ambient Temperature (TA) 0°C to +70°C VDD 3.3V −5%/+10% VDDQ 3.3V −5% to VDD Electrical Characteristics Over the Operating Range[7,8] Parameter VDD VDDQ VOH VOL VIH VIL IX Description Power Supply Voltage I/O Supply Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage[7] Input LOW Voltage[7] VDDQ = 3.3V, VDD = Min., IOH = –4.0 mA VDDQ = 3.3V, VDD = Min., IOL = 8.0 mA VDDQ = 3.3V VDDQ = 3.3V 2.0 –0.3 –5 –30 5 –5 30 –5 5 240 225 100 90 40 6-ns cycle, 166 MHz 7.5-ns cycle, 133 MHz Test Conditions Min. 3.135 3.135 2.4 0.4 VDD + 0.3V 0.8 5 Max. 3.6 VDD Unit V V V V V V µA µA µA µA µA µA mA mA mA mA mA Input Load Current except ZZ GND ≤ VI ≤ VDDQ and MODE Input Current of MODE Input Current of ZZ Input = VSS Input = VDD Input = VSS Input = VDD GND ≤ VI ≤ VDDQ, Output Disabled IOZ IDD ISB1 ISB2 ISB3 Output Leakage Current VDD Operating Supply Current VDD = Max., IOUT = 0 mA, f = fMAX = 1/tCYC Automatic CS Power-down Current—TTL Inputs Automatic CS Power-down Current—CMOS Inputs Automatic CS Power-down Current—CMOS Inputs Automatic CS Power-down Current—TTL Inputs VDD = Max., Device Deselected, 6-ns cycle, 166 MHz VIN ≥ VIH or VIN ≤ VIL, 7.5-ns cycle, 133 MHz f = fMAX = 1/tCYC VDD = Max., Device Deselected, All speeds VIN ≤ 0.3V or VIN > VDDQ – 0.3V, f = 0 VDD = Max., Device Deselected, 6-ns cycle, 166 MHz or VIN ≤ 0.3V or 7.5-ns cycle, 133 MHz VIN > VDDQ – 0.3V, f = fMAX = 1/tCYC VDD = Max., Device Deselected, All speeds VIN ≥ VIH or VIN ≤ VIL, f = 0 85 75 45 mA mA mA ISB4 Thermal Characteristics[9] Parameter Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51 TQFP Package 41.83 9.99 Unit °C/W °C/W ΘJA ΘJC Notes: 7. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC)> -2V (Pulse width less than tCYC/2). 8. Power-up: Assumes a linear ramp from 0v to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD. Document #: 38-05417 Rev. *A Page 8 of 15 CY7C1298F Capacitance[9] Parameter CIN CCLK CI/O Description Input Capacitance Clock Input Capacitance Input/Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VDD = 3.3V VDDQ = 3.3V Max. 5 5 5 Unit pF pF pF AC Test Loads and Waveforms 3.3V I/O Test Load OUTPUT Z0 = 50Ω 3.3V OUTPUT RL = 50Ω VDDQ 5 pF GND R = 351Ω 10% R = 317Ω ALL INPUT PULSES 90% 90% 10% ≤1ns VT = 1.5V INCLUDING JIG AND SCOPE ≤ 1ns (a) (b) [15] (c) Switching Characteristics Over the Operating Range Parameter tPOWER Clock tCYC tCH tCL Output Times tCO tDOH tCLZ tCHZ tOEV tOELZ tOEHZ Set-up Times tAS tADS tADVS tWES tDS Address Set-up Before CLK Rise Data Output Valid After CLK Rise Data Output Hold After CLK Rise Clock to Low-Z[11, 12, 13] Clock to High-Z[11, 12, 13] OE LOW to Output Valid OE LOW to Output Low-Z[11, 12, 13] OE HIGH to Output High-Z [11, 12, 13] 166 MHz Description VDD(Typical) to the first Access[10] Clock Cycle Time Clock HIGH Clock LOW Min. 1 6.0 2.5 2.5 3.5 2.0 0 3.5 3.5 0 3.5 1.5 1.5 1.5 1.5 1.5 Max. 133 MHz Min. 1 7.5 3.0 3.0 4.0 2.0 0 4.0 4.5 0 4.0 1.5 1.5 1.5 1.5 1.5 Max. Unit ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ADSC, ADSP Set-up Before CLK Rise ADV Set-up Before CLK Rise GW, BWE, BW[A : B] Set-up Before CLK Rise Data Input Set-up Before CLK Rise tCES Chip Enable Set-up Before CLK Rise 1.5 1.5 ns Notes: 9. Tested initially and after any design or process change that may affect these parameters. 10. This part has a voltage regulator internally; tpower is the time that the power needs to be supplied above VDD minimum initially before a read or write operation can be initiated. 11. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage. 12. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z prior to Low-Z under the same system conditions. 13. This parameter is sampled and not 100% tested. 14. Timing reference level is 1.5V when VDDQ =3.3V. 15. Test conditions shown in (a) of AC Test Loads unless otherwise noted. Document #: 38-05417 Rev. *A Page 9 of 15 CY7C1298F Switching Characteristics Over the Operating Range (continued)[15] 166 MHz Parameter Hold Times tAH tADH tADVH tWEH tDH tCEH Read Timing[16] tCYC 133 MHz Min. 0.5 0.5 0.5 0.5 0.5 0.5 Max. Unit ns ns ns ns ns ns Description Address Hold After CLK Rise ADSP , ADSC Hold After CLK Rise ADV Hold After CLK Rise GW,BWE, BW[A : B] Hold After CLK Rise Data Input Hold After CLK Rise Chip Enable Hold After CLK Rise Min. 0.5 0.5 0.5 0.5 0.5 0.5 Max. Switching Waveforms CLK tCH tADS tADH tCL ADSP tADS tADH ADSC tAS tAH ADDRESS A1 tWES tWEH A2 A3 Burst continued with new base address GW, BWE,BW [A:B] tCES tCEH Deselect cycle CE tADVS tADVH ADV ADV suspends burst OE tOEV t CLZ t OEHZ t OELZ tCO tDOH t CHZ Data Out (Q) High-Z Q(A1) t CO Q(A2) Q(A2 + 1) Q(A2 + 2) Q(A2 + 3) Q(A2) Q(A2 + 1) Q(A3) Single READ BURST READ Burst wraps around to its initial state DON’T CARE UNDEFINED Note: 16. On this diagram, when CE is LOW, CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH, CE1 is HIGH or CE2 is LOW or CE3 is HIGH. Document #: 38-05417 Rev. *A Page 10 of 15 CY7C1298F Switching Waveforms (continued) Write Timing[16,17] t CYC CLK tCH tADS tADH tCL ADSP tADS tADH ADSC extends burst tADS tADH ADSC tAS tAH ADDRESS A1 A2 Byte write signals are ignored for first cycle when ADSP initiates burst A3 tWES tWEH BWE, BW[A:B] tWES tWEH GW tCES tCEH CE tADVS tADVH ADV ADV suspends burst OE t DS t DH Data in (D) High-Z t OEHZ D(A1) D(A2) D(A2 + 1) D(A2 + 1) D(A2 + 2) D(A2 + 3) D(A3) D(A3 + 1) D(A3 + 2) Data Out (Q) BURST READ Single WRITE BURST WRITE DON’T CARE UNDEFINED Extended BURST WRITE Note: 17. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW[A:B] LOW. Document #: 38-05417 Rev. *A Page 11 of 15 CY7C1298F Switching Waveforms (continued) Read/Write Timing[16,18,19] tCYC CLK tCH tADS tADH tCL ADSP ADSC tAS tAH ADDRESS BWE, BW[A:B] A1 A2 A3 tWES tWEH A4 A5 A6 tCES tCEH CE ADV OE tCO tDS tDH tOELZ Data In (D) Data Out (Q) High-Z tCLZ tOEHZ D(A3) D(A5) D(A6) High-Z Q(A1) Back-to-Back READs Q(A2) Single WRITE DON’T CARE Q(A4) Q(A4+1) BURST READ Q(A4+2) Q(A4+3) Back-to-Back WRITEs UNDEFINED Notes: 18. The data bus (Q) remains in High-Z following a WRITE cycle, unless a new read access initiated by ADSP or ADSP . 19. GW is HIGH. Document #: 38-05417 Rev. *A Page 12 of 15 CY7C1298F Switching Waveforms (continued) ZZ Mode Timing [20,21] CLK t ZZ t ZZREC ZZ t ZZI I SUPPLY I DDZZ t RZZI DESELECT or READ Only ALL INPUTS (except ZZ) Outputs (Q) High-Z DON’T CARE Ordering Information Speed[22] (MHz) 133 Ordering Code CY7C1298F-133AC Package Name A101 Package Type 100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack Operating Range Commercial Shaded areas contain advance information. Please contact your local CYpress sales representative for availability of this part. Please contact your local Cypress Sales representative for availability of 166-MHz speed grade option. Note: 20. Device must be deselected when entering ZZ mode. See truth table for all possible signal conditions to deselect the device. 21. I/Os are in High-Z when exiting ZZ sleep mode. 22. Please contact your local Cypress sales representative for availability of 166-MHz speed grade option Document #: 38-05417 Rev. *A Page 13 of 15 CY7C1298F Package Diagram 100-pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101 51-85050-*A Intel and Pentium are registered trademarks, and i486 is a trademark, of Intel Corporation. PowerPC is a registered trademark of IBM. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05417 Rev. *A Page 14 of 15 © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C1298F Document History Page Document Title: CY7C1298F 1-Mb 64K x 18 Pipelined DCD Sync SRAM Document Number: 38-05417 REV. ** *A ECN NO. 130301 213321 Issue Date 12/30/03 See ECN Orig. of Change NJY VBL New Data Sheet Updated Ordering Info section: shaded part number, added explanation Shaded Selection Guide, Characteristics section Description of Change Document #: 38-05417 Rev. *A Page 15 of 15