PREMILINARY
CY7C1302CV25
9-Mbit Burst of Two Pipelined SRAMs with QDR™ Architecture
Features
• Separate independent Read and Write data ports — Supports concurrent transactions • 167-MHz clock for high bandwidth — 2.5 ns clock-to-Valid access time • 2-word burst on all accesses • Double Data Rate (DDR) interfaces on both Read and Write ports (data transferred at 333 MHz) @ 167 MHz • Two input clocks (K and K) for precise DDR timing — SRAM uses rising edges only • Two output clocks (C and C) account for clock skew and flight time mismatching • Single multiplexed address input bus latches address inputs for both Read and Write ports • Separate Port Selects for depth expansion • Synchronous internally self-timed writes • 2.5V core power supply with HSTL Inputs and Outputs • 13 x 15 x 1.4 mm 1.0-mm pitch fBGA package, 165 ball (11 x 15 matrix) • Variable drive HSTL output buffers • Expanded HSTL output voltage (1.4V–1.9V) • JTAG Interface
Functional Description
The CY7C1302CV25 is a 2.5V Synchronous Pipelined SRAM equipped with QDR™ architecture. QDR architecture consists of two separate ports to access the memory array. The Read port has dedicated data outputs to support Read operations and the Write Port has dedicated data inputs to support Write operations. Access to each port is accomplished through a common address bus. The Read address is latched on the rising edge of the K clock and the Write address is latched on the rising edge of K clock. QDR has separate data inputs and data outputs to completely eliminate the need to “turn-around” the data bus required with common I/O devices. Accesses to the CY7C1302CV25 Read and Write ports are completely independent of one another. All accesses are initiated synchronously on the rising edge of the positive input clock (K). In order to maximize data throughput, both Read and Write ports are equipped with DDR interfaces. Therefore, data can be transferred into the device on every rising edge of both input clocks (K and K) and out of the device on every rising edge of the output clock (C and C, or K and K in a single clock domain) thereby maximizing performance while simplifying system design. Each address location is associated with two 18-bit words that burst sequentially into or out of the device. Depth expansion is accomplished with a Port Select input for each port. Each Port Select allows each port to operate independently. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C (or K or K in a single clock domain) input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry.
Configurations
CY7C1302CV25 – 512K x 18
Logic Block Diagram (CY7C1302CV25)
D[17:0] 18
Write Data Reg
Write Add. Decode
Read Add. Decode
A(17:0)
Address Register 18
Write Data Reg
K K
CLK Gen.
256Kx18 256Kx18 Memory Memory Array Array
Address Register
18
A(17:0)
Control Logic
RPS C C
Read Data Reg. 36 Vref WPS BWS0 BWS1 Control Logic 18 18 Reg. Reg. 18
Reg. 18
18 Q[17:0]
Cypress Semiconductor Corporation Document #: 38-05491 Rev. *A
•
3901 North First Street
•
San Jose, CA 95134
• 408-943-2600 Revised June 1, 2004
PREMILINARY
Selection Guide
CY7C1302CV25 -167 Maximum Operating Frequency Maximum Operating Current 167 750 CY7C1302CV25 -133 133 650
CY7C1302CV25
CY7C1302CV25 -100 100 550
Unit MHz mA
Pin Configuration–CY7C1302CV25 (Top View)
1 A B C D E F G H J K L M N P R NC NC NC NC NC NC NC NC NC NC NC NC NC NC TDO 2 Q9 NC D11 NC Q12 D13 VREF NC NC Q15 NC D17 NC TCK 3 D9 D10 Q10 Q11 D12 Q13 VDDQ D14 Q14 D15 D16 Q16 Q17 A 4 WPS A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 5 BWS1 NC A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 6 K K A VSS VSS VSS VSS VSS VSS VSS VSS VSS A C C 7 NC BWS0 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 8 RPS A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 9 NC NC NC NC NC NC VDDQ NC NC NC NC NC NC A 10 NC Q7 NC D6 NC NC VREF Q4 D3 NC Q1 NC D0 TMS 11 NC Q8 D8 D7 Q6 Q5 D5 ZQ D4 Q3 Q2 D2 D1 Q0 TDI Gnd/144M NC/36M NC/18M Gnd/72M
Pin Definitions
Name D[17:0] WPS I/O InputSynchronous InputSynchronous InputSynchronous Description Data input signals, sampled on the rising edge of K and K clocks during valid Write operations. Write Port Select, active LOW. Sampled on the rising edge of the K clock. When asserted active, a Write operation is initiated. Deasserting will deselect the Write port. Deselecting the Write port will cause D[17:0] to be ignored. Byte Write Select 0, 1, active LOW. Sampled on the rising edge of the K and K clocks during Write operations. Used to select which byte is written into the device during the current portion of the Write operations. Bytes not written remain unaltered. BWS0 controls D[8:0] and BWS1 controls D[17:9]. All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select will cause the corresponding byte of data to be ignored and not written into the device. Address Inputs. Sampled on the rising edge of the K (read address) and K (write address) clocks for active Read and Write operations. These address inputs are multiplexed for both Read and Write operations. Internally, the device is organized as 512K x 18 (2 arrays each of 256K x 18). These inputs are ignored when the appropriate port is deselected. Data Output signals. These pins drive out the requested data during a Read operation. Valid data is driven out on the rising edge of both the C and C clocks during Read operations or K and K when in single clock mode. When the Read port is deselected, Q[17:0] are automatically three-stated. Read Port Select, active LOW. Sampled on the rising edge of positive input clock (K). When active, a Read operation is initiated. Deasserting will cause the Read port to be deselected. When deselected, the pending access is allowed to complete and the output drivers are automatically three-stated following the next rising edge of the C clock. Each read access consists of a burst of two sequential transfers. Positive Output Clock Input. C is used in conjunction with C to clock out the Read data from the device. C and C can be used together to deskew the flight times of various devices on the board back to the controller. See application example for further details. Page 2 of 18
BWS0, BWS1
A
InputSynchronous
Q[17:0]
OutputsSynchronous
RPS
InputSynchronous
C
InputClock
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PREMILINARY
Pin Definitions (continued)
Name C I/O Input-Clock Description
CY7C1302CV25
Negative Output Clock Input. C is used in conjunction with C to clock out the Read data from the device. C and C can be used together to deskew the flight times of various devices on the board cack to the controller. See application example for further details. Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device and to drive out data through Q[17:0] when in single clock mode. All accesses are initiated on the rising edge of K. Negative Input Clock Input. K is used to capture synchronous inputs being presented to the device and to drive out data through Q[17:0] when in single clock mode. Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus impedance. Q[17:0] output impedance is set to 0.2 x RQ, where RQ is a resistor connected between ZQ and ground. Alternately, this pin can be connected directly to VDD, which enables the minimum impedance mode. This pin cannot be connected directly to GND or left unconnected. TDO for JTAG. TCK pin for JTAG. TDI pin for JTAG. TMS pin for JTAG. Address expansion for 18M. This is not connected to the die and so can be tied to any voltage level. Address expansion for 36M. This is not connected to the die and so can be tied to any voltage level. Address expansion for 72M. This must be tied LOW. Address expansion for 144M. This must be tied LOW. Not connected to the die. Can be tied to any voltage level. Reference Voltage Input. Static input used to set the reference level for HSTL inputs and Outputs as well as AC measurement points. Ground for the device.
K
Input-Clock
K ZQ
Input-Clock Input
TDO TCK TDI TMS NC/18M NC/36M GND/72M GND/144M NC VREF VDD VSS VDDQ
Output Input Input Input N/A N/A Input Input N/A InputReference Ground
Power Supply Power supply inputs to the core of the device. Power Supply Power supply inputs for the outputs of the device. All synchronous control (RPS, WPS, BWS[1:0]) inputs pass through input registers controlled by the rising edge of input clocks (K and K). Read Operations The CY7C1302CV25 is organized internally as 2 arrays of 256K x 18. Accesses are completed in a burst of two sequential 18-bit data words. Read operations are initiated by asserting RPS active at the rising edge of the positive input clock (K). The address is latched on the rising edge of the K clock. Following the next K clock rise the corresponding lower order 18-bit word of data is driven onto the Q[17:0] using C as the output timing reference. On the subsequent rising edge of C the higher order data word is driven onto the Q[17:0]. The requested data will be valid 2.5 ns from the rising edge of the output clock (C and C, or K and K when in single clock mode, 167-MHz device). Synchronous internal circuitry will automatically three-state the outputs following the next rising edge of the positive output clock (C). This will allow for a seamless transition between devices without the insertion of wait states in a depth expanded memory.
Introduction
Functional Overview The CY7C1302CV25 is a synchronous pipelined Burst SRAM equipped with both a Read port and a Write port. The Read port is dedicated to Read operations and the Write port is dedicated to Write operations. Data flows into the SRAM through the Write port and out through the Read port. These devices multiplex the address inputs in order to minimize the number of address pins required. By having separate Read and Write ports, the QDR-I completely eliminates the need to “turn-around” the data bus and avoids any possible data contention, thereby simplifying system design. Accesses for both ports are initiated on the rising edge of the Positive Input Clock (K). All synchronous input timing is referenced from the rising edge of the input clocks (K and K) and all output timing is referenced to the output clocks (C and C, or K and K when in single clock mode). All synchronous data inputs (D[17:0]) pass through input registers controlled by the input clocks (K and K). All synchronous data outputs (Q[17:0]) pass through output registers controlled by the rising edge of the output clocks (C and C, or K and K when in single clock mode).
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Write Operations Write operations are initiated by asserting WPS active at the rising edge of the positive input clock (K). On the same K clock rise the data presented to D[17:0] is latched into the lower 18-bit Write Data register provided BWS[1:0] are both asserted active. On the subsequent rising edge of the negative input clock (K), the address is latched and the information presented to D[17:0] is stored into the Write Data register provided BWS[1:0] are both asserted active. The 36 bits of data are then written into the memory array at the specified location. When deselected, the Write port will ignore all inputs after the pending Write operations have been completed. Byte Write Operations Byte Write operations are supported by the CY7C1302CV25. A Write operation is initiated as described in the Write Operation section above. The bytes that are written are determined by BWS0 and BWS1 which are sampled with each set of 18-bit data word. Asserting the appropriate Byte Write Select input during the data portion of a write will allow the data being presented to be latched and written into the device. Deasserting the Byte Write Select input during the data portion of a write will allow the data stored in the device for that byte to remain unaltered. This feature can be used to simplify Read/Modify/Write operations to a Byte Write operation. Single Clock Mode The CY7C1302CV25 can be used with a single clock mode. In this mode the device will recognize only the pair of input clocks (K and K) that control both the input and output registers. This operation is identical to the operation if the device had zero skew between the K/K and C/C clocks. All timing parameters remain the same in this mode. To use this mode of operation, the user must tie C and C HIGH at
CY7C1302CV25
power-up.This function is a strap option and not alterable during device operation. Concurrent Transactions The Read and Write ports on the CY7C1302CV25 operate completely independently of one another. Since each port latches the address inputs on different clock edges, the user can Read or Write to any location, regardless of the transaction on the other port. Also, reads and writes can be started in the same clock cycle. If the ports access the same location at the same time, the SRAM will deliver the most recent information associated with the specified address location. This includes forwarding data from a Write cycle that was initiated on the previous K clock rise. Depth Expansion The CY7C1302CV25 has a Port Select input for each port. This allows for easy depth expansion. Both Port Selects are sampled on the rising edge of the Positive Input Clock only (K). Each port select input can deselect the specified port. Deselecting a port will not affect the other port. All pending transactions (Read and Write) will be completed prior to the device being deselected. Programmable Impedance An external resistor, RQ, must be connected between the ZQ pin on the SRAM and VSS to allow the SRAM to adjust its output driver impedance. The value of RQ must be 5X the value of the intended line impedance driven by the SRAM, The allowable range of RQ to guarantee impedance matching with a tolerance of ±15% is between 175Ω and 350Ω, with VDDQ =1.5V. The output impedance is adjusted every 1024 cycles to account for drifts in supply voltage and temperature.
Application Example[1]
Note: 1. The above application shows 4 QDR-I being used.
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Truth Table[2, 3, 4, 5, 6, 7]
Operation Write Cycle: Load address on the rising edge of K clock; input write data on K and K rising edges. Read Cycle: Load address on the rising edge of K clock; wait one cycle; read data on 2 consecutive C and C rising edges. NOP: No Operation Standby: Clock Stopped K L-H RPS X WPS L
CY7C1302CV25
DQ D(A+0)at K(t) ↑ Q(A+0) at C(t+1)↑ D=X Q = High-Z Previous State
DQ D(A+1) at K(t) ↑ Q(A+1) at C(t+1) ↑ D=X Q = High-Z Previous State
L-H
L
X
L-H Stopped
H X
H X
Write Cycle Descriptions[2,8]
BWS0 L L L L H H H H BWS1 L L H H L L H H K L-H – L-H – L-H – L-H – K – L-H – L-H – L-H – L-H Comments During the Data portion of a Write sequence, both bytes (D[17:0]) are written into the device. During the Data portion of a Write sequence, both bytes (D[17:0]) are written into the device. During the Data portion of a Write sequence, only the lower byte (D[8:0]) is written into the device. D[17:9] remains unaltered. During the Data portion of a Write sequence, only the lower byte (D[8:0]) is written into the device. D[17:9] remains unaltered. During the Data portion of a Write sequence, only the byte (D[17:9]) is written into the device. D[8:0] remains unaltered. During the Data portion of a Write sequence, only the byte (D[17:9]) is written into the device. D[8:0] remains unaltered. No data is written into the device during this portion of a Write operation. No data is written into the device during this portion of a Write operation.
Notes: 2. X = Don't Care, H = Logic HIGH, L = Logic LOW, ↑ represents rising edge. 3. Device will power-up deselected and the outputs in a three-state condition. 4. “A” represents address location latched by the devices when transaction was initiated. A+0, A+1 represent the addresses sequence in the burst. 5. “t” represents the cycle at which a Read/Write operation is started. t+1 is the first clock cycle succeeding the “t” clock cycle. 6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode. 7. It is recommended that K = K and C = C when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically. 8. Assumes a Write cycle was initiated per the Write Port Cycle Description Truth Table. BWS0, BWS1 can be altered on different portions of a Write cycle, as long as the set-up and hold requirements are achieved.
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Maximum Ratings
(Above which the useful life may be impaired.) Storage Temperature .................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage on VDD Relative to GND........ –0.5V to +3.6V DC Applied to Outputs in High-Z......... –0.5V to VDDQ + 0.5V DC Input Voltage[9 .............................. –0.5V to VDDQ + 0.5V Current into Outputs (LOW) .........................................20 mA
CY7C1302CV25
Static Discharge Voltage........................................... >2001V (per MIL-STD-883, Method 3015) Latch-up Current..................................................... >200 mA
Operating Range
Range Com’l Ambient Temperature (TA) 0°C to +70°C VDD[10] 2.5 ± 0.1V VDDQ[10] 1.4V to 1.9V
Electrical Characteristics Over the Operating Range[11]
DC Electrical Characteristics Over the Operating Range Parameter VDD VDDQ VOH VOL VOH(LOW) VOL(LOW) VIH VIL VIN IX IOZ VREF IDD Description Power Supply Voltage I/O Supply Voltage Output HIGH Voltage Output LOW Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage[9] Input LOW Voltage[9, 14] Clock Input Voltage Input Load Current Output Leakage Current Input Reference Voltage[15] VDD Operating Supply GND ≤ VI ≤ VDDQ GND ≤ VI ≤ VDDQ, Output Disabled Typical value = 0.75V VDD = Max., IOUT = 0 mA, f = fMAX = 1/tCYC 167 MHz 133 MHz 100 MHz Note 12 Note 13 IOH = –0.1 mA, Nominal Impedance IOL = 0.1 mA, Nominal Impedance Test Conditions Min. 2.4 1.4 VDDQ/2 – 0.12 VDDQ/2 – 0.12 VDDQ – 0.2 VSS VREF + 0.1 –0.3 –0.3 –5 –5 0.68 0.75 Typ. 2.5 1.5 Max. 2.6 1.9 VDDQ/2 + 0.12 VDDQ/2 + 0.12 VDDQ 0.2 VDDQ + 0.3 VREF –0.1 VDDQ+0.3 5 5 0.95 750 650 550 470 450 430 Unit V V V V V V V V V µA µA V mA mA mA mA mA mA
ISB1
Automatic Power-Down Current
167 MHz Max. VDD, Both Ports Deselected, VIN ≥ VIH or 133 MHz VIN ≤ VIL, f = 100 MHz fMAX = 1/tCYC, Inputs Static Test Conditions Min. VREF + 0.2 – Typ.
AC Input Requirements Over the Operating Range Parameter VIH VIL Description Input High (Logic 1) Voltage Input Low (Logic 0) Voltage Max. – VREF – 0.2 Unit V V
Notes: 9. Overshoot: VIH(AC) < VDDQ +0.85V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > –1.5V (Pulse width less than tCYC/2). 10. Power-up: Assumes a linear ramp from 0V to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD. 11. All voltage referenced to Ground. 12. Output are impedance controlled. IOH = –(VDDQ/2)/(RQ/5) for values of 175Ω
