CY7C1305AV25

PRELIMINARY CY7C1305AV25 CY7C1307AV25 18-Mbit Burst of 4 Pipelined SRAM with QDR™ Architecture Features • Separate independent Read and Write data ports • Supports concurrent transactions • 167-MHz clock for high bandwidth • 2.5 ns Clock-to-Valid access time • 4-Word Burst for reducing the address bus frequency • Double Data Rate (DDR) interfaces on both Read and Write Ports (data transferred at 333 MHz) @167 MHz • Two input clocks (K and K) for precise DDR timing • SRAM uses rising edges only • Two output clocks (C and C) accounts for clock skew and flight time mismatching • Single multiplexed address input bus latches address inputs for both Read and Write ports • Separate Port Selects for depth expansion • Synchronous internally self-timed writes • 2.5V core power supply with HSTL Inputs and Outputs • 13 x 15 x 1.4 mm 1.0-mm pitch fBGA package, 165 ball (11x15 matrix) • Variable drive HSTL output buffers • Expanded HSTL output voltage (1.4V–1.9V) • JTAG interface Functional Description The CY7C1305AV25/CY7C1307AV25 are 2.5V Synchronous Pipelined SRAMs equipped with QDR architecture. QDR architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to support Read operations and the Write Port has dedicated Data Inputs to support Write operations. QDR architecture has separate data inputs and data outputs to completely eliminate the need to “turn-around” the data bus required with common I/O devices. Access to each port is accomplished through a common address bus. Addresses for Read and Write addresses are latched on alternate rising edges of the input (K) clock. Accesses to the device’s Read and Write ports are completely independent of one another. In order to maximize data throughput, both Read and Write ports are equipped with Double Data Rate (DDR) interfaces. Each address location is associated with four 18-bit words (CY7C1305AV25) and four 36-bit words (CY7C1307AV25) that burst sequentially into or out of the device. Since data can be transferred into and out of the device on every rising edge of both input clocks (K/K and C/C) memory bandwidth is maximized while simplifying system design by eliminating bus “turn-arounds.” Depth expansion is accomplished with Port Selects for each port. Port selects allow each port to operate independently. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry. Configurations • CY7C1305AV25 – 1M x 18 • CY7C1307AV25 – 512K x 36 Logic Block Diagram (CY7C1305AV25) D[17:0] 18 Write Write Write Write Reg Reg Reg Reg Read Add. Decode Write Add. Decode A[17:0] Address Register 18 Address Register 256Kx18 Array 256Kx18 Array 256Kx18 Array 256Kx18 Array 18 A(17:0) K K CLK Gen. Control Logic RPS C C Read Data Reg. Vref WPS BWS[0:1] 72 Control Logic 36 36 Reg. Reg. 18 Reg. 18 Q[17:0] Cypress Semiconductor Corporation Document #: 38-05496 Rev. *A • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised June 1, 2004 PRELIMINARY Logic Block Diagram (CY7C1307AV25) D[35:0] 36 Write Write Write Write Reg Reg Reg Reg CY7C1305AV25 CY7C1307AV25 Read Add. Decode Write Add. Decode A(16:0) Address Register 17 Address Register 128K x 36 Array 128K x 36 Array 128K x 36 Array 128K x 36 Array 17 A(16:0) K K CLK Gen. Control Logic RPS C C Read Data Reg. Vref WPS BWS[0:3] 144 Control Logic 72 72 Reg. Reg. 36 Reg. 36 Q[35:0] Selection Guide CY7C1305AV25-167 CY7C1307AV25-167 Maximum Operating Frequency Maximum Operating Current 167 650 CY7C1305AV25-133 CY7C1307AV25-133 133 620 CY7C1305AV25-100 CY7C1307AV25-100 100 590 Unit MHz mA Document #: 38-05496 Rev. *A Page 2 of 21 PRELIMINARY \ CY7C1305AV25 CY7C1307AV25 Pin Configuration–CY7C1305AV25 (Top View) 1 A B C D E F G H J K L M N P R NC NC NC NC NC NC NC NC NC NC NC NC NC NC TDO 2 GND/ 144M Q9 NC D11 NC Q12 D13 VREF NC NC Q15 NC D17 NC TCK 3 NC/ 36M D9 D10 Q10 Q11 D12 Q13 VDDQ D14 Q14 D15 D16 Q16 Q17 A 4 WPS A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 5 BWS1 NC A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 6 K K NC VSS VSS VSS VSS VSS VSS VSS VSS VSS A C C 7 NC BWS0 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 8 RPS A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 9 A NC NC NC NC NC NC VDDQ NC NC NC NC NC NC A 10 GND/ 72M NC Q7 NC D6 NC NC VREF Q4 D3 NC Q1 NC D0 TMS 11 NC Q8 D8 D7 Q6 Q5 D5 ZQ D4 Q3 Q2 D2 D1 Q0 TDI Pin Configuration–CY7C1307AV25 (Top View) 1 A B C D E F G H J K L M N P R NC Q27 D27 D28 Q29 Q30 D30 NC D31 Q32 Q33 D33 D34 Q35 TDO 2 GND/ 288M Q18 Q28 D20 D29 Q21 D22 VREF Q31 D32 Q24 Q34 D26 D35 TCK 3 NC/ 72M D18 D19 Q19 Q20 D21 Q22 VDDQ D23 Q23 D24 D25 Q25 Q26 A 4 WPS A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 5 BWS2 BWS3 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 6 K K NC VSS VSS VSS VSS VSS VSS VSS VSS VSS A C C 7 BWS1 BWS0 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 8 RPS A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 9 NC/ 36M D17 D16 Q16 Q15 D14 Q13 VDDQ D12 Q12 D11 D10 Q10 Q9 A 10 GND/ 144M Q17 Q7 D15 D6 Q14 D13 VREF Q4 D3 Q11 Q1 D9 D0 TMS 11 NC Q8 D8 D7 Q6 Q5 D5 ZQ D4 Q3 Q2 D2 D1 Q0 TDI Document #: 38-05496 Rev. *A Page 3 of 21 PRELIMINARY Pin Definitions Name D[x:0] I/O InputSynchronous Description CY7C1305AV25 CY7C1307AV25 Data input signals, sampled on the rising edge of K and K clocks during valid write operations. CY7C1305AV25 – D[17:0] CY7C1307AV25 – D[35:0] Write Port Select, active LOW. Sampled on the rising edge of the K clock. When asserted active, a Write operation is initiated. Deasserting will deselect the Write port. Deselecting the Write port will cause D[x:0] to be ignored. Byte Write Select 0, 1, 2, and 3–active LOW. Sampled on the rising edge of the K and K clocks during Write operations. Used to select which byte is written into the device during the current portion of the Write operations. Bytes not written remain unaltered. CY7C1305AV25 - BWS0 controls D[8:0] and BWS1 controls D[17:9]. CY7C1307AV25 - BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18] and BWS3 controls D[35:27] All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select will cause the corresponding byte of data to be ignored and not written into the device. Address Inputs. Sampled on the rising edge of the K clock during active Read and Write operations. These address inputs are multiplexed for both Read and Write operations. Internally, the device is organized as 1M x 18 (4 arrays each of 256K x 18) for CY7C1305AV25 and 512K x 36 (4 arrays each of 128K x 36) for CY7C1307AV25. Therefore, only 18 address inputs for CY7C1305AV25 and 17 address inputs for CY7C1307AV25. These inputs are ignored when the appropriate port is deselected. Data Output signals. These pins drive out the requested data during a Read operation. Valid data is driven out on the rising edge of both the C and C clocks during Read operations or K and K when in single clock mode. When the Read port is deselected, Q[x:0] are automatically three-stated. CY7C1305AV25 - Q[17:0] CY7C1307AV25 - Q[35:0] Read Port Select, active LOW. Sampled on the rising edge of Positive Input Clock (K). When active, a Read operation is initiated. Deasserting will cause the Read port to be deselected. When deselected, the pending access is allowed to complete and the output drivers are automatically three-stated following the next rising edge of the C clock. Each read access consists of a burst of four sequential 18-bit or 36-bit transfers. Positive Output Clock Input. C is used in conjunction with C to clock out the Read data from the device. C and C can be used together to deskew the flight times of various devices on the board back to the controller. See application example for further details. Negative Output Clock Input. C is used in conjunction with C to clock out the Read data from the device. C and C can be used together to deskew the flight times of various devices on the board cack to the controller. See application example for further details. Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device and to drive out data through Q[x:0] when in single clock mode. All accesses are initiated on the rising edge of K. Negative Input Clock Input. K is used to capture synchronous inputs to the device and to drive out data through Q[x:0] when in single clock mode. Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus impedance. Q[x:0] output impedance are set to 0.2 x RQ, where RQ is a resistor connected between ZQ and ground. Alternately, this pin can be connected directly to VDD, which enables the minimum impedance mode. This pin cannot be connected directly to VSS or left unconnected. TDO pin for JTAG TCK pin for JTAG TDI pin for JTAG TMS pin for JTAG WPS InputSynchronous InputSynchronous BWS0, BWS1, BWS2, BWS3 A InputSynchronous Q[x:0] OutputsSynchronous RPS InputSynchronous C Input-Clock C Input-Clock K Input-Clock K ZQ Input-Clock Input TDO TCK TDI TMS Output Input Input Input Document #: 38-05496 Rev. *A Page 4 of 21 PRELIMINARY Pin Definitions (continued) Name NC/36M GND/72M NC/72M GND/144M GND/288M VREF VDD VSS VDDQ NC I/O N/A Input N/A Input Input InputReference Power Supply Ground Power Supply N/A Description CY7C1305AV25 CY7C1307AV25 Address expansion for 36M. This is not connected to the die. Can be connected to any voltage level on CY7C1305AV25/CY7C1307AV25. Address expansion for 72M. This should be tied LOW on the CY7C1305AV25. Address expansion for 72M. This can be connected to any voltage level on CY7C1307AV25. Address expansion for 144M. This should be tied LOW on CY7C1305AV25/CY7C1307AV25. Address expansion for 144M. This should be tied LOW on CY7C1307AV25. Reference Voltage Input. Static input used to set the reference level for HSTL inputs and Outputs as well as AC measurement points. Power supply inputs to the core of the device Ground for the device Power supply inputs for the outputs of the device Not connected to the die. Can be tied to any voltage level. onto the Q[17:0] using C as the output timing reference. On the subsequent rising edge of C the next 18-bit data word is driven onto the Q[17:0]. This process continues until all four 18-bit data words have been driven out onto Q[17:0]. The requested data will be valid 2.5 ns from the rising edge of the output clock (C and C, or K and K when in single clock mode, 167-MHz device). In order to maintain the internal logic, each Read access must be allowed to complete. Each Read access consists of four 18-bit data words and takes 2 clock cycles to complete. Therefore, Read accesses to the device can not be initiated on two consecutive K clock rises. The internal logic of the device will ignore the second Read request. Read accesses can be initiated on every other K clock rise. Doing so will pipeline the data flow such that data is transferred out of the device on every rising edge of the output clocks (C and C, or K and K when in single clock mode). When the read port is deselected, the CY7C1305AV25 will first complete the pending read transactions. Synchronous internal circuitry will automatically three-state the outputs following the next rising edge of the positive output clock (C). This will allow for a seamless transition between devices without the insertion of wait states in a depth expanded memory. Write Operations Write operations are initiated by asserting WPS active at the rising edge of the positive input clock (K). On the following K clock rise the data presented to D[17:0] is latched and stored into the lower 18-bit Write Data register provided BWS[1:0] are both asserted active. On the subsequent rising edge of the negative input clock (K) the information presented to D[17:0] is also stored into the Write Data Register provided BWS[1:0] are both asserted active. This process continues for one more cycle until four 18-bit words (a total of 72 bits) of data are stored in the SRAM. The 72 bits of data are then written into the memory array at the specified location. Therefore, Write accesses to the device can not be initiated on two consecutive K clock rises. The internal logic of the device will ignore the second Write request. Write accesses can be initiated on every other rising edge of the positive clock (K). Doing so will pipeline the data flow such that 18-bits of data can be transferred into the device on every rising edge of the input clocks (K and K). Page 5 of 21 Introduction Functional Overview The CY7C1305AV25/CY7C1307AV25 are synchronous pipelined Burst SRAMs equipped with both a Read port and a Write port. The Read port is dedicated to Read operations and the Write Port is dedicated to Write operations. Data flows into the SRAM through the Write port and out through the Read port. These devices multiplex the address inputs in order to minimize the number of address pins required. By having separate Read and Write ports, the device completely eliminates the need to “turn-around” the data bus and avoids any possible data contention, thereby simplifying system design. Each access consists of four 18-bit data transfers in the case of CY7C1305AV25 and four 36-bit data transfers in the case of CY7C1307AV25, in two clock cycles. Accesses for both ports are initiated on the rising edge of the positive input clock (K). All synchronous input timing is referenced from the rising edge of the input clocks (K and K) and all output timing is referenced to the rising edge of output clocks (C and C, or K and K when in single clock mode). All synchronous data inputs (D[x:0]) pass through input registers controlled by the rising edge of input clocks (K and K). All synchronous data outputs (Q[x:0]) pass through output registers controlled by the rising edge of the output clocks (C and C, or K and K when in single clock mode). All synchronous control (RPS, WPS, BWS[0:x]) inputs pass through input registers controlled by the rising edge of input clocks (K and K). CY7C1305AV25 is described in the following sections. The same basic descriptions apply to CY7C1307AV25. Read Operations The CY7C1305AV25 is organized internally as 4 arrays of 256K x 18. Accesses are completed in a burst of four sequential 18-bit data words. Read operations are initiated by asserting RPS active at the rising edge of the Positive Input Clock (K). The address presented to Address inputs are stored in the Read address register. Following the next K clock rise the corresponding lowest order 18-bit word of data is driven Document #: 38-05496 Rev. *A PRELIMINARY When deselected, the write port will ignore all inputs after the pending Write operations have been completed. Byte Write Operations Byte Write operations are supported by the CY7C1305AV25. A write operation is initiated as described in the Write Operation section above. The bytes that are written are determined by BWS0 and BWS1, which are sampled with each set of 18-bit data word. Asserting the appropriate Byte Write Select input during the data portion of a write will allow the data being presented to be latched and written into the device. Deasserting the Byte Write Select input during the data portion of a write will allow the data stored in the device for that byte to remain unaltered. This feature can be used to simplify Read/Modify/Write operations to a Byte Write operation. Single Clock Mode The CY7C1305AV25 can be used with a single clock that controls both the input and output registers. In this mode the device will recognize only a single pair of input clocks (K and K) that control both the input and output registers. This operation is identical to the operation if the device had zero skew between the K/K and C/C clocks. All timing parameters remain the same in this mode. To use this mode of operation, the user must tie C and C HIGH at power-on. This function is a strap option and not alterable during device operation. Concurrent Transactions The Read and Write ports on the CY7C1305AV25 operate completely independently of one another. Since each port latches the address inputs on different clock edges, the user can Read or Write to any location, regardless of the transaction on the other port. If the ports access the same location at the same time, the SRAM will deliver the most recent information associated with the specified address location. This CY7C1305AV25 CY7C1307AV25 includes forwarding data from a Write cycle that was initiated on the previous K clock rise. Read and Write accesses must be scheduled such that one transaction is initiated on any clock cycle. If both ports are selected on the same K clock rise, the arbitration depends on the previous state of the SRAM. If both ports were deselected, the Read port will take priority. If a Read was initiated on the previous cycle, the Write port will assume priority (since Read operations can not be initiated on consecutive cycles). If a Write was initiated on the previous cycle, the Read port will assume priority (since Write operations can not be initiated on consecutive cycles). Therefore, asserting both port selects active from a deselected state will result in alternating Read/Write operations being initiated, with the first access being a Read. Depth Expansion The CY7C1305AV25 has a Port Select input for each port. This allows for easy depth expansion. Both Port Selects are sampled on the rising edge of the positive input clock only (K). Each port select input can deselect the specified port. Deselecting a port will not affect the other port. All pending transactions (Read and Write) will be completed prior to the device being deselected. Programmable Impedance An external resistor, RQ, must be connected between the ZQ pin on the SRAM and VSS to allow the SRAM to adjust its output driver impedance. The value of RQ must be 5X the value of the intended line impedance driven by the SRAM, The allowable range of RQ to guarantee impedance matching with a tolerance of ±15% is between 175Ω and 350Ω, with VDDQ=1.5V. The output impedance is adjusted every 1024 cycles upon power-up to account for drifts in supply voltage and temperature. Application Example[1] Note: 1. The above application shows four QDR-I being used. Document #: 38-05496 Rev. *A Page 6 of 21 PRELIMINARY Truth Table[2, 3, 4, 5, 6, 7, 8, 9] Operation Write Cycle: Load address on the rising edge of K; wait one cycle; input write data on two consecutive K and K rising edges. Read Cycle: Load address on the rising edge of K; wait one cycle; read data on two consecutive C and C rising edges. NOP: No operation Standby: Clock stopped K L-H RPS H[8] WPS L [9] CY7C1305AV25 CY7C1307AV25 DQ D(A+00)at K(t+1) ↑ DQ D(A+01) at K(t+1) ↑ DQ D(A+10) at K(t+2) ↑ DQ D(A+11) at K(t+2) ↑ L-H L[9] X Q(A+00) at C(t+1) ↑ Q(A+01) at C(t+1) ↑ Q(A+10) at C(t+2) ↑ Q(A+11) at C(t+2) ↑ L-H Stopped H X H X D=X Q = High-Z D=X Q = High-Z D=X Q = High-Z D=X Q = High-Z Previous state Previous state Previous state Previous state Write Cycle Descriptions (CY7C1305AV25)[2, 10] BWS0 L L L L H H H H BWS1 L L H H L L H H K L-H – L-H – L-H – L-H – K – L-H – L-H – L-H – L-H Comments During the Data portion of a Write sequence, both bytes (D[17:0]) are written into the device. During the Data portion of a Write sequence, both bytes (D[17:0]) are written into the device. During the Data portion of a Write sequence, only the lower byte (D[8:0]) is written into the device. D[17:9] will remain unaltered. During the Data portion of a Write sequence, only the lower byte (D[8:0]) is written into the device. D[17:9] will remain unaltered. During the Data portion of a Write sequence, only the upper byte (D[17:9]) is written into the device. D[8:0] will remain unaltered. During the Data portion of a Write sequence, only the upper byte (D[17:9]) is written into the device. D[8:0] will remain unaltered. No data is written into the device during this portion of a Write operation. No data is written into the device during this portion of a Write operation. Notes: 2. X = Don't Care, H = Logic HIGH, L = Logic LOW, ↑represents rising edge. 3. Device will power-up deselected and the outputs in a three-state condition. 4. “A” represents address location latched by the devices when transaction was initiated. A+00, A+01, A+10 and A+11 represents the address sequence in the burst. 5. “t” represents the cycle at which a read/write operation is started. t+1 and t+2 are the first and second clock cycles respectively succeeding the “t” clock cycle. 6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode. 7. It is recommended that K = K and C = C when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically. 8. If this signal was LOW to initiate the previous cycle, this signal becomes a don’t care for this operation. 9. This signal was HIGH on previous K clock rise. Initiating consecutive Read or Write operations on consecutive K clock rises is not permitted. The device will ignore the second Read request. Document #: 38-05496 Rev. *A Page 7 of 21 PRELIMINARY Write Cycle Descriptions (CY7C1307AV25)[2, 10] BWS0 L L L BWS1 L L H BWS2 L L H BWS3 L L H K L-H – L-H K – L-H – CY7C1305AV25 CY7C1307AV25 Comments During the Data portion of a Write sequence, all four bytes (D[35:0]) are written into the device. During the Data portion of a Write sequence, all four bytes (D[35:0]) are written into the device. During the Data portion of a Write sequence, only the lower byte (D[8:0]) is written into the device. D[35:9] will remain unaltered. During the Data portion of a Write sequence, only the lower byte (D[8:0]) is written into the device. D[35:9] will remain unaltered. During the Data portion of a Write sequence, only the byte (D[17:9]) is written into the device. D[8:0] and D[35:18] will remain unaltered. During the Data portion of a Write sequence, only the byte (D[17:9]) is written into the device. D[8:0] and D[35:18] will remain unaltered. During the Data portion of a Write sequence, only the byte (D[26:18]) is written into the device. D[17:0] and D[35:27] will remain unaltered. During the Data portion of a Write sequence, only the byte (D[26:18]) is written into the device. D[17:0] and D[35:27] will remain unaltered. During the Data portion of a Write sequence, only the byte (D[35:27]) is written into the device. D[26:0] will remain unaltered. L H H H – L-H H L H H L-H – H L H H – L-H H H L H L-H – H H L H – L-H H H H L L-H H H H L – L-H During the Data portion of a Write sequence, only the byte (D[35:27]) is written into the device. D[26:0] will remain unaltered. No data is written into the device during this portion of a Write operation. No data is written into the device during this portion of a write operation. H H H H H H H H L-H – – L-H Note: 10. Assumes a Write cycle was initiated per the Write Port Cycle Description Truth Table. BWS0 and BWS1 in the case of CY7C1305AV25 and BWS2 and BWS3 in the case of CY7C1307AV25 can be altered on different portions of a Write cycle, as long as the set-up and hold requirements are achieved. Document #: 38-05496 Rev. *A Page 8 of 21 PRELIMINARY Maximum Ratings (Above which the useful life may be impaired.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage on VDD Relative to GND........ –0.5V to +3.6V DC Applied to Outputs in High-Z State –0.5V to VDDQ + 0.5V DC Input Voltage[11] ............................ –0.5V to VDDQ + 0.5V CY7C1305AV25 CY7C1307AV25 Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-Up Current ................................................... > 200 mA Operating Range Range Com’l Ambient Temperature (TA) 0°C to +70°C VDD[12] 2.5 ± 0.1V VDDQ[12] 1.4V to 1.9V Electrical Characteristics Over the Operating Range[13] DC Electrical Characteristics Over the Operating Range Parameter VDD VDDQ VOH VOL VOH(LOW) VOL(LOW) VIH VIL VIN IX IOZ VREF IDD Description Power Supply Voltage I/O Supply Voltage Output HIGH Voltage Output LOW Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage[11] Input LOW Voltage[11, 16] GND ≤ VI ≤ VDDQ GND ≤ VI ≤ VDDQ, Output Disabled VDD = Max., IOUT = 0 mA, f = fMAX = 1/tCYC 167 MHz 133 MHz 100 MHz Clock Input Voltage Input Load Current Output Leakage Current VDD Operating Supply Note 14 Note 15 IOH = –0.1 mA, Nominal Impedance IOH = 0.1 mA, Nominal Impedance Test Conditions Min. 2.4 1.4 VDDQ/2 – 0.12 VDDQ/2 – 0.12 VDDQ – 0.2 VSS VREF + 0.1 –0.3 –0.3 –5 –5 0.68 0.75 Typ. 2.5 1.5 Max. 2.6 1.9 VDDQ/2 + 0.12 VDDQ/2 + 0.12 VDDQ 0.2 VDDQ + 0.3 VREF – 0.1 VDDQ + 0.3 5 5 0.95 650 620 590 420 400 380 Min. VREF + 0.2 – Typ. – – Max. – VREF – 0.2 Unit V V V V V V V V V µA µA V mA mA mA mA mA mA Unit V V Input Reference Voltage[17] Typical value = 0.75V ISB1 Automatic Power-Down Current Max. VDD, Both Ports 167 MHz Deselected, 133 MHz VIN ≤ VIH or VIN < VIL f = fMAX = 1/tCYC, Inputs Static 100 MHz AC Input Requirements Over the Operating Range Test Conditions Parameter VIH VIL Description Input High (Logic 1) Voltage Input Low (Logic 0) Voltage Thermal Resistance[18] Parameter ΘJA ΘJC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51. 165 FBGA Package 16.7 2.5 Unit °C/W °C/W Notes: 11. Overshoot: VIH(AC) < VDDQ +0.85V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > –1.5V (Pulse width less than tCYC/2). 12. Power-up: Assumes a linear ramp from 0V to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD. 13. All Voltage referenced to Ground. 14. Output are impedance controlled. IOH = –(VDDQ/2)/(RQ/5) for values of 175Ω