CY7C1306CV25-167BZC

PRELIMINARY CY7C1303CV25 CY7C1306CV25 18-Mbit Burst of 2 Pipelined SRAM with QDR™ Architecture Features ■ Functional Description The CY7C1303CV25 and CY7C1306CV25 are 2.5V Synchronous Pipelined SRAMs, equipped with QDR™ architecture. QDR architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has data outputs to support read operations and the write port has data inputs to support write operations. QDR architecture has separate data inputs and data outputs to completely eliminate the need to “turn-around” the data bus required with common I/O devices. Access to each port is accomplished through a common address bus. The read address is latched on the rising edge of the K clock and the write address is latched on the rising edge of the K clock. Accesses to the QDR read and write ports are completely independent of one another. All accesses are initiated synchronously on the rising edge of the positive input clock (K). To maximize data throughput, both read and write ports are provided with DDR interfaces. Therefore, data can be transferred into the device on every rising edge of both input clocks (K and K) and out of the device on every rising edge of the output clock (C and C, or K and K when in single clock mode) thereby maximizing performance while simplifying system design. Each address location is associated with two 18-bit words (CY7C1303CV25), or 36-bit words (CY7C1306CV25) that burst sequentially into or out of the device. Depth expansion is accomplished with port selects, which enables each port to operate independently. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C (or K/K in a single clock domain) input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry. Separate independent read and write data ports ❐ Supports concurrent transactions 167 MHz clock for high bandwidth ❐ 2.5 ns Clock-to-Valid access time 2-word burst on all accesses Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 333 MHz) at 167 MHz Two input clocks (K and K) for precise DDR timing ❐ SRAM uses rising edges only Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches Single multiplexed address input bus latches address inputs for both read and write ports Separate port selects for depth expansion Synchronous internally self-timed writes 2.5V core power supply with HSTL inputs and outputs Available in 165-Ball FBGA package (13 x 15 x 1.4 mm) Variable drive HSTL output buffers Expanded HSTL output voltage (1.4V–1.9V) JTAG interface Variable Impedance HSTL ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Configurations CY7C1303CV25 – 1M x 18 CY7C1306CV25 – 512K x 36 Selection Guide Description Maximum Operating Frequency Maximum Operating Current 167 MHz 167 500 Unit MHz mA Cypress Semiconductor Corporation Document #: 001-44701 Rev. *B • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised July 31, 2009 [+] Feedback PRELIMINARY Logic Block Diagram (CY7C1303CV25) CY7C1303CV25 CY7C1306CV25 D[17:0] 18 Write Reg Write Reg Read Add. Decode Write Add. Decode A(18:0) 19 Address Register Address Register 19 A(18:0) 512K x 18 Array 512K x 18 Array K K CLK Gen. RPS Control Logic C C Read Data Reg. 36 VREF WPS BWS[1:0] Control Logic 18 18 Reg. Reg. Reg. 18 18 18 Q[17:0] Logic Block Diagram (CY7C1306CV25) D[35:0] 36 Write Reg Write Reg Read Add. Decode Write Add. Decode A(17:0) 18 Address Register Address Register 18 A(17:0) 256K x 36 Array 256K x 36 Array K K CLK Gen. RPS Control Logic C C Read Data Reg. 72 VREF WPS BWS[3:0] Control Logic 36 36 Reg. Reg. Reg. 36 36 36 Q[35:0] Document #: 001-44701 Rev. *B Page 2 of 21 [+] Feedback PRELIMINARY Pin Configuration The pin configurations for CY7C1303CV25 and CY7C1306CV25 follow. CY7C1303CV25 CY7C1306CV25 165-Ball FBGA (13 x 15 x 1.4 mm) Pinout CY7C1303CV25 (1M x 18) 1 A B C D E F G H J K L M N P R NC NC NC NC NC NC NC NC NC NC NC NC NC NC TDO 2 GND/144M 3 NC/36M D9 D10 Q10 Q11 D12 Q13 VDDQ D14 Q14 D15 D16 Q16 Q17 A 4 WPS A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 5 BWS1 NC A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 6 K K A VSS VSS VSS VSS VSS VSS VSS VSS VSS A C C 7 NC BWS0 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 8 RPS A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 9 A NC NC NC NC NC NC VDDQ NC NC NC NC NC NC A 10 GND/72M 11 NC Q8 D8 D7 Q6 Q5 D5 ZQ D4 Q3 Q2 D2 D1 Q0 TDI Q9 NC D11 NC Q12 D13 VREF NC NC Q15 NC D17 NC TCK NC Q7 NC D6 NC NC VREF Q4 D3 NC Q1 NC D0 TMS CY7C1306CV25 (512K x 36) 1 A B C D E F G H J K L M N P R NC Q27 D27 D28 Q29 Q30 D30 NC D31 Q32 Q33 D33 D34 Q35 TDO 2 GND/288M 3 NC/72M D18 D19 Q19 Q20 D21 Q22 VDDQ D23 Q23 D24 D25 Q25 Q26 A 4 WPS A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 5 BWS2 BWS3 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 6 K K A VSS VSS VSS VSS VSS VSS VSS VSS VSS A C C 7 BWS1 BWS0 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 8 RPS A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 9 NC/36M D17 D16 Q16 Q15 D14 Q13 VDDQ D12 Q12 D11 D10 Q10 Q9 A 10 GND/144M 11 NC Q8 D8 D7 Q6 Q5 D5 ZQ D4 Q3 Q2 D2 D1 Q0 TDI Q18 Q28 D20 D29 Q21 D22 VREF Q31 D32 Q24 Q34 D26 D35 TCK Q17 Q7 D15 D6 Q14 D13 VREF Q4 D3 Q11 Q1 D9 D0 TMS Document #: 001-44701 Rev. *B Page 3 of 21 [+] Feedback PRELIMINARY Pin Definitions Pin Name D[x:0] I/O Pin Description CY7C1303CV25 CY7C1306CV25 InputData Input Signals. Sampled on the rising edge of K and K clocks during valid write operations. Synchronous CY7C1303CV25 - D[17:0] CY7C1306CV25 - D[35:0] InputWrite Port Select − Active LOW. Sampled on the rising edge of the K clock. When asserted active, a Synchronous write operation is initiated. Deasserting deselects the write port. Deselecting the write port ignores D[x:0]. InputByte Write Select 0, 1, 2 and 3 − Active LOW. Sampled on the rising edge of the K and K clocks Synchronous during write operations. Used to select which byte is written into the device during the current portion of the write operations. CY7C1303CV25 − BWS0 controls D[8:0], BWS1 controls D[17:9]. CY7C1306CV25 − BWS0 controls D[8:0], BWS1 controls D[17:9],BWS2 controls D[26:18] and BWS3 controls D[35:27]. Bytes not written remain unaltered. Deselecting a Byte Write Select ignores the corresponding byte of data and it is not written into the device. InputAddress Inputs. Sampled on the rising edge of the K clock during active Read operations and on the Synchronous rising edge of K for Write operations. These address inputs are multiplexed for both read and write operations. Internally, the device is organized as 1M x 18 (2 arrays each of 512K x 18) for CY7C1303CV25 and 512K x 36 (2 arrays each of 256K x 36) for CY7C1306CV25. Therefore, only 19 address inputs are needed to access the entire memory array of CY7C1303CV25 and 18 address inputs for CY7C1306CV25. These inputs are ignored when the appropriate port is deselected. OutputsData Output Signals. These pins drive out the requested data during a read operation. Valid data is Synchronous driven out on the rising edge of both the C and C clocks during read operations, or K and K when in single clock mode. When the read port is deselected, Q[x:0] are automatically tri-stated. CY7C1303CV25 − Q[17:0] CY7C1306CV25 − Q[35:0] InputRead Port Select − Active LOW. Sampled on the rising edge of positive input clock (K). When active, Synchronous a read operation is initiated. Deasserting deselects the read port. When deselected, the pending access is allowed to complete and the output drivers are automatically tri-stated following the next rising edge of the C clock. Each read access consists of a burst of two sequential transfers. Input Clock Positive Input Clock for Output Data. C is used in conjunction with C to clock out the read data from the device. C and C can be used together to deskew the flight times of various devices on the board back to the controller. See Application Example on page 7 for further details. Negative Input Clock for Output Data. C is used in conjunction with C to clock out the read data from the device. C and C can be used together to deskew the flight times of various devices on the board back to the controller. See Application Example on page 7 for further details. Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device and to drive out data through Q[x:0] when in single clock mode. All accesses are initiated on the rising edge of K. Negative Input Clock Input. K is used to capture synchronous inputs being presented to the device and to drive out data through Q[x:0] when in single clock mode. Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus impedance. Q[x:0] output impedance are set to 0.2 x RQ, where RQ is a resistor connected between ZQ and ground. Alternatively, this pin can be connected directly to VDDQ, which enables the minimum impedance mode. This pin cannot be connected directly to GND or left unconnected. WPS BWS0, BWS1, BWS2, BWS3 A Q[x:0] RPS C C Input Clock K Input Clock K ZQ Input Clock Input Document #: 001-44701 Rev. *B Page 4 of 21 [+] Feedback PRELIMINARY Pin Definitions Pin Name TDO TCK TDI TMS NC NC/36M GND/72M NC/72M GND/144M GND/288M VREF VDD VSS VDDQ CY7C1303CV25 CY7C1306CV25 (continued) Pin Description TDO for JTAG. TCK Pin for JTAG. TDI Pin for JTAG. TMS Pin for JTAG. Not Connected to the Die. Can be tied to any voltage level. Not Connected to the Die. Can be tied to any voltage level. Address expansion for 72M. This pin must be tied to GND on CY7C1303CV25. Address expansion for 72M. This pin can be tied to any voltage level on CY7C1306CV25. Address expansion for 144M. This pin must be tied to GND on CY7C1303CV25/CY7C1306CV25. Address expansion for 288M. This pin must be tied to GND on CY7C1306CV25. Reference Voltage Input. Static input used to set the reference level for HSTL inputs, Outputs, and AC measurement points. I/O Output Input Input Input N/A N/A Input N/A Input Input InputReference Power Supply Power Supply Inputs to the Core of the Device. Ground Ground for the Device. Power Supply Power Supply Inputs for the Outputs of the Device. Document #: 001-44701 Rev. *B Page 5 of 21 [+] Feedback PRELIMINARY Functional Overview The CY7C1303CV25 and CY7C1306CV25 are synchronous pipelined Burst SRAMs equipped with a read port and a write port. The read port is dedicated to read operations and the write port is dedicated to write operations. Data flows into the SRAM through the write port and flows out through the read port. These devices multiplex the address inputs to minimize the number of address pins required. By having separate read and write ports, the QDR completely eliminates the need to “turn-around” the data bus and avoids any possible data contention, thereby simplifying system design. Each access consists of two 18-bit data transfers in the case of CY7C1303CV25, and two 36-bit data transfers in the case of CY7C1306CV25 in one clock cycle. Accesses for both ports are initiated on the rising edge of the positive input clock (K). All synchronous input timing is referenced from the rising edge of the input clocks (K and K) and all output timing is referenced to the rising edge of the output clocks (C and C, or K and K when in single clock mode). All synchronous data inputs (D[x:0]) pass through input registers controlled by the input clocks (K and K). All synchronous data outputs (Q[x:0]) pass through output registers controlled by the rising edge of the output clocks (C and C or K and K when in single clock mode). All synchronous control (RPS, WPS, BWS[x:0]) inputs pass through input registers controlled by the rising edge of the input clocks (K and K). CY7C1303CV25 is described in the following sections. The same basic descriptions apply to CY7C1306CV25. CY7C1303CV25 CY7C1306CV25 BWS[1:0] are both asserted active. The 36 bits of data are then written into the memory array at the specified location. When deselected, the write port ignores all inputs after completion of pending write operations. Byte Write Operations Byte write operations are supported by the CY7C1303CV25. A write operation is initiated as described in the section Write Operations on page 6. The bytes that are written are determined by BWS0 and BWS1, which are sampled with each 18-bit data word. Asserting the appropriate Byte Write Select input during the data portion of a write latches the data being presented and writes it into the device. Deasserting the Byte Write Select input during the data portion of a write allows the data stored in the device for that byte to remain unaltered. This feature can be used to simplify read, modify, or write operations to a byte write operation. Single Clock Mode The CY7C1303CV25 can be used with a single clock that controls both the input and output registers. In this mode, the device recognizes only a single pair of input clocks (K and K) that control both the input and output registers. This operation is identical to the operation if the device had zero skew between the K/K and C/C clocks. All timing parameters remain the same in this mode. To use this mode of operation, the user must tie C and C HIGH at power on. This function is a strap option and not alterable during device operation. Concurrent Transactions The read and write ports on the CY7C1303CV25 operate independently of one another. As each port latches the address inputs on different clock edges, the user can read or write to any location, regardless of the transaction on the other port. The user can start reads and writes in the same clock cycle. If the ports access the same location at the same time, the SRAM delivers the most recent information associated with the specified address location. This includes forwarding data from a write cycle that was initiated on the previous K clock rise. Read Operations The CY7C1303CV25 is organized internally as two arrays of 512K x 18. Accesses are completed in a burst of two sequential 18-bit data words. Read operations are initiated by asserting RPS active at the rising edge of the positive input clock (K). The address is latched on the rising edge of the K clock. The address presented to the address inputs is stored in the read address register. Following the next K clock rise the corresponding lowest order 18-bit word of data is driven onto the Q[17:0] using C as the output timing reference. On the subsequent rising edge of C, the next 18-bit data word is driven onto the Q[17:0]. The requested data is valid 2.5 ns from the rising edge of the output clock (C and C or K and K when in single clock mode). Synchronous internal circuitry automatically tri-states the outputs following the next rising edge of the positive output clock (C). This allows a seamless transition between devices without the insertion of wait states in a depth expanded memory. Depth Expansion The CY7C1303CV25 has a port select input for each port. This enables for easy depth expansion. Both port selects are sampled on the rising edge of the positive input clock only (K). Each port select input can deselect the specified port. Deselecting a port does not affect the other port. All pending transactions (read and write) are completed before the device is deselected. Programmable Impedance An external resistor, RQ, must be connected between the ZQ pin on the SRAM and VSS to allow the SRAM to adjust its output driver impedance. The value of RQ must be 5x the value of the intended line impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching with a tolerance of ±15% is between 175Ω and 350Ω, with VDDQ = 1.5V. The output impedance is adjusted every 1024 cycles upon power up to account for drifts in supply voltage and temperature. Write Operations Write operations are initiated by asserting WPS active at the rising edge of the positive input clock (K). On the same K clock rise, the data presented to D[17:0] is latched and stored into the lower 18-bit write data register, provided BWS[1:0] are both asserted active. On the subsequent rising edge of the negative input clock (K), the address is latched and the information presented to D[17:0] is stored into the write data register, provided Document #: 001-44701 Rev. *B Page 6 of 21 [+] Feedback PRELIMINARY Application Example Figure 1 shows four QDR-I used in an application. Figure 1. Application Example SRAM #1 Vt R D A R P S # W P S # B W S # CY7C1303CV25 CY7C1306CV25 ZQ Q C C# K K# R = 250ohms SRAM #4 D A R P S # W P S # B W S # ZQ Q C C# K K# R = 250ohms BUS MASTER (CPU or ASIC) DATA IN DATA OUT Address RPS# WPS# BWS# Source K Source K# Delayed K Delayed K# R R = 50ohms Vt = Vddq/2 R Vt Vt Truth Table The truth table for CY7C1303CV25 and CY7C1306CV25 follows. [1, 2, 3, 4, 5, 6] Operation Write Cycle: Load address on the rising edge of K; input write data on K and K rising edges. Read Cycle: Load address on the rising edge of K; wait one cycle; read data on C and C rising edges. NOP: No Operation Standby: Clock Stopped K L-H RPS WPS X L DQ D(A + 0) at K(t) ↑ DQ D(A + 1) at K(t) ↑ L-H L X Q(A + 0) at C(t + 1) ↑ Q(A + 1) at C(t + 1) ↑ L-H Stopped H X H X D=X Q = High-Z Previous State D=X Q = High-Z Previous State Notes 1. X = “Don't Care,” H = Logic HIGH, L = Logic LOW, ↑represents rising edge. 2. Device powers up deselected with the outputs in a tri-state condition. 3. “A” represents address location latched by the devices when transaction was initiated. A + 0, A + 1 represents the internal address sequence in the burst. 4. “t” represents the cycle at which a Read/Write operation is started. t + 1 is the first clock cycle succeeding the “t” clock cycle. 5. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode. 6. It is recommended that K = K and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically. Document #: 001-44701 Rev. *B Page 7 of 21 [+] Feedback PRELIMINARY Write Cycle Descriptions The write cycle description table for CY7C1303CV25 follows. [1, 7] BWS0 L L L L H H H H BWS1 L L H H L L H H K L–H – L–H – L–H – L–H – K – L-H – Comments CY7C1303CV25 CY7C1306CV25 During the data portion of a write sequence, both bytes (D[17:0]) are written into the device. During the data portion of a write sequence, both bytes (D[17:0]) are written into the device. During the data portion of a write sequence, only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered. L–H During the data portion of a write sequence, only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered. – During the data portion of a write sequence, only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered. L–H During the data portion of a write sequence, only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered. – No data is written into the devices during this portion of a write operation. L–H No data is written into the devices during this portion of a write operation. Write Cycle Descriptions The write cycle description table for CY7C1306CV25 follows. [1, 7] BWS0 L L L L H H H H H H H H BWS1 L L H H L L H H H H H H BWS2 L L H H H H L L H H H H BWS3 L L H H H H H H L L H H K L–H – L–H – L–H – L–H – L–H – L–H – K – Comments During the data portion of a write sequence, all four bytes (D[35:0]) are written into the device. L–H During the data portion of a write sequence, all four bytes (D[35:0]) are written into the device. – During the data portion of a write sequence, only the lower byte (D[8:0]) is written into the device. D[35:9] remains unaltered. L–H During the data portion of a write sequence, only the lower byte (D[8:0]) is written into the device. D[35:9] remains unaltered. – During the data portion of a write sequence, only the byte (D[17:9]) is written into the device. D[8:0] and D[35:18] remains unaltered. L–H During the data portion of a write sequence, only the byte (D[17:9]) is written into the device. D[8:0] and D[35:18] remains unaltered. – During the data portion of a write sequence, only the byte (D[26:18]) is written into the device. D[17:0] and D[35:27] remains unaltered. L–H During the data portion of a write sequence, only the byte (D[26:18]) is written into the device. D[17:0] and D[35:27] remains unaltered. – During the data portion of a write sequence, only the byte (D[35:27]) is written into the device. D[26:0] remains unaltered. L–H During the data portion of a write sequence, only the byte (D[35:27]) is written into the device. D[26:0] remains unaltered. – No data is written into the device during this portion of a write operation. L–H No data is written into the device during this portion of a write operation. Note 7. Is based on a write cycle that was initiated in accordance with the Write Cycle Descriptions table. BWS0, BWS1, BWS2, and BWS3 can be altered on different portions of a write cycle, as long as the setup and hold requirements are achieved. Document #: 001-44701 Rev. *B Page 8 of 21 [+] Feedback PRELIMINARY IEEE 1149.1 Serial Boundary Scan (JTAG) These SRAMs incorporate a serial boundary scan Test Access Port (TAP) in the FBGA package. This part is fully compliant with IEEE Standard #1149.1-1900. The TAP operates using JEDEC standard 2.5V I/O logic levels. Instruction Register CY7C1303CV25 CY7C1306CV25 Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternatively be connected to VDD through a pull up resistor. TDO must be left unconnected. Upon power up, the device comes up in a reset state, which does not interfere with the operation of the device. Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO pins, as shown in TAP Controller Block Diagram on page 12. Upon power up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state, as described in the previous section. When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary “01” pattern to allow the fault isolation of the board level serial test path. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between TDI and TDO pins. This enables shifting of data through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. Boundary Scan Register The boundary scan register is connected to all the input and output pins on the SRAM. Several No Connect (NC) pins are also included in the scan register to reserve pins for higher density devices. The boundary scan register is loaded with the contents of the RAM input and output ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO pins when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions can be used to capture the contents of the input and output ring. The Boundary Scan Order on page 15 shows the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO. Identification (ID) Register The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in Identification Register Definitions on page 14. Test Access Port—Test Clock The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. Test Mode Select (TMS) The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. This pin may be left unconnected if the TAP is not used. The pin is pulled up internally, resulting in a logic HIGH level. Test Data-In (TDI) The TDI pin is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see the TAP Controller State Diagram on page 11. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) on any register. Test Data-Out (TDO) The TDO output pin is used to serially clock data out from the registers. The output is active, depending upon the current state of the TAP state machine (see Instruction Codes on page 14). The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. Performing a TAP Reset A reset is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This reset does not affect the operation of the SRAM and can be performed while the SRAM is operating. At power up, the TAP is reset internally to ensure that TDO comes up in a High-Z state. TAP Instruction Set Eight different instructions are possible with the three-bit instruction register. All combinations are listed in Instruction Codes on page 14. Three of these instructions are listed as RESERVED and must not be used. The other five instructions are described in this section in detail. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO pins. To execute the instruction after it is shifted in, the TAP controller must be moved into the Update-IR state. TAP Registers Registers are connected between the TDI and TDO pins to scan the data in and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction registers. Data is serially loaded into the TDI pin on the rising edge of TCK. Data is output on the TDO pin on the falling edge of TCK. Document #: 001-44701 Rev. *B Page 9 of 21 [+] Feedback PRELIMINARY IDCODE The IDCODE instruction loads a vendor-specific, 32-bit code into the instruction register. It also places the instruction register between the TDI and TDO pins and shifts the IDCODE out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register at power up or whenever the TAP controller is supplied a Test-Logic-Reset state. SAMPLE Z The SAMPLE Z instruction connects the boundary scan register between the TDI and TDO pins when the TAP controller is in a Shift-DR state. The SAMPLE Z command puts the output bus into a High-Z state until the next command is supplied during the Update IR state. SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the input and output pins is captured in the boundary scan register. The user must be aware that the TAP controller clock can only operate at a frequency up to 10 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output undergoes a transition. The TAP may then try to capture a signal while in transition (metastable state). This does not harm the device, but there is no guarantee as to the value that is captured. Repeatable results may not be possible. To guarantee that the boundary scan register captures the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller's capture setup plus hold times (tCS and tCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK captured in the boundary scan register. After the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. PRELOAD places an initial data pattern at the latched parallel outputs of the boundary scan register cells before the selection of another boundary scan test operation. The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required, that is, while the data captured is shifted out, the preloaded data can be shifted in. BYPASS CY7C1303CV25 CY7C1306CV25 When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. EXTEST The EXTEST instruction drives the preloaded data out through the system output pins. This instruction also connects the boundary scan register for serial access between the TDI and TDO in the Shift-DR controller state. EXTEST OUTPUT BUS TRI-STATE IEEE Standard 1149.1 mandates that the TAP controller be able to put the output bus into a tri-state mode. The boundary scan register has a special bit located at bit #47. When this scan cell, called the “extest output bus tri-state,” is latched into the preload register during the Update-DR state in the TAP controller, it directly controls the state of the output (Q-bus) pins, when the EXTEST is entered as the current instruction. When HIGH, it enables the output buffers to drive the output bus. When LOW, this bit places the output bus into a High-Z condition. This bit can be set by entering the SAMPLE/PRELOAD or EXTEST command, and then shifting the desired bit into that cell, during the Shift-DR state. During Update-DR, the value loaded into that shift-register cell latches into the preload register. When the EXTEST instruction is entered, this bit directly controls the output Q-bus pins. Note that this bit is pre-set HIGH to enable the output when the device is powered up, and also when the TAP controller is in the Test-Logic-Reset state. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions. Document #: 001-44701 Rev. *B Page 10 of 21 [+] Feedback PRELIMINARY TAP Controller State Diagram The state diagram for the TAP controller follows. [8] CY7C1303CV25 CY7C1306CV25 1 TEST-LOGIC RESET 0 0 TEST-LOGIC/ IDLE 1 SELECT DR-SCAN 0 1 CAPTURE-DR 0 SHIFT-DR 1 EXIT1-DR 0 PAUSE-DR 1 0 EXIT2-DR 1 UPDATE-DR 1 0 1 1 SELECT IR-SCAN 0 1 CAPTURE-IR 0 0 SHIFT-IR 1 0 1 EXIT1-IR 0 0 PAUSE-IR 1 0 EXIT2-IR 1 UPDATE-IR 1 0 1 0 Note 8. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document #: 001-44701 Rev. *B Page 11 of 21 [+] Feedback PRELIMINARY TAP Controller Block Diagram CY7C1303CV25 CY7C1306CV25 0 Bypass Register 2 TDI Selection Circuitry 31 Instruction Register 30 29 . . 2 1 0 1 0 Selection Circuitry TDO Identification Register 106 . . . . 2 1 0 Boundary Scan Register TCK TMS TAP Controller TAP Electrical Characteristics Over the Operating Range [9, 10, 11] Parameter VOH1 VOH2 VOL1 VOL2 VIH VIL IX Description Output HIGH Voltage Output HIGH Voltage Output LOW Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input and Output Load Current GND ≤ VI ≤ VDD Test Conditions IOH = −2.0 mA IOH = −100 μA IOL = 2.0 mA IOL = 100 μA 1.7 –0.3 –5 Min 1.7 2.1 0.7 0.2 VDD + 0.3 0.7 5 Max Unit V V V V V V μA Notes 9. These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics table. 10. Overshoot: VIH(AC) < VDDQ + 0.85V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > −1.5V (Pulse width less than tCYC/2). 11. All Voltage referenced to Ground. Document #: 001-44701 Rev. *B Page 12 of 21 [+] Feedback PRELIMINARY TAP AC Switching Characteristics Over the Operating Range [12, 13] Parameter tTCYC tTF tTH tTL Setup Times tTMSS tTDIS tCS Hold Times tTMSH tTDIH tCH Output Times tTDOV tTDOX TCK Clock LOW to TDO Valid TCK Clock LOW to TDO Invalid 0 TMS Hold after TCK Clock Rise TDI Hold after Clock Rise Capture Hold after Clock Rise 10 10 10 TMS Setup to TCK Clock Rise TDI Setup to TCK Clock Rise Capture Setup to TCK Rise 10 10 10 TCK Clock Cycle Time TCK Clock Frequency TCK Clock HIGH TCK Clock LOW 20 20 Description CY7C1303CV25 CY7C1306CV25 Min 50 Max 20 Unit ns MHz ns ns ns ns ns ns ns ns 20 ns ns TAP Timing and Test Conditions Figure 2 shows the TAP timing and test conditions. [13] Figure 2. TAP Timing and Test Conditions 1.25V ALL INPUT PULSES 50Ω TDO Z0 = 50Ω CL = 20 pF 2.5V 1.25V 0V (a) GND tTH tTL Test Clock TCK tTMSS tTMSH tTCYC Test Mode Select TMS tTDIS tTDIH Test Data In TDI Test Data Out TDO tTDOV tTDOX Notes 12. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register. 13. Test conditions are specified using the load in TAP AC Test Conditions. tR/tF = 1 ns. Document #: 001-44701 Rev. *B Page 13 of 21 [+] Feedback PRELIMINARY Identification Register Definitions Instruction Field Revision Number (31:29) Cypress Device ID (28:12) Cypress JEDEC ID (11:1) ID Register Presence (0) Value CY7C1303CV25 000 01011011010010101 00000110100 1 CY7C1306CV25 000 01011011010100101 00000110100 1 CY7C1303CV25 CY7C1306CV25 Description Version number. Defines the type of SRAM. Allows unique identification of SRAM vendor. Indicates the presence of an ID register. Scan Register Sizes Register Name Instruction Bypass ID Boundary Scan Bit Size 3 1 32 107 Instruction Codes Instruction EXTEST IDCODE SAMPLE Z RESERVED SAMPLE/PRELOAD RESERVED RESERVED BYPASS Code 000 001 010 011 100 101 110 111 Description Captures the input and output ring contents. Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operation. Captures the input and output contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High-Z state. Do Not Use: This instruction is reserved for future use. Captures the input and output ring contents. Places the boundary scan register between TDI and TDO. Does not affect the SRAM operation. Do Not Use: This instruction is reserved for future use. Do Not Use: This instruction is reserved for future use. Places the bypass register between TDI and TDO. This operation does not affect SRAM operation. Document #: 001-44701 Rev. *B Page 14 of 21 [+] Feedback PRELIMINARY Boundary Scan Order Bit # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Bump ID 6R 6P 6N 7P 7N 7R 8R 8P 9R 11P 10P 10N 9P 10M 11N 9M 9N 11L 11M 9L 10L 11K 10K 9J 9K 10J 11J Bit # 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 Bump ID 11H 10G 9G 11F 11G 9F 10F 11E 10E 10D 9E 10C 11D 9C 9D 11B 11C 9B 10B 11A Internal 9A 8B 7C 6C 8A 7A Bit # 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Bump ID 7B 6B 6A 5B 5A 4A 5C 4B 3A 1H 1A 2B 3B 1C 1B 3D 3C 1D 2C 3E 2D 2E 1E 2F 3F 1G 1F CY7C1303CV25 CY7C1306CV25 Bit # 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 Bump ID 3G 2G 1J 2J 3K 3J 2K 1K 2L 3L 1M 1L 3N 3M 1N 2M 3P 2N 2P 1P 3R 4R 4P 5P 5N 5R Document #: 001-44701 Rev. *B Page 15 of 21 [+] Feedback PRELIMINARY Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied.. –55°C to +125°C Supply Voltage on VDD Relative to GND ........–0.5V to +3.6V Supply Voltage on VDDQ Relative to GND.......–0.5V to +VDD DC Applied to Outputs in High-Z ........ –0.5V to VDDQ + 0.5V DC Input Voltage [10] CY7C1303CV25 CY7C1306CV25 Current into Outputs (LOW) ........................................ 20 mA Static Discharge Voltage (MIL-STD-883, M. 3015).. > 2001V Latch-up Current ................................................... > 200 mA Operating Range Range Commercial Industrial Ambient Temperature (TA) 0°C to +70°C –40°C to +85°C VDD [14] 2.5 ± 0.1V VDDQ [14] 1.4V to 1.9V .............................. –0.5V to VDD + 0.5V Electrical Characteristics DC Electrical Characteristics Over the Operating Range [11] Parameter VDD VDDQ VOH VOL VOH(LOW) VOL(LOW) VIH VIL VREF IX IOZ IDD [19] Description Power Supply Voltage I/O Supply Voltage Output HIGH Voltage Output LOW Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage [10] Input LOW Voltage [10, 17] Test Conditions Min 2.4 1.4 Typ 2.5 1.5 Max 2.6 1.9 VDDQ/2 + 0.12 VDDQ/2 + 0.12 VDDQ 0.2 VDDQ + 0.3 VREF – 0.1 Unit V V V V V V V V V μA μA mA mA Note 15 Note 16 IOH = −0.1 mA, Nominal Impedance IOL = 0.1 mA, Nominal Impedance VDDQ/2 – 0.12 VDDQ/2 – 0.12 VDDQ – 0.2 VSS VREF + 0.1 –0.3 0.68 −5 −5 0.75 Input Reference Voltage [18] Typical Value = 0.75V Input Leakage Current Output Leakage Current VDD Operating Supply Automatic Power Down Current GND ≤ VI ≤ VDDQ GND ≤ VI ≤ VDDQ, Output Disabled VDD = Max, IOUT = 0 mA, f = fMAX = 1/tCYC Max VDD, Both Ports Deselected, VIN ≥ VIH or VIN ≤ VIL f = fMAX = 1/tCYC, Inputs Static 0.95 5 5 500 240 ISB1 AC Electrical Characteristics Over the Operating Range Parameter VIH VIL Description Input HIGH Voltage Input LOW Voltage Test Conditions Min VREF + 0.2 – Typ – – Max – VREF – 0.2 Unit V V Notes 14. Power up: Assumes a linear ramp from 0V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD. 15. Output are impedance controlled. IOH = −(VDDQ/2)/(RQ/5) for values of 175 ohms