CY7C131-30JI

CY7C130, CY7C130A CY7C131, CY7C131A CY7C140, CY7C141 1K x 8 Dual-Port Static RAM Features Functional Description ■ True dual-ported memory cells, which allow simultaneous reads of the same memory location ■ 1K x 8 organization ■ 0.65 micron CMOS for optimum speed and power ■ High speed access: 15 ns ■ Low operating power: ICC = 110 mA (maximum) ■ Fully asynchronous operation The CY7C130/130A/CY7C131/131A/CY7C140[1] and CY7C141 are high speed CMOS 1K by 8 dual-port static RAMs. Two ports are provided permitting independent access to any location in memory. The CY7C130/130A/ CY7C131/131A can be used as either a standalone 8-bit dual-port static RAM or as a master dual-port RAM in conjunction with the CY7C140/CY7C141 slave dual-port device in systems requiring 16-bit or greater word widths. It is the solution to applications requiring shared or buffered data, such as cache memory for DSP, bit-slice, or multiprocessor designs. ■ Automatic power down ■ Master CY7C130/130A/CY7C131/131A easily expands data bus width to 16 or more bits using slave CY7C140/CY7C141 ■ BUSY output flag on CY7C130/130A/CY7C131/131A; BUSY input on CY7C140/CY7C141 ■ INT flag for port-to-port communication ■ Available in 48-pin DIP (CY7C130/130A/140), 52-pin PLCC, 52-pin TQFP ■ Pb-free packages available Each port has independent control pins; chip enable (CE), write enable (R/W), and output enable (OE). Two flags are provided on each port, BUSY and INT. BUSY signals that the port is trying to access the same location currently being accessed by the other port. INT is an interrupt flag indicating that data is placed in a unique location (3FF for the left port and 3FE for the right port). An automatic power down feature is controlled independently on each port by the chip enable (CE) pins. The CY7C130/130A and CY7C140 are available in 48-pin DIP. The CY7C131/131A and CY7C141 are available in 52-pin PLCC, 52-pin Pb-free PLCC, 52-pin PQFP, and 52-pin Pb-free PQFP. Logic Block Diagram R/WL CEL R/WR CER OEL OER I/O7L I/O CONTROL I/O0L I/O CONTROL [2] BUSYL A 9L A 0L I/O7R I/O0R BUSYR ADDRESS DECODER CEL OEL MEMORY ARRAY ADDRESS DECODER ARBITRATION LOGIC (7C130/7C131 ONLY) AND INTERRUPT LOGIC A 9R A 0R CER OER R/WL R/WR [3] [3] INTL INTR Notes 1. CY7C130 and CY7C130A are functionally identical; CY7C131 and CY7C131A are functionally identical. 2. CY7C130/130A/CY7C131/131A (Master): BUSY is open drain output and requires pull-up resistor. CY7C140/CY7C141 (Slave): BUSY is input. 3. Open drain outputs: pull-up resistor required. Cypress Semiconductor Corporation Document #: 38-06002 Rev. *E • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised December 09, 2008 [+] Feedback CY7C130, CY7C130A CY7C131, CY7C131A CY7C140, CY7C141 Pin Configurations Figure 1. Pin Diagram - DIP (Top View) CE L R/W L BUSY L INTL OEL A0L A1L A2L A3L A4L A5L A6L A7L A8L A9L I/O0L I/O1L I/O2L I/O3L I/O4L I/O5L I/O6L I/O7L GND VCC CER R/WR BUSYR INTR OER A0R A1R A2R A3R A4R A5R A6R A7R A8R A9R I/O7R I/O6R I/O5R I/O4R I/O3R I/O2R I/O1R I/O0R Document #: 38-06002 Rev. *E BUSYR INTR NC CER R/WR A0L OEL NC INTL 1 2 3 4 5 6 7 8 9 10 11 12 13 39 38 37 36 35 34 33 32 31 30 29 28 27 7C131 7C141 OER A0R A1R A2R A3R A4R A5R A6R A7R A8R A9R NC I/O7R I/O5R I/O6R I/O2R I/O3R I/O4R NC GND I/O0R I/O1R 1415 16 17 18 19 20 21 22 23 24 25 26 I/O6L I/O7L A6R A7R A8R A9R NC I/O7R 52 5150 49 48 47 4645 44 43 42 41 40 A1L A2L A3L A4L A5L A6L A7L A8L A9L I/O0L I/O1L I/O2L I/O3L I/O4L I/O5L I/O5R I/O6R OER A0R A1R A2R A3R A4R A5R BUSYL R/W L CEL VCC Figure 3. Pin Diagram - PQFP (Top View) BUSYR INTR NC CER R/WR I/O2R I/O3R I/O4R I/O0R I/O1R NC GND 7 6 5 4 3 2 1 52 51 50 49 48 47 46 45 44 43 42 41 7C131 40 7C141 39 38 37 36 35 34 2122 23 24 25 26 27 28 29 30 31 32 33 I/O6L I/O7L 8 9 10 11 12 13 14 15 16 17 18 19 20 I/O4L I/O5L A1L A2L A3L A4L A5L A6L A7L A8L A9L I/O0L I/O1L I/O2L I/O3L BUSYL R/W L CEL VCC A0L OEL NC INTL Figure 2. Pin Diagram - PLCC (Top View) 48 1 47 2 46 3 45 4 44 5 43 6 42 7 41 8 40 9 39 10 38 11 12 7C130 37 13 7C140 36 14 35 15 34 16 33 17 32 18 31 30 19 20 29 28 21 22 27 23 26 24 25 Page 2 of 19 [+] Feedback CY7C130, CY7C130A CY7C131, CY7C131A CY7C140, CY7C141 Pin Definitions Left Port Right Port Description CEL CER Chip Enable R/WL R/WR Read/Write Enable OEL OER Output Enable A0L–A11/12L A0R–A11/12R Address I/O0L–I/O15/17L I/O0R–I/O15/17R Data Bus Input/Output INTL INTR Interrupt Flag BUSYL BUSYR Busy Flag VCC Power GND Ground Selection Guide Parameter Maximum Access Time 7C131-15[4] 7C131A-15 7C141-15 7C131-25[4] 7C141-25 7C130-30 7C130A-30 7C131-30 7C140-30 7C141-30 7C130-35 7C131-35 7C140-35 7C141-35 7C130-45 7C131-45 7C140-45 7C141-45 7C130-55 7C131-55 7C140-55 7C141-55 Unit 15 25 30 35 45 55 ns Maximum Operating Current Com’l/Ind 190 170 170 120 120 110 mA Maximum Standby Current Com’l/Ind 75 65 65 45 45 35 mA Shaded areas contain preliminary information. Note 4. 15 and 25 ns version available only in PLCC/PQFP packages. Document #: 38-06002 Rev. *E Page 3 of 19 [+] Feedback CY7C130, CY7C130A CY7C131, CY7C131A CY7C140, CY7C141 Maximum Ratings[5] DC Input Voltage ............................................–3.5V to +7.0V Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied ............................................ –55°C to +125°C Supply Voltage to Ground Potential (Pin 48 to Pin 24)............................................–0.5V to +7.0V DC Voltage Applied to Outputs in High Z State ................................................–0.5V to +7.0V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage........................................... >2001V (per MIL-STD-883, Method 3015) Latch Up Current .................................................... >200 mA Operating Range Range Commercial Industrial Military[6] Ambient Temperature 0°C to +70°C –40°C to +85°C –55°C to +125°C VCC 5V ± 10% 5V ± 10% 5V ± 10% Electrical Characteristics Over the Operating Range[7] Parameter Description VOH VOL Output HIGH Voltage Output LOW Voltage VIH VIL IIX IOZ Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current Output Short Circuit Current[9, 10] Test Conditions VCC = Min, IOH = –4.0 mA IOL = 4.0 mA IOL = 16.0 mA[8] ICC VCC Operating Supply Current GND < VI < VCC GND < VO < VCC, Output Disabled VCC = Max, VOUT = GND CE = VIL, Com’l Outputs Open, f = fMAX[11] ISB1 Standby Current Both Ports, TTL Inputs Standby Current One Port, TTL Inputs CEL and CER > VIH, Com’l f = fMAX[11] CEL or CER > VIH, Com’l Active Port Outputs Open f = fMAX[11] ISB3 Standby Current Both Ports, CMOS Inputs ISB4 Standby Current One Port, CMOS Inputs Both Ports CEL and CER > Com’l VCC – 0.2V, VIN > VCC – 0.2V or VIN < 0.2V, f = 0 One Port CEL or Com’l CER > VCC – 0.2V, VIN > VCC – 0.2V or VIN < 0.2V, Active Port Outputs Open, f = fMAX[11] IOS ISB2 7C130-30[4] 7C130-35,45 7C130-55 7C131-15[4] 7C130A-30 7C131-35,45 7C131-55 7C131A-15 7C131-25,30 7C140-35,45 7C140-55 7C141-15 7C140-30 7C141-35,45 7C141-55 Unit 7C141-25,30 Min Max Min Max Min Max Min Max 2.4 2.4 2.4 2.4 V 0.4 0.4 0.4 0.4 V 0.5 0.5 0.5 0.5 2.2 2.2 2.2 2.2 V 0.8 0.8 0.8 0.8 V –5 +5 –5 +5 –5 +5 –5 +5 μA –5 +5 –5 +5 –5 +5 –5 +5 μA –350 –350 –350 –350 mA 190 170 120 110 mA 75 65 45 35 mA 135 115 90 75 mA 15 15 15 15 mA 125 105 85 70 mA Shaded areas contain preliminary information. Notes 5. The voltage on any input or I/O pin cannot exceed the power pin during power up. 6. TA is the “instant on” case temperature 7. See the last page of this specification for Group A subgroup testing information. 8. BUSY and INT pins only. 9. Duration of the short circuit should not exceed 30 seconds. 10. This parameter is guaranteed but not tested. 11. At f = fMAX, address and data inputs are cycling at the maximum frequency of read cycle of 1/tRC and using AC Test Waveforms input levels of GND to 3V. Document #: 38-06002 Rev. *E Page 4 of 19 [+] Feedback CY7C130, CY7C130A CY7C131, CY7C131A CY7C140, CY7C141 Capacitance[10] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions Max TA = 25°C, f = 1 MHz, VCC = 5.0V Unit 15 pF 10 pF Figure 4. AC Test Loads and Waveforms R1 893Ω 5V OUTPUT 5V R1 893Ω 5V OUTPUT R2 347Ω 30 pF INCLUDING JIGAND SCOPE R2 347Ω 5 pF INCLUDING JIGAND SCOPE (a) BUSY OR INT 30 pF (b) BUSY Output Load (CY7C130/CY7C131 ONLY) ALL INPUT PULSES Equivalent to: THÉVENIN EQUIVALENT 250Ω OUTPUT Document #: 38-06002 Rev. *E 1.40V 281Ω 3.0V GND 10% ≤ 5 ns 90% 90% 10% ≤5ns Page 5 of 19 [+] Feedback CY7C130, CY7C130A CY7C131, CY7C131A CY7C140, CY7C141 Switching Characteristics Over the Operating Range[7, 12] Parameter Description 7C131-15[4] 7C131A-15 7C141-15 7C130-25[4] 7C131-25 7C140-25 7C141-25 Min Min Max Max 7C130-30 7C130A-30 7C131-30 7C140-30 7C141-30 Min Unit Max Read Cycle tRC Read Cycle Time 15 [13] tAA Address to Data Valid tOHA Data Hold from Address Change 25 15 0 30 25 0 ns 30 0 ns ns tACE [13] CE LOW to Data Valid 15 25 30 ns tDOE OE LOW to Data Valid[13] 10 15 20 ns 15 ns 15 ns 25 ns [10, 14, 15] tLZOE OE LOW to Low Z tHZOE OE HIGH to High Z[10, 14, 15] tLZCE CE LOW to Low Z[10, 14, 15] tHZCE CE HIGH to High Z[10, 14, 15] tPU CE LOW to Power Up[10] tPD CE HIGH to Power Down[10] 3 3 10 3 3 15 5 10 0 5 15 0 15 ns ns 0 25 ns Write Cycle[16] tWC Write Cycle Time 15 25 30 ns tSCE CE LOW to Write End 12 20 25 ns tAW Address Setup to Write End 12 20 25 ns tHA Address Hold from Write End 2 2 2 ns tSA Address Setup to Write Start 0 0 0 ns tPWE R/W Pulse Width 12 15 25 ns tSD Data Setup to Write End 10 15 15 ns tHD Data Hold from Write End 0 tHZWE R/W LOW to High Z[15] tLZWE R/W HIGH to Low Z[15] 0 10 0 0 15 0 ns 15 0 ns ns Shaded areas contain preliminary information. Notes 12. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading of the specified IOL/IOH, and 30 pF load capacitance. 13. AC Test Conditions use VOH = 1.6V and VOL = 1.4V. 14. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE. 15. tLZCE, tLZWE, tHZOE, tLZOE, tHZCE and tHZWE are tested with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady state voltage. 16. The internal write time of the memory is defined by the overlap of CS LOW and R/W LOW. Both signals must be low to initiate a write and either signal can terminate a write by going high. The data input setup and hold timing should be referenced to the rising edge of the signal that terminates the write. Document #: 38-06002 Rev. *E Page 6 of 19 [+] Feedback CY7C130, CY7C130A CY7C131, CY7C131A CY7C140, CY7C141 Switching Characteristics Over the Operating Range[7, 12] Parameter Description (continued) 7C131-15[4] 7C131A-15 7C141-15 7C130-25[4] 7C131-25 7C140-25 7C141-25 Min Min Max Max 7C130-30 7C130A-30 7C131-30 7C140-30 7C141-30 Min Unit Max Busy/Interrupt Timing tBLA BUSY LOW from Address Match 15 20 20 ns tBHA BUSY HIGH from Address Mismatch[17] 15 20 20 ns tBLC BUSY LOW from CE LOW 15 20 20 ns tBHC BUSY HIGH from CE HIGH[17] 15 20 20 ns tPS Port Set Up for Priority 5 5 5 ns tWB[18] R/W LOW after BUSY LOW 0 0 0 ns 13 tWH R/W HIGH after BUSY HIGH tBDD BUSY HIGH to Valid Data tDDD tWDD 20 30 ns 15 25 30 ns Write Data Valid to Read Data Valid Note 19 Note 19 Note 19 ns Write Pulse to Data Delay Note 19 Note 19 Note 19 ns Interrupt Timing tWINS R/W to INTERRUPT Set Time 15 25 25 ns tEINS CE to INTERRUPT Set Time 15 25 25 ns tINS Address to INTERRUPT Set Time 15 25 25 ns tOINR OE to INTERRUPT Reset Time[17] 15 25 25 ns tEINR CE to INTERRUPT Reset Time[17] 15 25 25 ns 15 25 25 ns tINR Address to INTERRUPT Reset Time[17] Shaded areas contain preliminary information. Notes 17. These parameters are measured from the input signal changing, until the output pin goes to a high-impedance state. 18. CY7C140/CY7C141 only. 19. A write operation on Port A, where Port A has priority, leaves the data on Port B’s outputs undisturbed until one access time after one of the following: BUSY on Port B goes HIGH. Port B’s address is toggled. CE for Port B is toggled. R/W for Port B is toggled during valid read. Document #: 38-06002 Rev. *E Page 7 of 19 [+] Feedback CY7C130, CY7C130A CY7C131, CY7C131A CY7C140, CY7C141 Switching Characteristics Over the Operating Range[7,12] Parameter Description Read Cycle tRC Read Cycle Time tAA Address to Data Valid[13] tOHA Data Hold from Address Change tACE CE LOW to Data Valid[13] tDOE OE LOW to Data Valid[13] tLZOE OE LOW to Low Z[10, 14, 15] tHZOE OE HIGH to High Z[10, 14, 15] tLZCE CE LOW to Low Z[10, 14, 15] tHZCE CE HIGH to High Z[10, 14, 15] tPU CE LOW to Power Up[10] tPD CE HIGH to Power Down[10] Write Cycle[16] tWC Write Cycle Time tSCE CE LOW to Write End tAW Address Setup to Write End tHA Address Hold from Write End tSA Address Setup to Write Start tPWE R/W Pulse Width tSD Data Setup to Write End tHD Data Hold from Write End tHZWE R/W LOW to High Z[15] tLZWE R/W HIGH to Low Z[15] Busy/Interrupt Timing tBLA BUSY LOW from Address Match tBHA BUSY HIGH from Address Mismatch[17] tBLC BUSY LOW from CE LOW BUSY HIGH from CE HIGH[17] tBHC tPS Port Set Up for Priority tWB[18] R/W LOW after BUSY LOW tWH R/W HIGH after BUSY HIGH tBDD BUSY HIGH to Valid Data tDDD Write Data Valid to Read Data Valid tWDD Write Pulse to Data Delay Interrupt Timing tWINS R/W to INTERRUPT Set Time tEINS tINS tOINR tEINR tINR CE to INTERRUPT Set Time Address to INTERRUPT Set Time OE to INTERRUPT Reset Time[17] CE to INTERRUPT Reset Time[17] Address to INTERRUPT Reset Time[17] Document #: 38-06002 Rev. *E 7C130-35 7C131-35 7C140-35 7C141-35 Min Max 35 7C130-45 7C131-45 7C140-45 7C141-45 Min Max 45 35 0 55 45 0 35 20 3 45 25 20 20 20 0 25 0 35 45 35 35 2 0 30 20 0 20 0 25 5 20 35 35 30 30 2 0 25 15 0 55 25 3 5 0 55 0 3 5 7C130-55 7C131-55 7C140-55 7C141-55 Min Max 35 55 40 40 2 0 30 20 0 20 0 20 20 20 20 25 0 ns ns ns ns ns ns ns ns ns ns 35 Note 19 Note 19 45 Note 19 Note 19 45 Note 19 Note 19 25 25 25 25 25 25 35 35 35 35 35 35 45 45 45 45 45 45 ns ns ns ns ns ns 5 0 35 30 30 30 30 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 5 0 30 25 25 25 25 Unit 5 0 35 Page 8 of 19 [+] Feedback CY7C130, CY7C130A CY7C131, CY7C131A CY7C140, CY7C141 Switching Waveforms Figure 5. Read Cycle No. 1[20, 21] Either Port Address Access tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATAVALID DATA VALID Figure 6. Read Cycle No. 2[20, 22] Either Port CE/OE Access CE tHZCE tACE OE tHZOE tDOE tLZOE tLZCE DATA VALID DATA OUT tPU tPD ICC ISB Figure 7. Read Cycle No. 3[21] Read with BUSY, Master: CY7C130 and CY7C131 tRC ADDRESSR ADDRESS MATCH tPWE R/WR tHD DINR VALID ADDRESS MATCH ADDRESSL tPS tBHA BUSYL tBLA tBDD DOUTL VALID tWDD tDDD Notes 20. R/W is HIGH for read cycle. 21. Device is continuously selected, CE = VIL and OE = VIL. 22. Address valid prior to or coincident with CE transition LOW. Document #: 38-06002 Rev. *E Page 9 of 19 [+] Feedback CY7C130, CY7C130A CY7C131, CY7C131A CY7C140, CY7C141 Switching Waveforms (continued) Figure 8. Write Cycle No. 1 (OE Three-States Data I/Os—Either Port[16, 23] Either Port tWC ADDRESS tSCE CE tAW tSA tHA tPWE R/W tSD DATAIN tHD DATA VALID OE tHZOE HIGH IMPEDANCE DOUT Figure 9. Write Cycle No. 2 (R/W Three-States Data I/Os—Either Port)[17, 24] tWC ADDRESS tSCE tHA CE tSA tAW tPWE R/W tSD DATAIN tHD DATA VALID tHZWE tLZWE HIGH IMPEDANCE DATAOUT Notes 23. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or tHZWE + tSD to allow the data I/O pins to enter high impedance and for data to be placed on the bus for the required tSD. 24. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high impedance state. Document #: 38-06002 Rev. *E Page 10 of 19 [+] Feedback CY7C130, CY7C130A CY7C131, CY7C131A CY7C140, CY7C141 Switching Waveforms (continued) Figure 10. Busy Timing Diagram No. 1 (CE Arbitration) CEL Valid First: ADDRESS L,R ADDRESS MATCH CEL tPS CER tBLC tBHC BUSYR CER Valid First: ADDRESSL,R ADDRESS MATCH CER tPS CEL tBLC tBHC BUSYL Figure 11. Busy Timing Diagram No. 2 (Address Arbitration) Left Address Valid First: tRC or tWC ADDRESS MATCH ADDRESSL ADDRESS MISMATCH tPS ADDRESS R tBLA tBHA BUSYR Right Address Valid First: tRC or tWC ADDRESS MATCH ADDRESSR ADDRESS MISMATCH tPS ADDRESSL tBLA tBHA BUSYL Document #: 38-06002 Rev. *E Page 11 of 19 [+] Feedback CY7C130, CY7C130A CY7C131, CY7C131A CY7C140, CY7C141 Switching Waveforms (continued) Figure 12. Busy Timing Diagram No. 3 Write with BUSY (Slave:CY7C140/CY7C141) CE tPWE R/W tWB tWH BUSY Document #: 38-06002 Rev. *E Page 12 of 19 [+] Feedback CY7C130, CY7C130A CY7C131, CY7C131A CY7C140, CY7C141 Switching Waveforms (continued) Figure 13. Interrupt Timing Diagrams Left Side Sets INTR tWC ADDRL WRITE 3FF tINS tHA CEL tEINS R/WL tSA tWINS INTR Right Side Clears INTR tRC ADDRR READ 3FF tHA tINT CER tEINR R/WR OER tOINR INTR Right Side Sets INTL t WC ADDRR WRITE 3FE tHA tINS CER tEINS R/WR tSA tWINS INTL Left Side Clears INTL tRC ADDRR READ 3FE tHA tINR CEL tEINR R/WL OEL tOINR INTL Document #: 38-06002 Rev. *E Page 13 of 19 [+] Feedback CY7C130, CY7C130A CY7C131, CY7C131A CY7C140, CY7C141 NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.2 ICC 1.0 0.8 0.6 0.4 1.0 0.8 0.6 0.0 4.0 4.5 5.0 VCC = 5.0V VIN = 5.0V 0.4 I SB3 0.2 I SB3 0.2 ICC 5.5 0.6 –55 6.0 1.6 1.3 NORMALIZED tAA 1.2 1.1 TA = 25°C 1.4 1.2 1.0 VCC = 5.0V 0.8 0.9 5.0 5.5 0.6 –55 6.0 25 SUPPLY VOLTAGE (V) AMBIENT TEMPERATURE (°C) TYPICAL POWER-ON CURRENT vs. SUPPLY VOLTAGE TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING 3.0 30.0 2.5 25.0 2.0 15.0 1.5 0.5 3.0 4.0 SUPPLY VOLTAGE (V) Document #: 38-06002 Rev. *E 40 20 0 0 5.0 0 1.0 2.0 3.0 4.0 OUTPUT VOLTAGE (V) OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE 140 120 100 80 60 40 VCC = 5.0V TA = 25°C 20 0 0.0 1.0 2.0 3.0 4.0 OUTPUT VOLTAGE (V) NORMALIZED ICC vs. CYCLE TIME VCC = 4.5V TA = 25°C VIN = 0.5V 1.0 VCC = 4.5V TA = 25°C 5.0 2.0 VCC = 5.0V TA = 25°C 0.75 10.0 1.0 1.0 60 1.25 20.0 0 80 125 DELTA tAA (ns) NORMALIZED tPC 4.5 100 NORMALIZED ICC NORMALIZED tAA 1.4 0.8 4.0 120 125 NORMALIZED ACCESS TIME vs. AMBIENT TEMPERATURE NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE 1.0 OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE AMBIENT TEMPERATURE (°C) SUPPLY VOLTAGE (V) 0.0 25 OUTPUT SINK CURRENT (mA) 1.2 NORMALIZED ICC, ISB NORMALIZED ICC, ISB 1.4 OUTPUT SOURCE CURRENT (mA) Typical DC and AC Characteristics 0 200 400 600 800 1000 CAPACITANCE (pF) 0.50 10 20 40 30 CYCLE FREQUENCY (MHz) Page 14 of 19 [+] Feedback CY7C130, CY7C130A CY7C131, CY7C131A CY7C140, CY7C141 Ordering Information Speed (ns) 30 35 45 55 15 25 30 35 45 55 30 Ordering Code Package Name Package Type Operating Range CY7C130-30PC P25 48-Pin (600 Mil) Molded DIP Commercial CY7C130A-30PI P25 48-Pin Pb-Free (600 Mil) Molded DIP Industrial CY7C130-35PC P25 48-Pin (600 Mil) Molded DIP Commercial CY7C130-35PI P25 48-Pin (600 Mil) Molded DIP Industrial CY7C130-45PC P25 48-Pin (600 Mil) Molded DIP Commercial CY7C130-45PI P25 48-Pin (600 Mil) Molded DIP Industrial CY7C130-55PC P25 48-Pin (600 Mil) Molded DIP Commercial CY7C130-55PI P25 48-Pin (600 Mil) Molded DIP Industrial CY7C131-15JC J69 52-Pin Plastic Leaded Chip Carrier Commercial CY7C131-15JXC J69 52-Pin Pb-Free Plastic Leaded Chip Carrier CY7C131-15NC N52 52-Pin Plastic Quad Flatpack CY7C131-15JI J69 52-Pin Plastic Leaded Chip Carrier CY7C131A-15JXI J69 52-Pin Pb-Free Plastic Leaded Chip Carrier CY7C131-15NXI N52 52-Pin Pb-Free Plastic Quad Flatpack CY7C131-25JC J69 52-Pin Plastic Leaded Chip Carrier CY7C131-25JXC J69 52-Pin Pb-Free Plastic Leaded Chip Carrier CY7C131-25NC N52 52-Pin Plastic Quad Flatpack CY7C131-25NXC N52 52-Pin Pb-Free Plastic Quad Flatpack CY7C131-25JI J69 52-Pin Plastic Leaded Chip Carrier CY7C131-25NI N52 52-Pin Plastic Quad Flatpack CY7C131-30JC J69 52-Pin Plastic Leaded Chip Carrier CY7C131-30NC N52 52-Pin Plastic Quad Flatpack CY7C131-30JI J69 52-Pin Plastic Leaded Chip Carrier Industrial CY7C131-35JC J69 52-Pin Plastic Leaded Chip Carrier Commercial CY7C131-35NC N52 52-Pin Plastic Quad Flatpack CY7C131-35JI J69 52-Pin Plastic Leaded Chip Carrier CY7C131-35NI N52 52-Pin Plastic Quad Flatpack CY7C131-45JC J69 52-Pin Plastic Leaded Chip Carrier CY7C131-45NC N52 52-Pin Plastic Quad Flatpack CY7C131-45JI J69 52-Pin Plastic Leaded Chip Carrier CY7C131-45NI N52 52-Pin Plastic Quad Flatpack CY7C131-55JC J69 52-Pin Plastic Leaded Chip Carrier CY7C131-55JXC J69 52-Pin Pb-Free Plastic Leaded Chip Carrier CY7C131-55NC N52 52-Pin Plastic Quad Flatpack CY7C131-55NXC N52 52-Pin Pb-Free Plastic Quad Flatpack CY7C131-55JI J69 52-Pin Plastic Leaded Chip Carrier CY7C131-55JXI J69 52-Pin Pb-Free Plastic Leaded Chip Carrier CY7C131-55NI N52 52-Pin Plastic Quad Flatpack CY7C131-55NXI N52 52-Pin Pb-Free Plastic Quad Flatpack CY7C140-30PC P25 48-Pin (600 Mil) Molded DIP Commercial CY7C140-30PI P25 48-Pin (600 Mil) Molded DIP Industrial Document #: 38-06002 Rev. *E Industrial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Page 15 of 19 [+] Feedback CY7C130, CY7C130A CY7C131, CY7C131A CY7C140, CY7C141 Ordering Information (continued) Speed (ns) 35 45 55 15 25 30 35 45 55 Ordering Code Package Name Package Type Operating Range CY7C140-35PC P25 48-Pin (600 Mil) Molded DIP Commercial CY7C140-35PI P25 48-Pin (600 Mil) Molded DIP Industrial CY7C140-45PC P25 48-Pin (600 Mil) Molded DIP Commercial CY7C140-45PI P25 48-Pin (600 Mil) Molded DIP Industrial CY7C140-55PC P25 48-Pin (600 Mil) Molded DIP Commercial CY7C140-55PI P25 48-Pin (600 Mil) Molded DIP Industrial CY7C141-15JC J69 52-Pin Plastic Leaded Chip Carrier Commercial CY7C141-15NC N52 52-Pin Plastic Quad Flatpack CY7C141-25JC J69 52-Pin Plastic Leaded Chip Carrier CY7C141-25JXC J69 52-Pin Pb-Free Plastic Leaded Chip Carrier CY7C141-25NC N52 52-Pin Plastic Quad Flatpack CY7C141-25JI J69 52-Pin Plastic Leaded Chip Carrier CY7C141-25NI N52 52-Pin Plastic Quad Flatpack CY7C141-30JC J69 52-Pin Plastic Leaded Chip Carrier CY7C141-30NC N52 52-Pin Plastic Quad Flatpack CY7C141-30JI J69 52-Pin Plastic Leaded Chip Carrier Industrial CY7C141-35JC J69 52-Pin Plastic Leaded Chip Carrier Commercial CY7C141-35NC N52 52-Pin Plastic Quad Flatpack CY7C141-35JI J69 52-Pin Plastic Leaded Chip Carrier CY7C141-35NI N52 52-Pin Plastic Quad Flatpack CY7C141-45JC J69 52-Pin Plastic Leaded Chip Carrier CY7C141-45NC N52 52-Pin Plastic Quad Flatpack CY7C141-45JI J69 52-Pin Plastic Leaded Chip Carrier CY7C141-45NI N52 52-Pin Plastic Quad Flatpack CY7C141-55JC J69 52-Pin Plastic Leaded Chip Carrier CY7C141-55NC N52 52-Pin Plastic Quad Flatpack CY7C141-55JI J69 52-Pin Plastic Leaded Chip Carrier CY7C141-55NI N52 52-Pin Plastic Quad Flatpack Document #: 38-06002 Rev. *E Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial Page 16 of 19 [+] Feedback CY7C130, CY7C130A CY7C131, CY7C131A CY7C140, CY7C141 Package Diagrams Figure 14. 48-Pin (600 Mil) Sidebraze DIP D26 MIL-STD-1835 D-14 Config. C 51-80044 ** Figure 15. 52-Pin Pb-Free Plastic Leaded Chip Carrier J69 SEATING PLANE PIN #1 ID 7 1 MIN. MAX. 0.004 DIMENSIONS IN INCHES 47 8 46 0.013 0.021 0.785 0.795 0.750 0.756 0.045 0.055 20 0.690 0.730 34 0.023 0.033 21 33 0.750 0.756 0.785 0.795 Document #: 38-06002 Rev. *E 0.020 MIN. 0.090 0.130 0.165 0.200 51-85004-*A Page 17 of 19 [+] Feedback CY7C130, CY7C130A CY7C131, CY7C131A CY7C140, CY7C141 Package Diagrams (continued) Figure 16. 48-Pin (600 Mil) Molded DIP P25 51-85020-*B Figure 17. 52-Pin Pb-Free Plastic Quad Flatpack N52 51-85042-** Document #: 38-06002 Rev. *E Page 18 of 19 [+] Feedback CY7C130, CY7C130A CY7C131, CY7C131A CY7C140, CY7C141 Document History Page Document Title: CY7C130/CY7C130A/CY7C131/CY7C131A/CY7C140/CY7C141 1K x 8 Dual-Port Static RAM Document Number: 38-06002 Rev. ECN No. Orig. of Change Submission Date ** 110169 SZV 09/29/01 *A 122255 RBI 12/26/02 Power up requirements added to Maximum Ratings Information *B 236751 YDT See ECN Removed cross information from features section *C 325936 RUY See ECN Added pin definitions table, 52-pin PQFP package diagram and Pb-free information *D 393153 YIM See ECN Added CY7C131-15JI to ordering information Added Pb-Free parts to ordering information: CY7C131-15JXI *E 2623540 VKN/PYRS 12/17/08 Added CY7C130A and CY7C131A parts Removed military information Updated ordering information table Description of Change Change from Spec number: 38-00027 to 38-06002 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Clocks & Buffers Wireless Memories Image Sensors PSoC Solutions psoc.cypress.com clocks.cypress.com General Low Power/Low Voltage psoc.cypress.com/solutions psoc.cypress.com/low-power wireless.cypress.com Precision Analog memory.cypress.com LCD Drive psoc.cypress.com/lcd-drive CAN 2.0b psoc.cypress.com/can USB psoc.cypress.com/usb image.cypress.com psoc.cypress.com/precision-analog © Cypress Semiconductor Corporation, 2001-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-06002 Rev. *E Revised December 09, 2008 Page 19 of 19 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback