CY7C1311BV18-250BZC

PRELIMINARY CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18 18-Mbit QDR™-II SRAM 4-Word Burst Architecture Features • Separate Independent Read and Write data ports — Supports concurrent transactions • 250-MHz clock for high bandwidth • 4-Word Burst for reducing address bus frequency • Double Data Rate (DDR) interfaces on both Read and Write ports (data transferred at 500 MHz) at 250 MHz • Two input clocks (K and K) for precise DDR timing — SRAM uses rising edges only • Two output clocks (C and C) account for clock skew and flight time mismatching • Echo clocks (CQ and CQ) simplify data capture in high-speed systems • Single multiplexed address input bus latches address inputs for both Read and Write ports • Separate Port Selects for depth expansion • Synchronous internally self-timed writes • Available in ×8, x9, ×18, and ×36 configurations • Full data coherency providing most current data • Core VDD = 1.8(+/-0.1V); I/O VDDQ = 1.4V to VDD) • 15 × 17 x 1.4 mm 1.0-mm pitch FBGA package, 165-ball (11 × 15 matrix) • Variable drive HSTL output buffers • JTAG 1149.1 compatible test access port • Delay Lock Loop (DLL) for accurate data placement Functional Description The CY7C1311BV18, CY7C1911BV18, CY7C1313BV18, and CY7C1315BV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to support Read operations and the Write port has dedicated Data Inputs to support Write operations. QDR-II architecture has separate data inputs and data outputs to completely eliminate the need to “turn-around” the data bus required with common I/O devices. Access to each port is accomplished through a common address bus. Addresses for Read and Write addresses are latched on alternate rising edges of the input (K) clock. Accesses to the QDR-II Read and Write ports are completely independent of one another. In order to maximize data throughput, both Read and Write ports are equipped with Double Data Rate (DDR) interfaces. Each address location is associated with four 8-bit words (CY7C1311BV18) or 9-bit words (CY7C1911BV18) or 18-bit words (CY7C1313BV18) or 36-bit words (CY7C1315BV18) that burst sequentially into or out of the device. Since data can be transferred into and out of the device on every rising edge of both input clocks (K and K and C and C), memory bandwidth is maximized while simplifying system design by eliminating bus “turn-arounds”. Depth expansion is accomplished with Port Selects for each port. Port selects allow each port to operate independently. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry. Configurations CY7C1311BV18–2M x 8 CY7C1911BV18–2M x 9 CY7C1313BV18–1M x 18 CY7C1315BV18–512K x 36 Cypress Semiconductor Corporation Document Number: 38-05620 Rev. ** • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised July 23, 2004 PRELIMINARY Logic Block Diagram (CY7C1311BV18) D[7:0] 8 Write Write Write Write Reg Reg Reg Reg CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18 19 Write Add. Decode Read Add. Decode A(18:0) Address Register Address Register 19 A(18:0) 512K x 8 Array 512K x 8 Array 512K x 8 Array 512K x 8 Array K K CLK Gen. Control Logic RPS C C DOFF Read Data Reg. 32 Control Logic 16 Reg. 16 Reg. 8 Reg. CQ CQ VREF WPS NWS[1:0] 8 Q[7:0] Logic Block Diagram (CY7C1911BV18) D[8:0] 9 Write Write Write Write Reg Reg Reg Reg 19 Write Add. Decode Read Add. Decode A(18:0) Address Register Address Register 19 A(18:0) 512K x 9 Array 512K x 9 Array 512K x 9 Array 512K x 9 Array K K CLK Gen. Control Logic RPS C C DOFF Read Data Reg. 36 Control Logic 18 Reg. 18 Reg. 9 Reg. CQ CQ VREF WPS BWS[0] 9 Q[8:0] Document Number: 38-05620 Rev. ** Page 2 of 23 PRELIMINARY Logic Block Diagram (CY7C1313BV18) D[17:0] 18 Write Write Write Write Reg Reg Reg Reg CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18 18 Write Add. Decode Read Add. Decode A(17:0) Address Register Address Register 18 A(17:0) 256K x 18 Array 256K x 18 Array 256K x 18 Array 256K x 18 Array K K CLK Gen. Control Logic RPS C C DOFF Read Data Reg. 72 Control Logic 36 Reg. 36 Reg. 18 Reg. CQ CQ VREF WPS BWS[1:0] 18 Q[17:0] Logic Block Diagram (CY7C1315BV18) D[35:0] 36 Write Write Write Write Reg Reg Reg Reg 17 Write Add. Decode Read Add. Decode A(16:0) Address Register Address Register 17 A(16:0) 128K x 36 Array 128K x 36 Array 128K x 36 Array 128K x 36 Array K K CLK Gen. Control Logic RPS C C DOFF VREF WPS BWS[3:0] Read Data Reg. 144 Control Logic 72 Reg. 72 Reg. 36 Reg. CQ CQ 36 Q [35:0] Selection Guide 250 MHz Maximum Operating Frequency Maximum Operating Current 250 TBD 200 MHz 200 TBD 167 MHz 167 TBD Unit MHz mA Document Number: 38-05620 Rev. ** Page 3 of 23 PRELIMINARY Pin Configurations CY7C1311BV18 (2M × 8)–15 × 17 FBGA CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18 1 A B C D E F G H J K L M N P R CQ NC NC NC NC NC NC DOFF NC NC NC NC NC NC TDO 2 NC/72M NC NC D4 NC NC D5 VREF NC NC Q6 NC D7 NC TCK 3 A NC NC NC Q4 NC Q5 VDDQ NC NC D6 NC NC Q7 A 4 WPS A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 5 NWS1 NC/288M A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 6 K K NC VSS VSS VSS VSS VSS VSS VSS VSS VSS A C C 7 NC/144M NWS0 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 8 RPS A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 9 A NC NC NC NC NC NC VDDQ NC NC NC NC NC NC A 10 NC/36M NC NC NC D2 NC NC VREF Q1 NC NC NC NC NC TMS 11 CQ Q3 D3 NC Q2 NC NC ZQ D1 NC Q0 D0 NC NC TDI CY7C1911BV18 (2M × 9)–15 × 17 FBGA 1 A B C D E F G H J K L M N P R CQ NC NC NC NC NC NC DOFF NC NC NC NC NC NC TDO 2 NC/72M NC NC D5 NC NC D6 VREF NC NC Q7 NC D8 NC TCK 3 A NC NC NC Q5 NC Q6 VDDQ NC NC D7 NC NC Q8 A 4 WPS A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 5 NC NC/288M A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 6 K K NC VSS VSS VSS VSS VSS VSS VSS VSS VSS A C C 7 NC/144M BWS0 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 8 RPS A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 9 A NC NC NC NC NC NC VDDQ NC NC NC NC NC NC A 10 NC/36M NC NC NC D3 NC NC VREF Q2 NC NC NC NC D0 TMS 11 CQ Q4 D4 NC Q3 NC NC ZQ D2 NC Q1 D1 NC Q0 TDI Document Number: 38-05620 Rev. ** Page 4 of 23 PRELIMINARY Pin Configurations (continued) CY7C1313V18 (1M × 18)–15 × 17 FBGA CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18 1 A B C D E F G H J K L M N P R CQ NC NC NC NC NC NC DOFF NC NC NC NC NC NC TDO 2 Q9 NC D11 NC Q12 D13 VREF NC NC Q15 NC D17 NC TCK 3 D9 D10 Q10 Q11 D12 Q13 VDDQ D14 Q14 D15 D16 Q16 Q17 A 4 WPS A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 5 BWS1 NC A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 6 K K NC VSS VSS VSS VSS VSS VSS VSS VSS VSS A C C 7 NC/288M BWS0 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 8 RPS A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 9 A NC NC NC NC NC NC VDDQ NC NC NC NC NC NC A 10 NC/72M NC Q7 NC D6 NC NC VREF Q4 D3 NC Q1 NC D0 TMS 11 CQ Q8 D8 D7 Q6 Q5 D5 ZQ D4 Q3 Q2 D2 D1 Q0 TDI NC/144M NC/36M CY7C1315AV18 (512K × 36)–15 × 17FBGA 1 A B C D E F G H J K L M N P R CQ Q27 D27 D28 Q29 Q30 D30 DOFF D31 Q32 Q33 D33 D34 Q35 TDO 2 Q18 Q28 D20 D29 Q21 D22 VREF Q31 D32 Q24 Q34 D26 D35 TCK 3 D18 D19 Q19 Q20 D21 Q22 VDDQ D23 Q23 D24 D25 Q25 Q26 A 4 WPS A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 5 BWS2 BWS3 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 6 K K NC VSS VSS VSS VSS VSS VSS VSS VSS VSS A C C 7 BWS1 BWS0 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 8 RPS A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 9 D17 D16 Q16 Q15 D14 Q13 VDDQ D12 Q12 D11 D10 Q10 Q9 A 10 Q17 Q7 D15 D6 Q14 D13 VREF Q4 D3 Q11 Q1 D9 D0 TMS 11 CQ Q8 D8 D7 Q6 Q5 D5 ZQ D4 Q3 Q2 D2 D1 Q0 TDI NC/288M NC/72M NC/36M NC/144M Document Number: 38-05620 Rev. ** Page 5 of 23 PRELIMINARY Pin Definitions Pin Name D[x:0] I/O Pin Description CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18 InputData input signals, sampled on the rising edge of K and K clocks during valid write operaSynchronous tions. CY7C1311BV18 − D[7:0] CY7C1911BV18 − D[8:0] CY7C1313BV18 − D[17:0] CY7C1315BV18 − D[35:0] InputWrite Port Select, active LOW. Sampled on the rising edge of the K clock. When asserted active, Synchronous a Write operation is initiated. Deasserting will deselect the Write port. Deselecting the Write port will cause D[x:0] to be ignored. InputNibble Write Select 0, 1 − active LOW.(CY7C1311BV18 Only) Sampled on the rising edge of Synchronous the K and K clocks during Write operations. Used to select which nibble is written into the device NWS0 controls D[3:0] and NWS1 controls D[7:4]. All the Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble Write Select will cause the corresponding nibble of data to be ignored and not written into the device. WPS NWS0, NWS1, BWS0, BWS1, InputByte Write Select 0, 1, 2, and 3 − active LOW. Sampled on the rising edge of the K and K clocks BWS2, BWS3 Synchronous during Write operations. Used to select which byte is written into the device during the current portion of the Write operations. Bytes not written remain unaltered. CY7C1911BV18 − BWS0 controls D[8:0] CY7C1313BV18 − BWS0 controls D[8:0] and BWS1 controls D[17:9]. CY7C1315BV18 − BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18] and BWS3 controls D[35:27]. All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select will cause the corresponding byte of data to be ignored and not written into the device. A InputAddress Inputs. Sampled on the rising edge of the K clock during active Read and Write operaSynchronous tions. These address inputs are multiplexed for both Read and Write operations. Internally, the device is organized as 2M x 8 (4 arrays each of 512K x 8) for CY7C1311BV18, 2M x 9 (4 arrays each of 512K x 9) for CY7C1911BV18,1M x 18 (4 arrays each of 256K x 18) for CY7C1313BV18 and 512K x 36 (4 arrays each of 128K x 36) for CY7C1315BV18. Therefore, only 19 address inputs are needed to access the entire memory array of CY7C1311BV18 and CY7C1911BV18, 18 address inputs for CY7C1313BV18 and 17 address inputs for CY7C1315BV18. These inputs are ignored when the appropriate port is deselected. OutputsData Output signals. These pins drive out the requested data during a Read operation. Valid Synchronous data is driven out on the rising edge of both the C and C clocks during Read operations or K and K. when in single clock mode. When the Read port is deselected, Q[x:0] are automatically tri-stated. CY7C1311BV18 − Q[7:0] CY7C1911BV18 − Q[8:0] CY7C1313BV18 − Q[17:0] CY7C1315BV18 − Q[35:0] InputRead Port Select, active LOW. Sampled on the rising edge of Positive Input Clock (K). When Synchronous active, a Read operation is initiated. Deasserting will cause the Read port to be deselected. When deselected, the pending access is allowed to complete and the output drivers are automatically tri-stated following the next rising edge of the C clock. Each Read access consists of a burst of four sequential transfers. InputClock InputClock InputClock InputClock Positive Output Clock Input. C is used in conjunction with C to clock out the Read data from the device. C and C can be used together to deskew the flight times of various devices on the board back to the controller. See application example for further details. Negative Output Clock Input. C is used in conjunction with C to clock out the Read data from the device. C and C can be used together to deskew the flight times of various devices on the board back to the controller. See application example for further details. Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device and to drive out data through Q[x:0] when in single clock mode. All accesses are initiated on the rising edge of K. Negative Input Clock Input. K is used to capture synchronous inputs being presented to the device and to drive out data through Q[x:0] when in single clock mode. Page 6 of 23 Q[x:0] RPS C C K K Document Number: 38-05620 Rev. ** PRELIMINARY Pin Definitions (continued) Pin Name CQ I/O Echo Clock Pin Description CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18 CQ is referenced with respect to C. This is a free running clock and is synchronized to the output clock (C) of the QDR-II. In the single clock mode, CQ is generated with respect to K. The timings for the echo clocks are shown in the AC Timing table. CQ is referenced with respect to C. This is a free running clock and is synchronized to the output clock (C) of the QDR-II. In the single clock mode, CQ is generated with respect to K. The timings for the echo clocks are shown in the AC Timing table. Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 x RQ, where RQ is a resistor connected between ZQ and ground. Alternately, this pin can be connected directly to VDD, which enables the minimum impedance mode. This pin cannot be connected directly to GND or left unconnected. DLL Turn Off - active LOW. Connecting this pin to ground will turn off the DLL inside the device. The timings in the DLL turned off operation will be different from those listed in this data sheet. More details on this operation can be found in the application note, “DLL Operation in the QDR-II.” TDO for JTAG. TCK pin for JTAG. TDI pin for JTAG. TMS pin for JTAG. Not connected to the die. Can be tied to any voltage level. Not connected to the die. Can be tied to any voltage level. Not connected to the die. Can be tied to any voltage level. Not connected to the die. Can be tied to any voltage level. Not connected to the die. Can be tied to any voltage level. Reference Voltage Input. Static input used to set the reference level for HSTL inputs and outputs as well as AC measurement points. Ground for the device. CQ Echo Clock ZQ Input DOFF Input TDO TCK TDI TMS NC NC/36M NC/72M Output Input Input Input N/A N/A N/A N/A N/A InputReference Ground NC/144M NC/288M VREF VDD VSS VDDQ Power Supply Power supply inputs to the core of the device. Power Supply Power supply inputs for the outputs of the device. All synchronous data inputs (D[x:0]) inputs pass through input registers controlled by the input clocks (K and K). All synchronous data outputs (Q[x:0]) outputs pass through output registers controlled by the rising edge of the output clocks (C and C or K and K when in single-clock mode). All synchronous control (RPS, WPS, BWS[x:0]) inputs pass through input registers controlled by the rising edge of the input clocks (K and K). CY7C1313BV18 is described in the following sections. The same basic descriptions apply to CY7C1311BV18, CY7C1911BV18, and CY7C1315BV18. Read Operations The CY7C1313BV18 is organized internally as 4 arrays of 256K x 18. Accesses are completed in a burst of four sequential 18-bit data words. Read operations are initiated by asserting RPS active at the rising edge of the Positive Input Clock (K). The address presented to Address inputs are stored in the Read address register. Following the next K clock rise, the corresponding lowest order 18-bit word of data is driven onto the Q[17:0] using C as the output timing reference. On the subsequent rising edge of C the next 18-bit data word is driven onto the Q[17:0]. This process continues until all four 18-bit data Page 7 of 23 Functional Overview The CY7C1311BV18, CY7C1911BV18, CY7C1313BV18, CY7C1315BV18 are synchronous pipelined Burst SRAMs equipped with both a Read port and a Write port. The Read port is dedicated to Read operations and the Write port is dedicated to Write operations. Data flows into the SRAM through the Write port and out through the Read port. These devices multiplex the address inputs in order to minimize the number of address pins required. By having separate Read and Write ports, the QDR-II completely eliminates the need to “turn-around” the data bus and avoids any possible data contention, thereby simplifying system design. Each access consists of four 8-bit data transfers in the case of CY7C1311BV18, four 9-bit data transfers in the case of CY7C1911BV18, four 18-bit data transfers in the case of CY7C1313BV18, and four 36-bit data in the case of CY7C1315BV18 transfers in two clock cycles. Accesses for both ports are initiated on the Positive Input Clock (K). All synchronous input timing is referenced from the rising edge of the input clocks (K and K) and all output timing is referenced to the output clocks (C and C or K and K when in single clock mode). Document Number: 38-05620 Rev. ** PRELIMINARY words have been driven out onto Q[17:0]. The requested data will be valid 0.45 ns from the rising edge of the output clock (C or C or (K or K when in single-clock mode)). In order to maintain the internal logic, each read access must be allowed to complete. Each Read access consists of four 18-bit data words and takes 2 clock cycles to complete. Therefore, Read accesses to the device can not be initiated on two consecutive K clock rises. The internal logic of the device will ignore the second Read request. Read accesses can be initiated on every other K clock rise. Doing so will pipeline the data flow such that data is transferred out of the device on every rising edge of the output clocks (C and C or K and K when in single-clock mode). When the read port is deselected, the CY7C1313BV18 will first complete the pending Read transactions. Synchronous internal circuitry will automatically tri-state the outputs following the next rising edge of the Positive Output Clock (C). This will allow for a seamless transition between devices without the insertion of wait states in a depth expanded memory. Write Operations Write operations are initiated by asserting WPS active at the rising edge of the Positive Input Clock (K). On the following K clock rise the data presented to D[17:0] is latched and stored into the lower 18-bit Write Data register, provided BWS[1:0] are both asserted active. On the subsequent rising edge of the Negative Input Clock (K) the information presented to D[17:0] is also stored into the Write Data register, provided BWS[1:0] are both asserted active. This process continues for one more cycle until four 18-bit words (a total of 72 bits) of data are stored in the SRAM. The 72 bits of data are then written into the memory array at the specified location. Therefore, Write accesses to the device can not be initiated on two consecutive K clock rises. The internal logic of the device will ignore the second Write request. Write accesses can be initiated on every other rising edge of the Positive Input Clock (K). Doing so will pipeline the data flow such that 18 bits of data can be transferred into the device on every rising edge of the input clocks (K and K). When deselected, the Write port will ignore all inputs after the pending Write operations have been completed. Byte Write Operations Byte Write operations are supported by the CY7C1313BV18. A Write operation is initiated as described in the Write Operations section above. The bytes that are written are determined by BWS0 and BWS1, which are sampled with each set of 18-bit data words. Asserting the appropriate Byte Write Select input during the data portion of a Write will allow the data being presented to be latched and written into the device. Deasserting the Byte Write Select input during the data portion of a write will allow the data stored in the device for that byte to remain unaltered. This feature can be used to simplify Read/Modify/Write operations to a Byte Write operation. Single Clock Mode The CY7C1313BV18 can be used with a single clock that controls both the input and output registers. In this mode the device will recognize only a single pair of input clocks (K and K) that control both the input and output registers. This operation is identical to the operation if the device had zero skew between the K/K and C/C clocks. All timing parameters remain the same in this mode. To use this mode of operation, Document Number: 38-05620 Rev. ** CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18 the user must tie C and C HIGH at power on. This function is a strap option and not alterable during device operation. Concurrent Transactions The Read and Write ports on the CY7C1313BV18 operate completely independently of one another. Since each port latches the address inputs on different clock edges, the user can Read or Write to any location, regardless of the transaction on the other port. If the ports access the same location when a Read follows a Write in successive clock cycles, the SRAM will deliver the most recent information associated with the specified address location. This includes forwarding data from a Write cycle that was initiated on the previous K clock rise. Read accesses and Write access must be scheduled such that one transaction is initiated on any clock cycle. If both ports are selected on the same K clock rise, the arbitration depends on the previous state of the SRAM. If both ports were deselected, the Read port will take priority. If a Read was initiated on the previous cycle, the Write port will assume priority (since Read operations can not be initiated on consecutive cycles). If a Write was initiated on the previous cycle, the Read port will assume priority (since Write operations can not be initiated on consecutive cycles). Therefore, asserting both port selects active from a deselected state will result in alternating Read/Write operations being initiated, with the first access being a Read. Depth Expansion The CY7C1313BV18 has a Port Select input for each port. This allows for easy depth expansion. Both Port Selects are sampled on the rising edge of the Positive Input Clock only (K). Each port select input can deselect the specified port. Deselecting a port will not affect the other port. All pending transactions (Read and Write) will be completed prior to the device being deselected. Programmable Impedance An external resistor, RQ, must be connected between the ZQ pin on the SRAM and VSS to allow the SRAM to adjust its output driver impedance. The value of RQ must be 5X the value of the intended line impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching with a tolerance of ±15% is between 175Ω and 350Ω, with VDDQ = 1.5V. The output impedance is adjusted every 1024 cycles upon power-up to account for drifts in supply voltage and temperature. Echo Clocks Echo clocks are provided on the QDR-II to simplify data capture on high-speed systems. Two echo clocks are generated by the QDR-II. CQ is referenced with respect to C and CQ is referenced with respect to C. These are free running clocks and are synchronized to the output clock of the QDR-II. In the single clock mode, CQ is generated with respect to K and CQ is generated with respect to K. The timings for the echo clocks are shown in the AC Timing table. DLL These chips utilize a Delay Lock Loop (DLL) that is designed to function between 80 MHz and the specified maximum clock frequency. The DLL may be disabled by applying ground to the DOFF pin. The DLL can also be reset by slowing the cycle time of input clocks K and K to greater than 30 ns. Page 8 of 23 PRELIMINARY Application Example[1] SRAM #1 Vt R D A R P S # W P S # B W S # R = 250ohms R P S # CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18 ZQ CQ/CQ# Q C C# K K# SRAM #4 D A W P S # B W S # ZQ R = 250ohms CQ/CQ# Q C C# K K# DATA IN DATA OUT Address RPS# BUS WPS# MASTER BWS# (CPU CLKIN/CLKIN# or Source K ASIC) Source K# Delayed K Delayed K# R R = 50ohms Vt = Vddq/2 R Vt Vt Truth Table[2, 3, 4, 5, 6, 7] Operation K L-H Write Cycle: Load address on the rising edge of K; input write data on two consecutive K and K rising edges. L-H Read Cycle: Load address on the rising edge of K; wait one and a half cycle; read data on two consecutive C and C rising edges. NOP: No Operation L-H Standby: Clock Stopped Stopped RPS H[8] WPS L[9] DQ D(A) at K(t+1) ↑ DQ D(A + 1) at K(t+1) ↑ DQ DQ D(A + 2) at K(t + D(A + 3) at 2) ↑ K(t +2) ↑ L[9] X Q(A) at C(t +1)↑ Q(A + 1) at C(t + 2) ↑ Q(A + 2) at C(t Q(A + 3) at C(t + 2)↑ + 3) ↑ H X H X D=X D=X D=X D=X Q = High-Z Q = High-Z Q = High-Z Q = High-Z Previous State Previous State Previous State Previous State [2, 10] Write Cycle Descriptions CY7C1311BV18 and CY7C1313BV18) BWS0/NWS0 BWS1/NWS1 K L L L–H K – L L – Comments During the Data portion of a Write sequence: CY7C1311BV18 − both nibbles (D[7:0]) are written into the device, CY7C1313BV18 − both bytes (D[17:0]) are written into the device. L-H During the Data portion of a Write sequence: CY7C1311BV18 − both nibbles (D[7:0]) are written into the device, CY7C1313BV18 − both bytes (D[17:0]) are written into the device. Notes: 1. The above application shows four QDR-II being used. 2. X = “Don't Care,” H = Logic HIGH, L = Logic LOW, ↑ represents rising edge. 3. Device will power-up deselected and the outputs in a tri-state condition. 4. “A” represents address location latched by the devices when transaction was initiated. A + 1, A + 2, and A +3 represents the address sequence in the burst. 5. “t” represents the cycle at which a Read/write operation is started. t + 1, t + 2, and t + 3 are the first, second and third clock cycles respectively succeeding the “t” clock cycle. 6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode. 7. It is recommended that K = K and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically. 8. If this signal was LOW to initiate the previous cycle, this signal becomes a “Don’t Care” for this operation. 9. This signal was HIGH on previous K clock rise. Initiating consecutive Read or Write operations on consecutive K clock rises is not permitted. The device will ignore the second Read or Write request. 10. Assumes a Write cycle was initiated per the Write Port Cycle Description Truth Table. NWS0, NWS1, BWS0, BWS1, BWS2 and BWS3 can be altered on different portions of a Write cycle, as long as the set-up and hold requirements are achieved. Document Number: 38-05620 Rev. ** Page 9 of 23 PRELIMINARY Write Cycle Descriptions CY7C1311BV18 and CY7C1313BV18) (continued)[2, 10] BWS0/NWS0 BWS1/NWS1 K L H L–H K – CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18 L H H L H L H H H H Comments During the Data portion of a Write sequence : CY7C1311BV18 − only the lower nibble (D[3:0]) is written into the device. D[7:4] will remain unaltered, CY7C1313BV18 − only the lower byte (D[8:0]) is written into the device. D[17:9] will remain unaltered. – L–H During the Data portion of a Write sequence : CY7C1311BV18 − only the lower nibble (D[3:0]) is written into the device. D[7:4] will remain unaltered, CY7C1313BV18 − only the lower byte (D[8:0]) is written into the device. D[17:9] will remain unaltered. L–H – During the Data portion of a Write sequence : CY7C1311BV18 − only the upper nibble (D[7:4]) is written into the device. D[3:0] will remain unaltered, CY7C1313BV18 − only the upper byte (D[17:9]) is written into the device. D[8:0] will remain unaltered. – L–H During the Data portion of a Write sequence : CY7C1311BV18 − only the upper nibble (D[7:4]) is written into the device. D[3:0] will remain unaltered, CY7C1313BV18 − only the upper byte (D[17:9]) is written into the device. D[8:0] will remain unaltered. L–H – No data is written into the devices during this portion of a write operation. – L–H No data is written into the devices during this portion of a write operation. Write Cycle Descriptions[2, 10](CY7C1315BV18) BWS0 BWS1 BWS2 BWS3 L L L L L L L H H H H H H H H L H H L L H H H H H H L H H H H L L H H H H L H H H H H H L L H H K L–H – L–H – L–H – L–H – L–H – L–H – L–H – L–H K – L–H – L–H – L–H – L–H Comments During the Data portion of a Write sequence, all four bytes (D[35:0]) are written into the device. During the Data portion of a Write sequence, all four bytes (D[35:0]) are written into the device. During the Data portion of a Write sequence, only the lower byte (D[8:0]) is written into the device. D[35:9] will remain unaltered. During the Data portion of a Write sequence, only the lower byte (D[8:0]) is written into the device. D[35:9] will remain unaltered. During the Data portion of a Write sequence, only the byte (D[17:9]) is written into the device. D[8:0] and D[35:18] will remain unaltered. During the Data portion of a Write sequence, only the byte (D[17:9]) is written into the device. D[8:0] and D[35:18] will remain unaltered. During the Data portion of a Write sequence, only the byte (D[26:18]) is written into the device. D[17:0] and D[35:27] will remain unaltered. During the Data portion of a Write sequence, only the byte (D[26:18]) is written into the device. D[17:0] and D[35:27] will remain unaltered. During the Data portion of a Write sequence, only the byte (D[35:27]) is written into the device. D[26:0] will remain unaltered. During the Data portion of a Write sequence, only the byte (D[35:27]) is written into the device. D[26:0] will remain unaltered. No data is written into the device during this portion of a write operation. No data is written into the device during this portion of a write operation. Write Cycle Descriptions[2, 10] (CY7C1911BV18) BWS0 L L H H K L–H – L–H – K – L–H – L–H During the Data portion of a Write sequence, the single byte (D[8:0]) is written into the device. During the Data portion of a Write sequence, the single byte (D[8:0]) is written into the device. No data is written into the device during this portion of a write operation. No data is written into the device during this portion of a write operation. Page 10 of 23 Document Number: 38-05620 Rev. ** PRELIMINARY Maximum Ratings (Above which the useful life may be impaired.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied .... –10°C to +85°C Supply Voltage on VDD Relative to GND........ –0.5V to +2.9V DC Applied to Outputs in High-Z .........–0.5V to VDDQ + 0.3V DC Input Voltage[14] ............................ –0.5V to VDDQ + 0.3V Current into Outputs (LOW) .........................................20 mA Range Com’l CY7C1311BV18 CY7C1911BV18 CY7C1313BV18 CY7C1315BV18 Static Discharge Voltage (MIL-STD-883, M. 3015)... >2001V Latch-up Current..................................................... >200 mA Operating Range Ambient Temperature (TA) 0°C to +70°C VDD[15] 1.8 ± 0.1V VDDQ[15] 1.4V to VDD DC Electrical Characteristics Over the Operating Range[11] Parameter VDD VDDQ VOH VOL VOH(LOW) VOL(LOW) VIH VIL IX IOZ VREF IDD Description Power Supply Voltage I/O Supply Voltage Output HIGH Voltage Output LOW Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage[14] Input LOW Voltage[14] Input Load Current Output Leakage Current Input Reference Voltage[16] VDD Operating Supply GND ≤ VI ≤ VDDQ GND ≤ VI ≤ VDDQ, Output Disabled Typical Value = 0.75V VDD = Max., IOUT = 0 mA, 167 MHz f = fMAX = 1/tCYC 200 MHz 250 MHz ISB1 Automatic Power-down Current 167 MHz Max. VDD, Both Ports Deselected, VIN ≥ VIH or 200 MHz VIN ≤ VIL 250 MHz f = fMAX = 1/tCYC, Inputs Static Note 12 Note 13 IOH = −0.1 mA, Nominal Impedance IOL = 0.1 mA, Nominal Impedance Test Conditions Min. 1.7 1.4 VDDQ/2 – 0.12 VDDQ/2 – 0.12 VDDQ – 0.2 VSS VREF + 0.1 –0.3 −5 −5 0.68 0.75 Typ. 1.8 1.5 Max. 1.9 VDD VDDQ/2 + 0.12 VDDQ/2 + 0.12 VDDQ 0.2 VDDQ + 0.3 VREF – 0.1 5 5 0.95 TBD TBD TBD TBD TBD TBD Unit V V V V V V V V µA µA V mA mA mA mA mA mA Notes: 11. All Voltage referenced to Ground. 12. Output are impedance controlled. IOH = −(VDDQ/2)/(RQ/5) for values of 175Ω