CY7C1312CV18-167BZXI

PRELIMINARY CY7C1310CV18 CY7C1910CV18 CY7C1312CV18 CY7C1314CV18 18-Mbit QDR-II™ SRAM 2-Word Burst Architecture Features • Separate Independent Read and Write data ports — Supports concurrent transactions • 250-MHz clock for high bandwidth • 2-Word Burst on all accesses • Double Data Rate (DDR) interfaces on both Read and Write ports (data transferred at 500 MHz) @ 250 MHz • Two input clocks (K and K) for precise DDR timing — SRAM uses rising edges only • Two input clocks for output data (C and C) to minimize clock-skew and flight-time mismatches • Echo clocks (CQ and CQ) simplify data capture in high-speed systems • Single multiplexed address input bus latches address inputs for both Read and Write ports • Separate Port Selects for depth expansion • Synchronous internally self-timed writes • QDR-II operates with 1.5 cycle read latency when the DLL is enabled • Operates like a QDR-I device with 1 cycle read latency in DLL off mode • Available in x 8, x 9, x 18, and x 36 configurations • Full data coherency, providing most current data • Core VDD = 1.8V (±0.1V); I/O VDDQ = 1.4V to VDD • Available in 165-ball FBGA package (13 x 15 x 1.4 mm) • Offered in both lead-free and non-lead free packages • Variable drive HSTL output buffers • JTAG 1149.1 compatible test access port • Delay Lock Loop (DLL) for accurate data placement Functional Description The CY7C1310CV18, CY7C1910CV18, CY7C1312CV18 and CY7C1314CV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR™-II architecture. QDR-II architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to support Read operations and the Write Port has dedicated Data Inputs to support Write operations. QDR-II architecture has separate data inputs and data outputs to completely eliminate the need to “turn-around” the data bus required with common I/O devices. Access to each port is accomplished through a common address bus. The Read address is latched on the rising edge of the K clock and the Write address is latched on the rising edge of the K clock. Accesses to the QDR-II Read and Write ports are completely independent of one another. In order to maximize data throughput, both Read and Write ports are equipped with Double Data Rate (DDR) interfaces. Each address location is associated with two 8-bit words (CY7C1310CV18) or 9-bit words (CY7C1910CV18) or 18-bit words (CY7C1312CV18) or 36-bit words (CY7C1314CV18) that burst sequentially into or out of the device. Since data can be transferred into and out of the device on every rising edge of both input clocks (K and K and C and C), memory bandwidth is maximized while simplifying system design by eliminating bus “turn-arounds.” Depth expansion is accomplished with Port Selects for each port. Port selects allow each port to operate independently. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C (or K or K in a single clock domain) input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry. Configurations CY7C1310CV18 – 2M x 8 CY7C1910CV18 – 2M x 9 CY7C1312CV18 – 1M x 18 CY7C1314CV18 – 512K x 36 Cypress Semiconductor Corporation Document #: 001-07164 Rev. *B • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised September 20, 2006 [+] Feedback PRELIMINARY Logic Block Diagram (CY7C1310CV18) D[7:0] 8 Write Reg Write Add. Decode CY7C1310CV18 CY7C1910CV18 CY7C1312CV18 CY7C1314CV18 A(19:0) 20 Read Add. Decode Address Register Write Reg 1M x 8 Array Address Register 20 A(19:0) 1M x 8 Array K K CLK Gen. Control Logic RPS C C DOFF Read Data Reg. 16 Control Logic 8 Reg. 8 Reg. 8 Reg. CQ CQ VREF WPS NWS[1:0] 8 8 Q[7:0] Logic Block Diagram (CY7C1910CV18) D[8:0] 9 Write Reg Write Add. Decode A(19:0) 20 Read Add. Decode Address Register Write Reg 1M x 9 Array Address Register 20 A(19:0) 1M x 9 Array K K CLK Gen. Control Logic RPS C C DOFF Read Data Reg. 18 Control Logic 9 9 Reg. Reg. 9 Reg. 9 CQ CQ VREF WPS BWS[0] 9Q [8:0] Document #: 001-07164 Rev. *B Page 2 of 26 [+] [+] Feedback PRELIMINARY Logic Block Diagram (CY7C1312CV18) D[17:0] 18 Write Reg Write Add. Decode CY7C1310CV18 CY7C1910CV18 CY7C1312CV18 CY7C1314CV18 A(18:0) 19 Read Add. Decode Address Register Write Reg 512K x 18 Array Address Register 19 A(18:0) 512K x 18 Array K K CLK Gen. Control Logic RPS C C DOFF Read Data Reg. 36 Control Logic 18 Reg. 18 Reg. 18 Reg. CQ CQ VREF WPS BWS[1:0] 18 18 Q[17:0] Logic Block Diagram (CY7C1314CV18) D[35:0] 36 Write Reg Write Add. Decode A(17:0) 18 Read Add. Decode Address Register Write Reg 256K x 36 Array Address Register 18 A(17:0) 256K x 36 Array K K CLK Gen. Control Logic RPS C C DOFF Read Data Reg. 72 Control Logic 36 Reg. 36 Reg. 36 Reg. CQ CQ VREF WPS BWS[3:0] 36 36 Q[35:0] Selection Guide 250 MHz Maximum Operating Frequency Maximum Operating Current 250 600 200 MHz 200 550 167 MHz 167 500 Unit MHz mA Document #: 001-07164 Rev. *B Page 3 of 26 [+] [+] Feedback PRELIMINARY Pin Configurations 165-ball FBGA (13 x 15 x 1.4 mm) Pinout CY7C1310CV18 (2M x 8) CY7C1310CV18 CY7C1910CV18 CY7C1312CV18 CY7C1314CV18 1 A B C D E F G H J K L M N P R CQ NC NC NC NC NC NC DOFF NC NC NC NC NC NC TDO 2 NC/72M NC NC D4 NC NC D5 VREF NC NC Q6 NC D7 NC TCK 3 A NC NC NC Q4 NC Q5 VDDQ NC NC D6 NC NC Q7 A 4 WPS A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 5 NWS1 NC/288M A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 6 K K A VSS VSS VSS VSS VSS VSS VSS VSS VSS A C C 7 NC/144M NWS0 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 8 RPS A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 9 A NC NC NC NC NC NC VDDQ NC NC NC NC NC NC A 10 NC/36M NC NC NC D2 NC NC VREF Q1 NC NC NC NC NC TMS 11 CQ Q3 D3 NC Q2 NC NC ZQ D1 NC Q0 D0 NC NC TDI CY7C1910CV18 (2M x 9) 1 A B C D E F G H J K L M N P R CQ NC NC NC NC NC NC DOFF NC NC NC NC NC NC TDO 2 NC/72M NC NC D5 NC NC D6 VREF NC NC Q7 NC D8 NC TCK 3 A NC NC NC Q5 NC Q6 VDDQ NC NC D7 NC NC Q8 A 4 WPS A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 5 NC NC/288M A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 6 K K A VSS VSS VSS VSS VSS VSS VSS VSS VSS A C C 7 NC/144M BWS0 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 8 RPS A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 9 A NC NC NC NC NC NC VDDQ NC NC NC NC NC NC A 10 NC/36M NC NC NC D3 NC NC VREF Q2 NC NC NC NC D0 TMS 11 CQ Q4 D4 NC Q3 NC NC ZQ D2 NC Q1 D1 NC Q0 TDI Document #: 001-07164 Rev. *B Page 4 of 26 [+] [+] Feedback PRELIMINARY Pin Configurations (continued) 165-ball FBGA (13 x 15 x 1.4 mm) Pinout CY7C1312CV18 (1M x 18) CY7C1310CV18 CY7C1910CV18 CY7C1312CV18 CY7C1314CV18 1 A B C D E F G H J K L M N P R CQ NC NC NC NC NC NC DOFF NC NC NC NC NC NC TDO 2 Q9 NC D11 NC Q12 D13 VREF NC NC Q15 NC D17 NC TCK 3 D9 D10 Q10 Q11 D12 Q13 VDDQ D14 Q14 D15 D16 Q16 Q17 A 4 WPS A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 5 BWS1 NC A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 6 K K A VSS VSS VSS VSS VSS VSS VSS VSS VSS A C C 7 NC/288M BWS0 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 8 RPS A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 9 A NC NC NC NC NC NC VDDQ NC NC NC NC NC NC A 10 NC/72M NC Q7 NC D6 NC NC VREF Q4 D3 NC Q1 NC D0 TMS 11 CQ Q8 D8 D7 Q6 Q5 D5 ZQ D4 Q3 Q2 D2 D1 Q0 TDI NC/144M NC/36M CY7C1314CV18 (512K x 36) 1 A B C D E F G H J K L M N P R CQ Q27 D27 D28 Q29 Q30 D30 DOFF D31 Q32 Q33 D33 D34 Q35 TDO 2 Q18 Q28 D20 D29 Q21 D22 VREF Q31 D32 Q24 Q34 D26 D35 TCK 3 D18 D19 Q19 Q20 D21 Q22 VDDQ D23 Q23 D24 D25 Q25 Q26 A 4 WPS A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 5 BWS2 BWS3 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 6 K K A VSS VSS VSS VSS VSS VSS VSS VSS VSS A C C 7 BWS1 BWS0 A VSS VSS VDD VDD VDD VDD VDD VSS VSS A A A 8 RPS A VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS A A 9 D17 D16 Q16 Q15 D14 Q13 VDDQ D12 Q12 D11 D10 Q10 Q9 A 10 Q17 Q7 D15 D6 Q14 D13 VREF Q4 D3 Q11 Q1 D9 D0 TMS 11 CQ Q8 D8 D7 Q6 Q5 D5 ZQ D4 Q3 Q2 D2 D1 Q0 TDI NC/288M NC/72M NC/36M NC/144M Document #: 001-07164 Rev. *B Page 5 of 26 [+] Feedback PRELIMINARY Pin Definitions Pin Name D[x:0] I/O InputSynchronous Pin Description CY7C1310CV18 CY7C1910CV18 CY7C1312CV18 CY7C1314CV18 Data input signals, sampled on the rising edge of K and K clocks during valid write operations. CY7C1310CV18 - D[7:0] CY7C1910CV18 - D[8:0] CY7C1312CV18 - D[17:0] CY7C1314CV18 - D[35:0] Write Port Select, active LOW. Sampled on the rising edge of the K clock. When asserted active, a Write operation is initiated. Deasserting will deselect the Write port. Deselecting the Write port will cause D[x:0] to be ignored. Nibble Write Select 0, 1 − active LOW. (CY7C1310CV18 Only) Sampled on the rising edge of the K and K clocks during Write operations. Used to select which nibble is written into the device during the current portion of the Write operations.Nibbles not written remain unaltered. NWS0 controls D[3:0] and NWS1 controls D[7:4]. All Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble Write Select will cause the corresponding nibble of data to be ignored and not written into the device. WPS InputSynchronous NWS0,NWS1 BWS0, BWS1, BWS2, BWS3 InputSynchronous Byte Write Select 0, 1, 2 and 3 − active LOW. Sampled on the rising edge of the K and K clocks during Write operations. Used to select which byte is written into the device during the current portion of the Write operations. Bytes not written remain unaltered. CY7C1910CV18 − BWS0 controls D[8:0] CY7C1312CV18 − BWS0 controls D[8:0], BWS1 controls D[17:9]. CY7C1314CV18 − BWS0 controls D[8:0], BWS1 controls D[17:9],BWS2 controls D[26:18] and BWS3 controls D[35:27]. All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select will cause the corresponding byte of data to be ignored and not written into the device. Address Inputs. Sampled on the rising edge of the K (Read address) and K (Write address) clocks during active Read and Write operations. These address inputs are multiplexed for both Read and Write operations. Internally, the device is organized as 2M x 8 (2 arrays each of 1M x 8) for CY7C1310CV18, 2M x 9 (2 arrays each of 1M x 9) for CY7C1910CV18, 1M x 18 (2 arrays each of 512K x 18) for CY7C1312CV18 and 512K x 36 (2 arrays each of 256K x 36) for CY7C1314CV18. Therefore, only 20 address inputs are needed to access the entire memory array of CY7C1310CV18 and CY7C1910CV18, 19 address inputs for CY7C1312CV18 and 18 address inputs for CY7C1314CV18. These inputs are ignored when the appropriate port is deselected. Data Output signals. These pins drive out the requested data during a Read operation. Valid data is driven out on the rising edge of both the C and C clocks during Read operations or K and K when in single clock mode. When the Read port is deselected, Q[x:0] are automatically tri-stated. CY7C1310CV18 − Q[7:0] CY7C1910CV18 − Q[8:0] CY7C1312CV18 − Q[17:0] CY7C1314CV18 − Q[35:0] Read Port Select, active LOW. Sampled on the rising edge of Positive Input Clock (K). When active, a Read operation is initiated. Deasserting will cause the Read port to be deselected. When deselected, the pending access is allowed to complete and the output drivers are automatically tri-stated following the next rising edge of the C clock. Each read access consists of a burst of two sequential transfers. Positive Input Clock for Output Data. C is used in conjunction with C to clock out the Read data from the device. C and C can be used together to deskew the flight times of various devices on the board back to the controller. See application example for further details. Negative Input Clock for Output Data. C is used in conjunction with C to clock out the Read data from the device. C and C can be used together to deskew the flight times of various devices on the board back to the controller. See application example for further details. A InputSynchronous Q[x:0] OutputsSynchronous RPS InputSynchronous C Input-Clock C Input-Clock Document #: 001-07164 Rev. *B Page 6 of 26 [+] [+] Feedback PRELIMINARY Pin Definitions (continued) Pin Name K I/O Input-Clock Pin Description CY7C1310CV18 CY7C1910CV18 CY7C1312CV18 CY7C1314CV18 Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device and to drive out data through Q[x:0] when in single clock mode. All accesses are initiated on the rising edge of K. Negative Input Clock Input. K is used to capture synchronous inputs being presented to the device and to drive out data through Q[x:0] when in single clock mode. CQ is referenced with respect to C. This is a free running clock and is synchronized to the input clock for output data (C) of the QDR-II. In the single clock mode, CQ is generated with respect to K. The timings for the echo clocks are shown in the AC Timing table. CQ is referenced with respect to C. This is a free running clock and is synchronized to the input clock for output data (C) of the QDR-II. In the single clock mode, CQ is generated with respect to K. The timings for the echo clocks are shown in the AC Timing table. Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 x RQ, where RQ is a resistor connected between ZQ and ground. Alternatively, this pin can be connected directly to VDDQ, which enables the minimum impedance mode. This pin cannot be connected directly to GND or left unconnected. DLL Turn Off - Active LOW. Connecting this pin to ground will turn off the DLL inside the device. The timings in the DLL turned off operation will be different from those listed in this data sheet. For normal operation, this pin can be connected to a pull-up through a 10-Kohm or less pull-up resistor. The device will behave in QDR-I mode when the DLL is turned off. In this mode, the device can be operated at a frequency of up to 167 MHz with QDR-I timing. TDO for JTAG. TCK pin for JTAG. TDI pin for JTAG. TMS pin for JTAG. Not connected to the die. Can be tied to any voltage level. Not connected to the die. Can be tied to any voltage level. Not connected to the die. Can be tied to any voltage level. Not connected to the die. Can be tied to any voltage level. Not connected to the die. Can be tied to any voltage level. Reference Voltage Input. Static input used to set the reference level for HSTL inputs and Outputs as well as AC measurement points. Power supply inputs to the core of the device. Ground for the device. Power supply inputs for the outputs of the device. consists of two 8-bit data transfers in the case CY7C1310CV18, two 9-bit data transfers in the case CY7C1910CV18,two 18-bit data transfers in the case CY7C1312CV18 and two 36-bit data transfers in the case CY7C1314CV18, in one clock cycle. of of of of K CQ Input-Clock Echo Clock CQ Echo Clock ZQ Input DOFF Input TDO TCK TDI TMS NC NC/36M NC/72M NC/144M NC/288M VREF VDD VSS VDDQ Output Input Input Input N/A N/A N/A N/A N/A InputReference Power Supply Ground Power Supply Functional Overview The CY7C1310CV18, CY7C1910CV18, CY7C1312CV18 and CY7C1314CV18 are synchronous pipelined Burst SRAMs equipped with both a Read port and a Write port. The Read port is dedicated to Read operations and the Write port is dedicated to Write operations. Data flows into the SRAM through the Write port and out through the Read port. These devices multiplex the address inputs in order to minimize the number of address pins required. By having separate Read and Write ports, the QDR-II completely eliminates the need to “turn-around” the data bus and avoids any possible data contention, thereby simplifying system design. Each access This device operates with a read latency of one and half cycles when DOFF pin is tied HIGH. When DOFF pin is set LOW or connected to VSS then the device will behave in QDR-I mode with a read latency of one clock cycle. Accesses for both ports are initiated on the rising edge of the positive Input Clock (K). All synchronous input timings are referenced from the rising edge of the input clocks (K and K) Document #: 001-07164 Rev. *B Page 7 of 26 [+] [+] Feedback PRELIMINARY and all output timings are referenced to the rising edge of output clocks (C and C or K and K when in single clock mode). All synchronous data inputs (D[x:0]) inputs pass through input registers controlled by the input clocks (K and K). All synchronous data outputs (Q[x:0]) outputs pass through output registers controlled by the rising edge of the output clocks (C and C or K and K when in single clock mode). All synchronous control (RPS, WPS, BWS[x:0]) inputs pass through input registers controlled by the rising edge of the input clocks (K and K). CY7C1312CV18 is described in the following sections. The same basic descriptions apply to CY7C1310CV18 CY7C1910CV18 and CY7C1314CV18. Read Operations The CY7C1312CV18 is organized internally as 2 arrays of 512K x 18. Accesses are completed in a burst of two sequential 18-bit data words. Read operations are initiated by asserting RPS active at the rising edge of the Positive Input Clock (K). The address is latched on the rising edge of the K Clock. The address presented to Address inputs is stored in the Read address register. Following the next K clock rise the corresponding lowest order 18-bit word of data is driven onto the Q[17:0] using C as the output timing reference. On the subsequent rising edge of C, the next 18-bit data word is driven onto the Q[17:0]. The requested data will be valid 0.45 ns from the rising edge of the output clock (C and C or K and K when in single clock mode). Synchronous internal circuitry will automatically tri-state the outputs following the next rising edge of the Output Clocks (C/C). This will allow for a seamless transition between devices without the insertion of wait states in a depth expanded memory. Write Operations Write operations are initiated by asserting WPS active at the rising edge of the Positive Input Clock (K). On the same K clock rise, the data presented to D[17:0] is latched and stored into the lower 18-bit Write Data register provided BWS[1:0] are both asserted active. On the subsequent rising edge of the Negative Input Clock (K), the address is latched and the information presented to D[17:0] is stored into the Write Data register provided BWS[1:0] are both asserted active. The 36 bits of data are then written into the memory array at the specified location. When deselected, the write port will ignore all inputs after the pending Write operations have been completed. Byte Write Operations Byte Write operations are supported by the CY7C1312CV18. A Write operation is initiated as described in the Write Operations section above. The bytes that are written are determined by BWS0 and BWS1, which are sampled with each 18-bit data word. Asserting the appropriate Byte Write Select input during the data portion of a Write will allow the data being presented to be latched and written into the device. Deasserting the Byte CY7C1310CV18 CY7C1910CV18 CY7C1312CV18 CY7C1314CV18 Write Select input during the data portion of a write will allow the data stored in the device for that byte to remain unaltered. This feature can be used to simplify Read/Modify/Write operations to a Byte Write operation. Single Clock Mode The CY7C1312CV18 can be used with a single clock that controls both the input and output registers. In this mode, the device will recognize only a single pair of input clocks (K and K) that control both the input and output registers. This operation is identical to the operation if the device had zero skew between the K/K and C/C clocks. All timing parameters remain the same in this mode. To use this mode of operation, the user must tie C and C HIGH at power on. This function is a strap option and not alterable during device operation. Concurrent Transactions The Read and Write ports on the CY7C1312CV18 operate completely independently of one another. Since each port latches the address inputs on different clock edges, the user can Read or Write to any location, regardless of the transaction on the other port. Also, reads and writes can be started in the same clock cycle. If the ports access the same location at the same time, the SRAM will deliver the most recent information associated with the specified address location. This includes forwarding data from a Write cycle that was initiated on the previous K clock rise. Depth Expansion The CY7C1312CV18 has a Port Select input for each port. This allows for easy depth expansion. Both Port Selects are sampled on the rising edge of the Positive Input Clock only (K). Each port select input can deselect the specified port. Deselecting a port will not affect the other port. All pending transactions (Read and Write) will be completed prior to the device being deselected. Programmable Impedance An external resistor, RQ, must be connected between the ZQ pin on the SRAM and VSS to allow the SRAM to adjust its output driver impedance. The value of RQ must be 5x the value of the intended line impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching with a tolerance of ±15% is between 175Ω and 350Ω, with VDDQ = 1.5V.The output impedance is adjusted every 1024 cycles upon power-up to account for drifts in supply voltage and temperature. Echo Clocks Echo clocks are provided on the QDR-II to simplify data capture on high-speed systems. Two echo clocks are generated by the QDR-II. CQ is referenced with respect to C and CQ is referenced with respect to C. These are free-running clocks and are synchronized to the output clock (C/C) of the QDR-II. In the single clock mode, CQ is generated with respect to K and CQ is generated with respect to K. The timings for the echo clocks are shown in the AC Timing table. Document #: 001-07164 Rev. *B Page 8 of 26 [+] [+] Feedback PRELIMINARY DLL These chips utilize a Delay Lock Loop (DLL) that is designed to function between 80 MHz and the specified maximum clock frequency. During power-up, when the DOFF is tied HIGH, the DLL gets locked after 1024 cycles of stable clock. The DLL can also be reset by slowing or stopping the input clock K and K for a minimum of 30 ns. However, it is not necessary for the DLL to be specifically reset in order to lock the DLL to the desired frequency. The DLL will automatically lock 1024 clock cycles after a stable clock is presented. The DLL may be disabled by applying ground to the DOFF pin. When the DLL is turned off, the device will behave in QDR-I mode (with one cycle latency and a longer access time). For information refer to the application note “DLL Considerations in QDRII/DDRII”. CY7C1310CV18 CY7C1910CV18 CY7C1312CV18 CY7C1314CV18 Application Example[1] SRAM #1 Vt R D A R P S # W P S # B W S # ZQ CQ/CQ# Q C C# K K# R = 250οηµσ R P S # SRAM #4 D A W P S # B W S # ZQ R = 250οηµσ CQ/CQ# Q C C# K K# DATA IN DATA OUT Address RPS# BUS WPS# MASTER BWS# (CPU CLKIN/CLKIN# or Source K ASIC) Source K# Delayed K Delayed K# R R = 50οηµσ Vt = Vddq/2 R Vt Vt Truth Table[2, 3, 4, 5, 6, 7] Operation Write Cycle: Load address on the rising edge of K clock; input write data on K and K rising edges. Read Cycle: Load address on the rising edge of K clock; wait one and a half cycle; read data on C and C rising edges. NOP: No Operation Standby: Clock Stopped K L-H RPS X WPS L DQ D(A + 0) at K(t) ↑ DQ D(A + 1) at K(t) ↑ L-H L X Q(A + 0) at C(t + 1)↑ Q(A + 1) at C(t + 2) ↑ L-H Stopped H X H X D=X Q = High-Z Previous State D=X Q = High-Z Previous State Notes: 1. The above application shows four QDR-II being used. 2. X = “Don't Care,” H = Logic HIGH, L= Logic LOW, ↑represents rising edge. 3. Device will power-up deselected and the outputs in a tri-state condition. 4. “A” represents address location latched by the devices when transaction was initiated. A + 0, A + 1 represents the internal address sequence in the burst. 5. “t” represents the cycle at which a Read/Write operation is started. t + 1 and t + 2 are the first and second clock cycles respectively succeeding the “t” clock cycle. 6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode. 7. It is recommended that K = K and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically. Document #: 001-07164 Rev. *B Page 9 of 26 [+] [+] Feedback PRELIMINARY Write Cycle Descriptions (CY7C1310CV18 and CY7C1312CV18) [2, 8] BWS0/NWS0 L BWS1/NWS1 L K L-H K – Comments CY7C1310CV18 CY7C1910CV18 CY7C1312CV18 CY7C1314CV18 During the Data portion of a Write sequence: CY7C1310CV18 − both nibbles (D[7:0]) are written into the device, CY7C1312CV18 − both bytes (D[17:0]) are written into the device. L L – L-H During the Data portion of a Write sequence: CY7C1310CV18 − both nibbles (D[7:0]) are written into the device, CY7C1312CV18 − both bytes (D[17:0]) are written into the device. – During the Data portion of a Write sequence: CY7C1310CV18 − only the lower nibble (D[3:0]) is written into the device. D[7:4] will remain unaltered, CY7C1312CV18 − only the lower byte (D[8:0]) is written into the device. D[17:9] will remain unaltered. L H L-H L H – L-H During the Data portion of a Write sequence: CY7C1310CV18 − only the lower nibble (D[3:0]) is written into the device. D[7:4] will remain unaltered, CY7C1312CV18 − only the lower byte (D[8:0]) is written into the device. D[17:9] will remain unaltered. – During the Data portion of a Write sequence: CY7C1310CV18 − only the upper nibble (D[7:4]) is written into the device. D[3:0] will remain unaltered, CY7C1312CV18 − only the upper byte (D[17:9]) is written into the device. D[8:0] will remain unaltered. H L L-H H L – L-H During the Data portion of a Write sequence: CY7C1310CV18 − only the upper nibble (D[7:4]) is written into the device. D[3:0] will remain unaltered, CY7C1312CV18 − only the upper byte (D[17:9]) is written into the device. D[8:0] will remain unaltered. – No data is written into the devices during this portion of a Write operation. L-H No data is written into the devices during this portion of a Write operation. H H H H L-H – Note: 8. Assumes a Write cycle was initiated per the Write Port Cycle Description Truth Table. NWS0, NWS1, BWS0, BWS1, BWS2 and BWS3 can be altered on different portions of a Write cycle, as long as the set-up and hold requirements are achieved. Document #: 001-07164 Rev. *B Page 10 of 26 [+] [+] Feedback PRELIMINARY Write Cycle Descriptions (CY7C1314CV18) BWS0 BWS1 BWS2 BWS3 L L L L H H H H H H H H L L H H L L H H H H H H L L H H H H L L H H H H L L H H H H H H L L H H K L-H L-H L-H L-H L-H L-H K [2, 8] CY7C1310CV18 CY7C1910CV18 CY7C1312CV18 CY7C1314CV18 Comments During the Data portion of a Write sequence, all four bytes (D[35:0]) are written into the device. L-H During the Data portion of a Write sequence, all four bytes (D[35:0]) are written into the device. During the Data portion of a Write sequence, only the lower byte (D[8:0]) is written into the device. D[35:9] will remain unaltered. L-H During the Data portion of a Write sequence, only the lower byte (D[8:0]) is written into the device. D[35:9] will remain unaltered. During the Data portion of a Write sequence, only the byte (D[17:9]) is written into the device. D[8:0] and D[35:18] will remain unaltered. L-H During the Data portion of a Write sequence, only the byte (D[17:9]) is written into the device. D[8:0] and D[35:18] will remain unaltered. During the Data portion of a Write sequence, only the byte (D[26:18]) is written into the device. D[17:0] and D[35:27] will remain unaltered. L-H During the Data portion of a Write sequence, only the byte (D[26:18]) is written into the device. D[17:0] and D[35:27] will remain unaltered. During the Data portion of a Write sequence, only the byte (D[35:27]) is written into the device. D[26:0] will remain unaltered. L-H During the Data portion of a Write sequence, only the byte (D[35:27]) is written into the device. D[26:0] will remain unaltered. No data is written into the device during this portion of a Write operation. L-H No data is written into the device during this portion of a Write operation. Write Cycle Descriptions (CY7C1910CV18) [2, 8] BWS0 L L H H K L-H – L-H – K – L-H – L-H Comments During the Data portion of a Write sequence: CY7C1910CV18 − the single byte (D[8:0]) is written into the device During the Data portion of a Write sequence: CY7C1910CV18 − the single byte (D[8:0]) is written into the device, No data is written into the devices during this portion of a Write operation. No data is written into the devices during this portion of a Write operation. Document #: 001-07164 Rev. *B Page 11 of 26 [+] Feedback PRELIMINARY IEEE 1149.1 Serial Boundary Scan (JTAG) These SRAMs incorporate a serial boundary scan test access port (TAP) in the FBGA package. This part is fully compliant with IEEE Standard #1149.1-2001. The TAP operates using JEDEC standard 1.8V I/O logic levels. Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be connected to VDD through a pull-up resistor. TDO should be left unconnected. Upon power-up, the device will come up in a reset state which will not interfere with the operation of the device. Test Access Port—Test Clock The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. Test Mode Select The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this pin unconnected if the TAP is not used. The pin is pulled up internally, resulting in a logic HIGH level. Test Data-In (TDI) The TDI pin is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see the TAP Controller State Diagram. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) on any register. Test Data-Out (TDO) The TDO output pin is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine (see Instruction codes). The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. Performing a TAP Reset A Reset is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating. At power-up, the TAP is reset internally to ensure that TDO comes up in a high-Z state. TAP Registers Registers are connected between the TDI and TDO pins and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction registers. Data is serially loaded into the TDI pin on the rising edge of TCK. Data is output on the TDO pin on the falling edge of TCK. Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the Document #: 001-07164 Rev. *B CY7C1310CV18 CY7C1910CV18 CY7C1312CV18 CY7C1314CV18 TDI and TDO pins as shown in TAP Controller Block Diagram. Upon power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section. When the TAP controller is in the Capture IR state, the two least significant bits are loaded with a binary “01” pattern to allow for fault isolation of the board level serial test path. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between TDI and TDO pins. This allows data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. Boundary Scan Register The boundary scan register is connected to all of the input and output pins on the SRAM. Several no connect (NC) pins are also included in the scan register to reserve pins for higher density devices. The boundary scan register is loaded with the contents of the RAM Input and Output ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO pins when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the Input and Output ring. The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO. Identification (ID) Register The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in the Identification Register Definitions table. TAP Instruction Set Eight different instructions are possible with the three-bit instruction register. All combinations are listed in the Instruction Code table. Three of these instructions are listed as RESERVED and should not be used. The other five instructions are described in detail below. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO pins. To execute the instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state. IDCODE The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO pins and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction Page 12 of 26 [+] [+] Feedback PRELIMINARY is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state. SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO pins when the TAP controller is in a Shift-DR state. The SAMPLE Z command puts the output bus into a High-Z state until the next command is given during the “Update IR” state. SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. The user must be aware that the TAP controller clock can only operate at a frequency up to 20 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output will undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This will not harm the device, but there is no guarantee as to the value that will be captured. Repeatable results may not be possible. To guarantee that the boundary scan register will capture the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller's capture set-up plus hold times (tCS and tCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK captured in the boundary scan register. Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. PRELOAD allows an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells prior to the selection of another boundary scan test operation. The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required—that is, while data captured is shifted out, the preloaded data can be shifted in. BYPASS CY7C1310CV18 CY7C1910CV18 CY7C1312CV18 CY7C1314CV18 When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. EXTEST The EXTEST instruction enables the preloaded data to be driven out through the system output pins. This instruction also selects the boundary scan register to be connected for serial access between the TDI and TDO in the shift-DR controller state. EXTEST OUTPUT BUS TRI-STATE IEEE Standard 1149.1 mandates that the TAP controller be able to put the output bus into a tri-state mode. The boundary scan register has a special bit located at bit #47. When this scan cell, called the “extest output bus tri-state,” is latched into the preload register during the “Update-DR” state in the TAP controller, it will directly control the state of the output (Q-bus) pins, when the EXTEST is entered as the current instruction. When HIGH, it will enable the output buffers to drive the output bus. When LOW, this bit will place the output bus into a High-Z condition. This bit can be set by entering the SAMPLE/PRELOAD or EXTEST command, and then shifting the desired bit into that cell, during the “Shift-DR” state. During “Update-DR”, the value loaded into that shift-register cell will latch into the preload register. When the EXTEST instruction is entered, this bit will directly control the output Q-bus pins. Note that this bit is pre-set LOW to enable the output when the device is powered-up, and also when the TAP controller is in the “Test-Logic-Reset” state. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions. Document #: 001-07164 Rev. *B Page 13 of 26 [+] Feedback PRELIMINARY TAP Controller State Diagram[9] 1 TEST-LOGIC RESET 0 0 TEST-LOGIC/ IDLE 1 SELECT DR-SCAN 0 1 CAPTURE-DR 0 SHIFT-DR 1 EXIT1-DR 0 PAUSE-DR 1 0 EXIT2-DR 1 UPDATE-DR 1 Note: 9. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. CY7C1310CV18 CY7C1910CV18 CY7C1312CV18 CY7C1314CV18 1 1 SELECT IR-SCAN 0 1 CAPTURE-IR 0 0 SHIFT-IR 1 0 1 EXIT1-IR 0 1 0 PAUSE-IR 1 0 EXIT2-IR 1 UPDATE-IR 1 0 0 0 Document #: 001-07164 Rev. *B Page 14 of 26 [+] [+] Feedback PRELIMINARY TAP Controller Block Diagram 0 Bypass Register Selection Circuitry TDI 2 Instruction Register 31 30 29 . . 2 1 0 1 0 CY7C1310CV18 CY7C1910CV18 CY7C1312CV18 CY7C1314CV18 Selection Circuitry TDO Identification Register 106 . . . . 2 1 0 Boundary Scan Register TCK TAP Controller TMS TAP Electrical Characteristics Over the Operating Range [10, 11, 12] Parameter VOH1 VOH2 VOL1 VOL2 VIH VIL IX Description Output HIGH Voltage Output HIGH Voltage Output LOW Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input and OutputLoad Current GND ≤ VI ≤ VDD Test Conditions IOH = −2.0 mA IOH = −100 µA IOL = 2.0 mA IOL = 100 µA 0.65VDD –0.3 −5 Min. 1.4 1.6 0.4 0.2 VDD + 0.3 0.35VDD 5 Max. Unit V V V V V V µA Notes: 10. These characteristic pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics table. 11. Overshoot: VIH(AC) < VDDQ +0.85V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > –1.5V (Pulse width less than tCYC/2). 12. All voltage referenced to Ground. Document #: 001-07164 Rev. *B Page 15 of 26 [+] [+] Feedback PRELIMINARY TAP AC Switching Characteristics Over the Operating Range[13, 14] Parameter tTCYC tTF tTH tTL tTMSS tTDIS tCS Hold Times tTMSH tTDIH tCH tTDOV tTDOX TMS Hold after TCK Clock Rise TDI Hold after Clock Rise Capture Hold after Clock Rise TCK Clock LOW to TDO Valid TCK Clock LOW to TDO Invalid 0 5 5 5 TCK Clock Cycle Time TCK Clock Frequency TCK Clock HIGH TCK Clock LOW TMS Set-up to TCK Clock Rise TDI Set-up to TCK Clock Rise Capture Set-up to TCK Rise Description CY7C1310CV18 CY7C1910CV18 CY7C1312CV18 CY7C1314CV18 Min. 50 20 20 20 5 5 5 Max. Unit ns MHz ns ns ns ns ns ns ns ns 10 ns ns Set-up Times Output Times TAP Timing and Test Conditions[13] 0.9V 50Ω TDO Z0 = 50Ω CL = 20 pF 0V 1.8V 0.9V ALL INPUT PULSES tTH GND tTL (a) Test Clock TCK tTCYC tTMSS tTMSH Test Mode Select TMS tTDIS tTDIH Test Data-In TDI Test Data-Out TDO tTDOV Notes: 13. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns. 14. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register. tTDOX Document #: 001-07164 Rev. *B Page 16 of 26 [+] [+] Feedback PRELIMINARY Identification Register Definitions Value Instruction Field Revision Number (31:29) Cypress Device ID (28:12) Cypress JEDEC ID (11:1) ID Register Presence (0) CY7C1310CV18 001 CY7C1910CV18 001 CY7C1312CV18 001 CY7C1310CV18 CY7C1910CV18 CY7C1312CV18 CY7C1314CV18 CY7C1314CV18 001 Description Version number. 11010011010000101 1101011010001101 11010011010010101 11010011010100101 Defines the type of SRAM. 00000110100 00000110100 00000110100 00000110100 Unique identification of SRAM vendor. Indicates the presence of an ID register. 1 1 1 1 Scan Register Sizes Register Name Instruction Bypass ID Boundary Scan Cells Bit Size 3 1 32 107 Instruction Codes Instruction EXTEST IDCODE SAMPLE Z RESERVED SAMPLE/PRELOAD RESERVED RESERVED BYPASS Code 000 001 010 011 100 101 110 111 Description Captures the Input/Output ring contents. Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operation. Captures the Input/Output contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High-Z state. Do Not Use: This instruction is reserved for future use. Captures the Input/Output ring contents. Places the boundary scan register between TDI and TDO. Does not affect the SRAM operation. Do Not Use: This instruction is reserved for future use. Do Not Use: This instruction is reserved for future use. Places the bypass register between TDI and TDO. This operation does not affect SRAM operation. Document #: 001-07164 Rev. *B Page 17 of 26 [+] [+] Feedback PRELIMINARY Boundary Scan Order Bit # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 Bump ID 6R 6P 6N 7P 7N 7R 8R 8P 9R 11P 10P 10N 9P 10M 11N 9M 9N 11L 11M 9L 10L 11K 10K 9J 9K 10J 11J 11H Bit # 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 Bump ID 10G 9G 11F 11G 9F 10F 11E 10E 10D 9E 10C 11D 9C 9D 11B 11C 9B 10B 11A Internal 9A 8B 7C 6C 8A 7A 7B 6B Bit # 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 Bump ID 6A 5B 5A 4A 5C 4B 3A 1H 1A 2B 3B 1C 1B 3D 3C 1D 2C 3E 2D 2E 1E 2F 3F 1G 1F 3G 2G 1J CY7C1310CV18 CY7C1910CV18 CY7C1312CV18 CY7C1314CV18 Bit # 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 Bump ID 2J 3K 3J 2K 1K 2L 3L 1M 1L 3N 3M 1N 2M 3P 2N 2P 1P 3R 4R 4P 5P 5N 5R Document #: 001-07164 Rev. *B Page 18 of 26 [+] [+] Feedback PRELIMINARY Power-up Sequence in QDR-II SRAM[15] QDR-II SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. Power-up Sequence • Apply power and drive DOFF LOW (All other inputs can be HIGH or LOW) — Apply VDD before VDDQ — Apply VDDQ before VREF or at the same time as VREF • After the power and clock (K, K) are stable take DOFF HIGH • The additional 1024 cycles of clocks are required for the DLL to lock. DLL Constraints CY7C1310CV18 CY7C1910CV18 CY7C1312CV18 CY7C1314CV18 • DLL uses K clock as its synchronizing input. The input should have low phase jitter, which is specified as tKC Var. • The DLL will function at frequencies down to 80 MHz. • If the input clock is unstable and the DLL is enabled, then the DLL may lock onto an incorrect frequency, causing unstable SRAM behavior. To avoid this, provide 1024 cycles stable clock to relock to the desired clock frequency Power-up Waveforms ~ ~ K K ~ ~ Unstable Clock > 1024 Stable clock Start Normal Operation Clock Start (Clock Starts after V DD / V DDQ Stable) VDD / VDDQ DOFF V DD / V DDQ Stable (< +/- 0.1V DC per 50ns ) Fix High (or tied to VDDQ) Note: 15. During Power-up, when the DOFF is tied HIGH, the DLL gets locked after 1024 cycles of stable clock. Document #: 001-07164 Rev. *B Page 19 of 26 [+] [+] Feedback PRELIMINARY Maximum Ratings (Above which the useful life may be impaired.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................... –10°C to +85°C Supply Voltage on VDD Relative to GND........ –0.5V to +2.9V Supply Voltage on VDDQ Relative to GND ...... –0.5V to +VDD DC Voltage Applied to Outputs in High-Z State .................................... –0.5V to VDDQ + 0.3V DC Input Voltage[11] ...............................–0.5V to VDD + 0.3V CY7C1310CV18 CY7C1910CV18 CY7C1312CV18 CY7C1314CV18 Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current.................................................... > 200 mA Operating Range Range Com’l Ind’l Ambient Temperature (TA) 0°C to +70°C –40°C to +85°C VDD[18] 1.8 ± 0.1 V VDDQ[18] 1.4V to VDD Electrical Characteristics Over the Operating Range[12, 18] DC Electrical Characteristics Over the Operating Range Parameter VDD VDDQ VOH VOL VOH(LOW) VOL(LOW) VIH VIL IX IOZ VREF IDD Description Power Supply Voltage I/O Supply Voltage Output HIGH Voltage Output LOW Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage[11] Input LOW Voltage[11] GND ≤ VI ≤ VDDQ GND ≤ VI ≤ VDDQ, Output Disabled VDD = Max., IOUT = 0 mA, f = fMAX = 1/tCYC 167 MHz 200 MHz 250 MHz ISB1 Automatic Power-down Current Max. VDD, Both Ports 167 MHz Deselected, VIN ≥ VIH 200 MHz or VIN ≤ VIL f = fMAX = 250 MHz 1/tCYC, Inputs Static Input Leakage Current Output Leakage Current VDD Operating Supply Note 16 Note 17 IOH = −0.1 mA, Nominal Impedance IOL = 0.1 mA, Nominal Impedance Test Conditions Min. 1.7 1.4 VDDQ/2 – 0.12 VDDQ/2 – 0.12 VDDQ – 0.2 VSS VREF + 0.1 –0.3 −5 −5 0.68 0.75 Typ. 1.8 1.5 Max. 1.9 VDD VDDQ/2 + 0.12 VDDQ/2 + 0.12 VDDQ 0.2 VDDQ+0.3 VREF – 0.1 5 5 0.95 500 550 600 240 260 280 Unit V V V V V V V V µA µA V mA mA mA mA mA mA Input Reference Voltage[19] Typical Value = 0.75V AC Input Requirements Over the Operating Range Parameter VIH VIL Description Input HIGH Voltage Input LOW Voltage Test Conditions Min. VREF + 0.2 – Typ. – – Max. – VREF - 0.2 Unit V V Capacitance[20] Parameter CIN CCLK CO Description Input Capacitance Clock Input Capacitance Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VDD = 1.8V VDDQ = 1.5V Max. 5 6 7 Unit pF pF pF Notes: 16. Outputs are impedance controlled. IOH = –(VDDQ/2)/(RQ/5) for values of 175Ω