CY7C1313AV18-200BZC

CY7C1311AV18 CY7C1313AV18 CY7C1315AV18 PRELIMINARY 18-Mb QDR™-II SRAM 4-Word Burst Architecture Features Functional Description • Separate Independent Read and Write Data Ports — Supports concurrent transactions • 250-MHz Clock for High Bandwidth • 4-Word Burst for reducing address bus frequency • Double Data Rate (DDR) interfaces on both Read and Write Ports (data transferred at 500 MHz) at 250 MHz • Two input clocks (K and K) for precise DDR timing — SRAM uses rising edges only • Two output clocks (C and C) accounts for clock skew and flight time mismatching • Echo clocks (CQ and CQ) simplify data capture in high speed systems • Single multiplexed address input bus latches address inputs for both Read and Write ports • Separate Port Selects for depth expansion • Synchronous internally self-timed writes • Available in ×8, ×18, and ×36 configurations • Full data coherancy providing most current data • Core Vdd=1.8(+/-0.1V);I/O Vddq=1.4V to Vdd) • 13 × 15 x 1.4 mm 1.0-mm pitch FBGA package, 165-ball (11 × 15 matrix) • Variable drive HSTL output buffers • JTAG 1149.1 Compatible test access port • Delay Lock Loop (DLL) for accurate data placement The CY7C1311AV18/CY7C1313AV18/CY7C1315AV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR-II architecture. QDR-II architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to support Read operations and the Write Port has dedicated Data Inputs to support Write operations. QDR-II architecture has separate data inputs and data outputs to completely eliminate the need to “turn-around” the data bus required with common I/O devices. Access to each port is accomplished through a common address bus. Addresses for Read and Write addresses are latched on alternate rising edges of the input (K) clock. Accesses to the QDR-II Read and Write ports are completely independent of one another. In order to maximize data throughput, both Read and Write ports are equipped with Double Data Rate (DDR) interfaces. Each address location is associated with four 8-bit words (CY7C1311AV18) or 18-bit words (CY7C1313AV18) or 36-bit words (CY7C1315AV18) that burst sequentially into or out of the device. Since data can be transferred into and out of the device on every rising edge of both input clocks (K and K and C and C), memory bandwidth is maximized while simplifying system design by eliminating bus “turn-arounds”. Depth expansion is accomplished with Port Selects for each port. Port selects allow each port to operate independently. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry. Configurations CY7C1311AV18–2M x 8 CY7C1313AV18–1M x 18 CY7C1315AV18–512K x 36 Logic Block Diagram (CY7C1311AV18) Write Write Write Write Reg Reg Reg Reg Write Add. Decode CLK Gen. DOFF VREF WPS BWS[1:0] 512K x 8 Array K K 512K x 8 Array 19 512K x 8 Array Address Register 512K x 8 Array A(18:0) 8 Address Register Read Add. Decode D[7:0] RPS Control Logic C C Read Data Reg. 32 CQ 16 Reg. Reg. 8 8 Cypress Semiconductor Corporation Document #: 38-05498 Rev. *A • 3901 North First Street CQ 16 Reg. Control Logic A(18:0) 19 • Q[7:0] San Jose, CA 95134 • 408-943-2600 Revised June 1, 2004 [+] Feedback CY7C1311AV18 CY7C1313AV18 CY7C1315AV18 PRELIMINARY Logic Block Diagram (CY7C1313AV18) D[17:0] DOFF Address Register Read Add. Decode Write Add. Decode CLK Gen. 256K x 18 Array K K 256K x 18 Array 18 Write Write Write Write Reg Reg Reg Reg 256K x 18 Array Address Register 256K x 18 Array A(17:0) 18 18 RPS Control Logic C C Read Data Reg. 72 VREF WPS CQ CQ 36 Reg. Control Logic BWS[1:0] A(17:0) 36 Reg. Reg. 18 18 Q[17:0] Logic Block Diagram (CY7C1315AV18) D[35:0] DOFF VREF WPS BWS[3:0] Address Register Read Add. Decode Write Add. Decode CLK Gen. 128K x 36 Array K K 128K x 36 Array 17 Write Write Write Write Reg Reg Reg Reg 128K x 36 Array Address Register 128K x 36 Array A(16:0) 36 17 RPS Control Logic C C Read Data Reg. 144 Control Logic CQ CQ 72 Reg. 72 A(16:0) Reg. Reg. 36 36 Q [35:0] Selection Guide 250 MHz 200 MHz 167 MHz Unit Maximum Operating Frequency 250 200 167 MHz Maximum Operating Current 800 700 640 mA Document #: 38-05498 Rev. *A Page 2 of 22 [+] Feedback CY7C1311AV18 CY7C1313AV18 CY7C1315AV18 PRELIMINARY Pin Configurations CY7C1311AV18 (2M × 8)–11 × 15 FBGA A B C D E F G H J K L M N P R 1 2 3 4 5 6 7 8 9 10 11 CQ NC VSS/72M A K K VSS/36M CQ NC NC NC D4 NC NC VSS VSS A VSS NC VSS BWS0 A VSS RPS A A NC BWS1 NC/288M NC/144M NC WPS A NC NC Q4 VDDQ VSS VSS NC NC NC NC VDDQ VDD VSS DOFF NC D5 VREF NC Q5 VDDQ NC VDDQ VDDQ VDDQ VDD VDD VDD NC NC Q3 VSS VSS NC NC NC NC D3 NC VSS VDDQ NC D2 Q2 VDD VDD VDD VDD VDDQ VDDQ VDDQ VDDQ NC NC VDDQ NC NC VSS VSS VSS NC VREF Q1 NC NC ZQ D1 NC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC NC Q6 D6 VDDQ VSS VSS VSS VDDQ NC NC Q0 NC NC NC D7 NC NC VSS VSS VSS A VSS A VSS A VSS VSS NC NC NC NC D0 NC NC NC Q7 A A C A A NC NC NC TDO TCK A A A C A A A TMS TDI CY7C1313AV18 (1M × 18)–11 × 15 FBGA 1 A B C D E F G H J K L M N P R CQ NC NC NC 2 3 5 6 7 WPS A BWS1 NC K NC/288M K A Q10 VSS VSS BWS0 A VSS VSS/144M NC/36M Q9 D9 NC D11 D10 4 VSS NC VSS 8 9 10 11 RPS A A VSS/72M CQ NC NC Q8 VSS VSS NC Q7 NC D8 D7 NC NC NC Q11 VDDQ VSS VSS VSS VDDQ NC D6 Q6 NC Q12 D12 VDDQ VDD VSS VDD VDDQ NC NC Q5 NC D13 VREF NC Q13 VDDQ D14 VDDQ VDDQ VDDQ VDD VDD VDD VSS VSS VSS VDD VDD VDD VDDQ VDDQ VDDQ NC VDDQ NC NC VREF Q4 D5 ZQ D4 DOFF NC NC NC Q14 VDDQ VDD VSS VDD VDDQ NC D3 Q3 NC Q15 D15 VDDQ VSS VSS VSS VDDQ NC NC Q2 NC NC NC D17 D16 Q16 VSS VSS VSS A VSS A VSS A VSS VSS NC NC Q1 NC D2 D1 NC NC Q17 A A C A A NC D0 Q0 TDO TCK A A A C A A A TMS TDI Document #: 38-05498 Rev. *A Page 3 of 22 [+] Feedback CY7C1311AV18 CY7C1313AV18 CY7C1315AV18 PRELIMINARY Pin Configurations (continued) CY7C1315AV18 (512K × 36)–11 × 15 FBGA 1 A B C D E F G H J K L M N P R 2 3 VSS/288M NC/72M 4 5 6 7 8 BWS2 K K BWS1 RPS A Q18 D18 WPS A D27 D28 Q28 D20 D19 Q19 VSS VSS Q29 D29 Q20 VDDQ Q30 D30 Q21 D21 D22 VREF Q31 Q22 VDDQ D23 Q32 D32 Q23 Q33 Q24 D24 D33 D34 Q34 D26 Q35 TDO CQ Q27 DOFF D31 9 10 11 NC/36M VSS/144M CQ D17 Q17 Q8 D16 Q16 Q7 D15 D8 D7 Q15 D6 Q6 D14 Q13 VDDQ D12 Q14 VDDQ VDDQ VDDQ D13 VREF Q4 Q5 D5 ZQ D4 VDD VDDQ Q12 D3 Q3 VSS VDDQ D11 Q11 Q2 VSS A VSS A VSS VSS D10 Q10 Q1 D9 D2 D1 A C A A Q9 D0 Q0 A C A A A TMS TDI VSS NC VSS BWS0 A VSS VSS VSS VSS VDDQ VDD VSS VDDQ VDDQ VDDQ VDD VDD VDD VSS VSS VSS VDDQ VDD VDDQ VSS D25 Q25 VSS VSS D35 Q26 TCK A BWS3 A VSS VSS VDDQ VDD VDDQ VDD VDD VDD VSS VSS VSS A A A Pin Definitions Pin Name I/O Pin Description D[x:0] InputData input signals, sampled on the rising edge of K and K clocks during valid write operaSynchronous tions. CY7C1311AV18 − D[7:0] CY7C1313AV18 − D[17:0] CY7C1315AV18 − D[35:0] WPS InputWrite Port Select, active LOW. Sampled on the rising edge of the K clock. When asserted active, Synchronous a write operation is initiated. Deasserting will deselect the Write port. Deselecting the Write port will cause D[x:0] to be ignored. BWS0, BWS1, InputByte Write Select 0, 1, 2 and 3 − active LOW. Sampled on the rising edge of the K and K clocks BWS2, BWS3 Synchronous during write operations. Used to select which byte is written into the device during the current portion of the write operations. Bytes not written remain unaltered. CY7C1311AV18 − BWS0 controls D[3:0] and BWS1 controls D[7:4]. CY7C1313AV18 − BWS0 controls D[8:0] and BWS1 controls D[17:9]. CY7C1315AV18 − BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18] and BWS3 controls D[35:27]. All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select will cause the corresponding byte of data to be ignored and not written into the device. A InputAddress Inputs. Sampled on the rising edge of the K clock during active read and write operaSynchronous tions. These address inputs are multiplexed for both Read and Write operations. Internally, the device is organized as 2M x 8 (4 arrays each of 512K x 8) for CY7C1311AV18, 1M x 18 (4 arrays each of 256K x 18) for CY7C1313AV18 and 512K x 36 (4 arrays each of 128K x 36) for CY7C1315AV18. Therefore, only 19 address inputs are needed to access the entire memory array of CY7C1311AV18, 18 address inputs for CY7C1313AV18 and 17 address inputs for CY7C1315AV18.These inputs are ignored when the appropriate port is deselected. Document #: 38-05498 Rev. *A Page 4 of 22 [+] Feedback PRELIMINARY CY7C1311AV18 CY7C1313AV18 CY7C1315AV18 Pin Definitions (continued) Pin Name I/O Pin Description Q[x:0] OutputsData Output signals. These pins drive out the requested data during a Read operation. Valid Synchronous data is driven out on the rising edge of both the C and C clocks during Read operations or K and K. when in single clock mode. When the Read port is deselected, Q[x:0] are automatically tri-stated. CY7C1311AV18 − Q[7:0] CY7C1313AV18 − Q[17:0] CY7C1315AV18 − Q[35:0] RPS InputRead Port Select, active LOW. Sampled on the rising edge of Positive Input Clock (K). When Synchronous active, a Read operation is initiated. Deasserting will cause the Read port to be deselected. When deselected, the pending access is allowed to complete and the output drivers are automatically tri-stated following the next rising edge of the C clock. Each read access consists of a burst of four sequential transfers. C InputClock Positive Output Clock Input. C is used in conjunction with C to clock out the Read data from the device. C and C can be used together to deskew the flight times of various devices on the board back to the controller. See application example for further details. C InputClock Negative Output Clock Input. C is used in conjunction with C to clock out the Read data from the device. C and C can be used together to deskew the flight times of various devices on the board back to the controller. See application example for further details. K InputClock Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device and to drive out data through Q[x:0] when in single clock mode. All accesses are initiated on the rising edge of K. K InputClock Negative Input Clock Input. K is used to capture synchronous inputs being presented to the device and to drive out data through Q[x:0] when in single clock mode. CQ Echo Clock CQ is referenced with respect to C. This is a free running clock and is synchronized to the output clock(C) of the QDR-II. In the single clock mode, CQ is generated with respect to K. The timings for the echo clocks are shown in the AC timing table. CQ Echo Clock CQ is referenced with respect to C. This is a free running clock and is synchronized to the output clock(C) of the QDR-II. In the single clock mode, CQ is generated with respect to K. The timings for the echo clocks are shown in the AC timing table. ZQ Input Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus impedance. CQ,CQ and Q[x:0] output impedance are set to 0.2 x RQ, where RQ is a resistor connected between ZQ and ground. Alternately, this pin can be connected directly to VDD, which enables the minimum impedance mode. This pin cannot be connected directly to GND or left unconnected. DOFF Input DLL Turn Off - Active LOW. Connecting this pin to ground will turn off the DLL inside the device. The timings in the DLL turned off operation will be different from those listed in this data sheet. More details on this operation can be found in the application note, “DLL Operation in the QDR-II.” TDO Output TCK Input TCK pin for JTAG. TDI Input TDI pin for JTAG. TMS Input TMS pin for JTAG. NC N/A Not connected to the die. Can be tied to any voltage level. NC/36M N/A Address expansion for 36M. This is not connected to the die and so can be tied to any voltage level. NC/72M N/A Address expansion for 72M. This is not connected to the die and so can be tied to any voltage level. VSS/72M Input Address expansion for 72M. This must be tied LOW on the these devices. VSS/144M Input Address expansion for 144M. This must be tied LOW on the these devices. VSS/288M Input Address expansion for 288M. This must be tied LOW on the these devices. Document #: 38-05498 Rev. *A TDO for JTAG. Page 5 of 22 [+] Feedback PRELIMINARY CY7C1311AV18 CY7C1313AV18 CY7C1315AV18 Pin Definitions (continued) Pin Name VREF VDD I/O Pin Description InputReference Reference Voltage Input. Static input used to set the reference level for HSTL inputs and Outputs as well as AC measurement points. Power Supply Power supply inputs to the core of the device. VSS VDDQ Ground Ground for the device. Power Supply Power supply inputs for the outputs of the device. Introduction Functional Overview The CY7C1311AV18/CY7C1313AV18/CY7C1315AV18 are synchronous pipelined Burst SRAMs equipped with both a Read Port and a Write Port. The Read port is dedicated to Read operations and the Write Port is dedicated to Write operations. Data flows into the SRAM through the Write port and out through the Read Port. These devices multiplex the address inputs in order to minimize the number of address pins required. By having separate Read and Write ports, the QDR-II completely eliminates the need to “turn-around” the data bus and avoids any possible data contention, thereby simplifying system design. Each access consists of four 8-bit data transfers in the case of CY7C1311AV18, four 18-bit data transfers in the case of CY7C1313AV18, and four 36-bit data in the case of CY7C1315AV18 transfers in two clock cycles. Accesses for both ports are initiated on the Positive Input Clock (K). All synchronous input timing is referenced from the rising edge of the input clocks (K and K) and all output timing is referenced to the output clocks (C and C or K and K when in single clock mode). All synchronous data inputs (D[x:0]) inputs pass through input registers controlled by the input clocks (K and K). All synchronous data outputs (Q[x:0]) outputs pass through output registers controlled by the rising edge of the output clocks (C and C or K and K when in single-clock mode). All synchronous control (RPS, WPS, BWS[x:0]) inputs pass through input registers controlled by the rising edge of the input clocks (K and K). CY7C1313AV18 is described in the following sections. The same basic descriptions apply to CY7C1311AV18 and CY7C1315AV18. Read Operations The CY7C1313AV18 is organized internally as 4 arrays of 256K x 18. Accesses are completed in a burst of four sequential 18-bit data words. Read operations are initiated by asserting RPS active at the rising edge of the Positive Input Clock (K). The address presented to Address inputs are stored in the Read address register. Following the next K clock rise, the corresponding lowest order 18-bit word of data is driven onto the Q[17:0] using C as the output timing reference. On the subsequent rising edge of C the next 18-bit data word is driven onto the Q[17:0]. This process continues until all four 18-bit data words have been driven out onto Q[17:0]. The requested data will be valid 0.45 ns from the rising edge of the output clock (C or C or (K or K when in single-clock mode)). In order to maintain the internal logic, each read access must be allowed to complete. Each Read access consists of four 18-bit data Document #: 38-05498 Rev. *A words and takes 2 clock cycles to complete. Therefore, Read accesses to the device can not be initiated on two consecutive K clock rises. The internal logic of the device will ignore the second Read request. Read accesses can be initiated on every other K clock rise. Doing so will pipeline the data flow such that data is transferred out of the device on every rising edge of the output clocks (C and C or K and K when in single-clock mode). When the read port is deselected, the CY7C1313AV18 will first complete the pending read transactions. Synchronous internal circuitry will automatically tri-state the outputs following the next rising edge of the Positive Output Clock (C). This will allow for a seamless transition between devices without the insertion of wait states in a depth expanded memory. Write Operations Write operations are initiated by asserting WPS active at the rising edge of the Positive Input Clock (K). On the following K clock rise the data presented to D[17:0] is latched and stored into the lower 18-bit Write Data register, provided BWS[1:0] are both asserted active. On the subsequent rising edge of the Negative Input Clock (K) the information presented to D[17:0] is also stored into the Write Data Register, provided BWS[1:0] are both asserted active. This process continues for one more cycle until four 18-bit words (a total of 72 bits) of data are stored in the SRAM. The 72 bits of data are then written into the memory array at the specified location. Therefore, Write accesses to the device can not be initiated on two consecutive K clock rises. The internal logic of the device will ignore the second Write request. Write accesses can be initiated on every other rising edge of the Positive Input Clock (K). Doing so will pipeline the data flow such that 18 bits of data can be transferred into the device on every rising edge of the input clocks (K and K). When deselected, the write port will ignore all inputs after the pending Write operations have been completed. Byte Write Operations Byte Write operations are supported by the CY7C1313AV18. A write operation is initiated as described in the Write Operation section above. The bytes that are written are determined by BWS0 and BWS1, which are sampled with each set of 18-bit data words. Asserting the appropriate Byte Write Select input during the data portion of a write will allow the data being presented to be latched and written into the device. Deasserting the Byte Write Select input during the data portion of a write will allow the data stored in the device for that byte to remain unaltered. This feature can be used to simplify Read/Modify/Write operations to a Byte Write operation. Page 6 of 22 [+] Feedback CY7C1311AV18 CY7C1313AV18 CY7C1315AV18 PRELIMINARY Single Clock Mode Depth Expansion The CY7C1313AV18 can be used with a single clock that controls both the input and output registers. In this mode the device will recognize only a single pair of input clocks (K and K) that control both the input and output registers. This operation is identical to the operation if the device had zero skew between the K/K and C/C clocks. All timing parameters remain the same in this mode. To use this mode of operation, the user must tie C and C HIGH at power on. This function is a strap option and not alterable during device operation. The CY7C1313AV18 has a Port Select input for each port. This allows for easy depth expansion. Both Port Selects are sampled on the rising edge of the Positive Input Clock only (K). Each port select input can deselect the specified port. Deselecting a port will not affect the other port. All pending transactions (Read and Write) will be completed prior to the device being deselected. Concurrent Transactions The Read and Write ports on the CY7C1313AV18 operate completely independently of one another. Since each port latches the address inputs on different clock edges, the user can Read or Write to any location, regardless of the transaction on the other port. If the ports access the same location when a read follows a write in successive clock cycles, the SRAM will deliver the most recent information associated with the specified address location. This includes forwarding data from a Write cycle that was initiated on the previous K clock rise. Read accesses and Write access must be scheduled such that one transaction is initiated on any clock cycle. If both ports are selected on the same K clock rise, the arbitration depends on the previous state of the SRAM. If both ports were deselected, the Read port will take priority. If a Read was initiated on the previous cycle, the Write port will assume priority (since Read operations can not be initiated on consecutive cycles). If a Write was initiated on the previous cycle, the Read port will assume priority (since Write operations can not be initiated on consecutive cycles). Therefore, asserting both port selects active from a deselected state will result in alternating Read/Write operations being initiated, with the first access being a Read. Programmable Impedance An external resistor, RQ, must be connected between the ZQ pin on the SRAM and VSS to allow the SRAM to adjust its output driver impedance. The value of RQ must be 5X the value of the intended line impedance driven by the SRAM, The allowable range of RQ to guarantee impedance matching with a tolerance of ±15% is between 175Ω and 350Ω, with VDDQ = 1.5V. The output impedance is adjusted every 1024 cycles upon powerup to account for drifts in supply voltage and temperature. Echo Clocks Echo clocks are provided on the QDR-II to simplify data capture on high speed systems. Two echo clocks are generated by the QDR-II. CQ is referenced with respect to C and CQ is referenced with respect to C. These are free running clocks and are synchronized to the output clock of the QDR-II. In the single clock mode, CQ is generated with respect to K and CQ is generated with respect to K. The timings for the echo clocks are shown in the AC timing table. DLL These chips utilize a Delay Lock Loop (DLL) that is designed to function between 80 MHz and the specified maximum clock frequency. The DLL may be disabled by applying ground to the DOFF pin. The DLL can also be reset by slowing the cycle time of input clocks K and K to greater than 30 ns. Application Example[1] SRAM #1 Vt R D A R P S # W P S # B W S # DATA IN DATA OUT Address RPS# BUS WPS# MASTER BWS# (CPU CLKIN/CLKIN# or Source K ASIC) Source K# ZQ CQ/CQ# Q C C# K K# R = 250ohms SRAM #4 R P S # D A R W P S # B W S # ZQ R = 250ohms CQ/CQ# Q C C# K K# Vt Vt Delayed K Delayed K# R R = 50ohms Vt = Vddq/2 Note: 1. The above application shows four QDRII being used. Document #: 38-05498 Rev. *A Page 7 of 22 [+] Feedback CY7C1311AV18 CY7C1313AV18 CY7C1315AV18 PRELIMINARY Truth Table[ 2, 3, 4, 5, 6, 7] Operation K RPS WPS [9] DQ DQ DQ DQ L-H Write Cycle: Load address on the rising edge of K; input write data on two consecutive K and K rising edges. H[8] L D(A) at K(t+1) ↑ D(A + 1) at K(t+1) ↑ D(A + 2) at K(t D(A + 3) at + 2) ↑ K(t +2) ↑ Read Cycle: L-H Load address on the rising edge of K; wait one and a half cycle; read data on two consecutive C and C rising edges. L[9] X Q(A) at C(t +1)↑ Q(A + 1) at C(t + 2) ↑ Q(A + 2) at C(t Q(A + 3) at C(t + 2)↑ + 3) ↑ NOP: No Operation L-H H H D=X Q=High-Z D=X Q=High-Z D=X Q=High-Z Standby: Clock Stopped Stopped X X Previous State Previous State Previous State Write Cycle Descriptions CY7C1311AV18 and CY7C1313AV18) BWS0 BWS1 K K – L L L–H L L – L H L–H L H – H L L–H H L – H H L–H H H – D=X Q=High-Z Previous State [2, 10] Comments During the Data portion of a Write sequence : CY7C1311AV18 − both nibbles (D[7:0]) are written into the device, CY7C1313AV18 − both bytes (D[17:0]) are written into the device. L-H During the Data portion of a Write sequence : CY7C1311AV18 − both nibbles (D[7:0]) are written into the device, CY7C1313AV18 − both bytes (D[17:0]) are written into the device. – During the Data portion of a Write sequence : CY7C1311AV18 − only the lower nibble (D[3:0]) is written into the device. D[7:4] will remain unaltered, CY7C1313AV18 − only the lower byte (D[8:0]) is written into the device. D[17:9] will remain unaltered. L–H During the Data portion of a Write sequence : CY7C1311AV18 − only the lower nibble (D[3:0]) is written into the device. D[7:4] will remain unaltered, CY7C1313AV18 − only the lower byte (D[8:0]) is written into the device. D[17:9] will remain unaltered. – During the Data portion of a Write sequence : CY7C1311AV18 − only the upper nibble (D[7:4]) is written into the device. D[3:0] will remain unaltered, CY7C1313AV18 − only the upper byte (D[17:9]) is written into the device. D[8:0] will remain unaltered. L–H During the Data portion of a Write sequence : CY7C1311AV18 − only the upper nibble (D[7:4]) is written into the device. D[3:0] will remain unaltered, CY7C1313AV18 − only the upper byte (D[17:9]) is written into the device. D[8:0] will remain unaltered. – No data is written into the devices during this portion of a write operation. L–H No data is written into the devices during this portion of a write operation. Notes: 2. X = “Don't Care,” H = Logic HIGH, L = Logic LOW, ↑represents rising edge. 3. Device will power-up deselected and the outputs in a tri-state condition. 4. “A” represents address location latched by the devices when transaction was initiated. A + 1, A + 2, and A +3 represents the address sequence in the burst. 5. “t” represents the cycle at which a read/write operation is started. t + 1, t + 2, and t + 3 are the first, second and third clock cycles respectively succeeding the “t” clock cycle. 6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode. 7. It is recommended that K = K and C = C = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically. 8. If this signal was LOW to initiate the previous cycle, this signal becomes a “Don’t Care” for this operation. 9. This signal was HIGH on previous K clock rise. Initiating consecutive Read or Write operations on consecutive K clock rises is not permitted. The device will ignore the second Read or Write request. 10. Assumes a Write cycle was initiated per the Write Port Cycle Description Truth Table. BWS0, BWS1 in the case of CY7C1311AV18 and CY7C1313AV18 and also BWS2, BWS3 in the case of CY7C1315AV18 can be altered on different portions of a write cycle, as long as the set-up and hold requirements are achieved. Document #: 38-05498 Rev. *A Page 8 of 22 [+] Feedback CY7C1311AV18 CY7C1313AV18 CY7C1315AV18 PRELIMINARY Write Cycle Descriptions[2, 10](CY7C1315AV18) BWS0 BWS1 BWS2 BWS3 K K Comments L L L L L–H – During the Data portion of a Write sequence, all four bytes (D[35:0]) are written into the device. L L L L – L–H During the Data portion of a Write sequence, all four bytes (D[35:0]) are written into the device. L H H H L–H – During the Data portion of a Write sequence, only the lower byte (D[8:0]) is written into the device. D[35:9] will remain unaltered. L H H H – L–H During the Data portion of a Write sequence, only the lower byte (D[8:0]) is written into the device. D[35:9] will remain unaltered. H L H H L–H – During the Data portion of a Write sequence, only the byte (D[17:9]) is written into the device. D[8:0] and D[35:18] will remain unaltered. H L H H – L–H During the Data portion of a Write sequence, only the byte (D[17:9]) is written into the device. D[8:0] and D[35:18] will remain unaltered. H H L H L–H – During the Data portion of a Write sequence, only the byte (D[26:18]) is written into the device. D[17:0] and D[35:27] will remain unaltered. H H L H – L–H During the Data portion of a Write sequence, only the byte (D[26:18]) is written into the device. D[17:0] and D[35:27] will remain unaltered. H H H L L–H H H H L – L–H H H H H L–H – No data is written into the device during this portion of a write operation. H H H H – L–H No data is written into the device during this portion of a write operation. Document #: 38-05498 Rev. *A During the Data portion of a Write sequence, only the byte (D[35:27]) is written into the device. D[26:0] will remain unaltered. During the Data portion of a Write sequence, only the byte (D[35:27]) is written into the device. D[26:0] will remain unaltered. Page 9 of 22 [+] Feedback CY7C1311AV18 CY7C1313AV18 CY7C1315AV18 PRELIMINARY Maximum Ratings (Above which the useful life may be impaired.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied .. –55°C to +125°C Supply Voltage on VDD Relative to GND........ –0.5V to +2.9V Static Discharge Voltage (MIL-STD-883, M. 3015)... >2001V Latch-up Current..................................................... >200 mA Operating Range DC Applied to Outputs in High-Z .........–0.5V to VDDQ + 0.5V Range DC Input Voltage[14] ............................ –0.5V to VDDQ + 0.5V Com’l Ambient Temperature(TA) VDD[16] VDDQ[16] 0°C to +70°C 1.8 ± 0.1V 1.4V to VDD Current into Outputs (LOW) .........................................20 mA DC Electrical Characteristics Over the Operating Range[11] Min. Typ. Max. Unit VDD Parameter Power Supply Voltage Description Test Conditions 1.7 1.8 1.9 V VDDQ I/O Supply Voltage 1.4 1.5 VDD V VOH Output HIGH Voltage [12] VDDQ/2 -0.12 VDDQ/2 + 0.12 V VOL Output LOW Voltage [13] VDDQ/2 -0.12 VDDQ/2 + 0.12 V VOH(LOW) Output HIGH Voltage IOH = −0.1 mA, Nominal Impedance VDDQ – 0.2 VDDQ V VOL(LOW) Output LOW Voltage IOL = 0.1mA, Nominal Impedance VSS 0.2 V VREF + 0.1 VDDQ+0.3 V Input HIGH Voltage[14] VIL Input LOW Voltage[14,15] VIN Clock Input Voltage IX Input Load Current GND ≤ VI ≤ VDDQ IOZ Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled VIH Voltage[17] VREF Input Reference IDD VDD Operating Supply ISB1 Automatic Power-down Curren –0.3 VREF–0.1 V VDDQ + 0.3 V −5 5 µA −5 5 µA –0.3 Typical Value = 0.75V 0.68 - 0.95 V VDD = Max., IOUT = 0 mA, f = fMAX = 1/tCYC 167 MHz 0.75 640 mA 200 MHz 700 mA 250 MHz 800 mA Max. VDD, Both Ports Deselected, VIN ≥ VIH or VIN ≤ VIL f = fMAX = 1/tCYC, Inputs Static 167 MHz 420 mA 200 MHz 450 mA 250 MHz 490 mA Notes: 11. All Voltage referenced to Ground. 12. Output are impedance controlled. Ioh=−(Vddq/2)/(RQ/5) for values of 175ohms