CY7C13201KV18
18-Mbit DDR II SRAM 2-Word
Burst Architecture
Features
Functional Description
■
18 Mbit Density (512K x 36)
The CY7C13201KV18 is 1.8V Synchronous Pipelined SRAM
equipped with DDR II architecture. The DDR II consists of an
SRAM core with advanced synchronous peripheral circuitry and
a 1-bit burst counter. Addresses for read and write are latched
on alternate rising edges of the input (K) clock. Write data is
registered on the rising edges of both K and K. Read data is
driven on the rising edges of C and C if provided, or on the rising
edge of K and K if C/C are not provided. The burst counter takes
in the least significant bit of the external address and bursts two
two 36-bit words sequentially into or out of the device.
■
333 MHz Clock for High Bandwidth
■
2-Word Burst to Reduce Address Bus Frequency
■
Double Data Rate (DDR) Interfaces
(data transferred at 666 MHz) at 333 MHz
■
Two Input Clocks (K and K) for Precise DDR Timing
❐ SRAM uses rising edges only
■
Two Input Clocks for Output Data (C and C) to minimize Clock
Skew and Flight Time Mismatches
■
Echo Clocks (CQ and CQ) simplify Data Capture in High Speed
Systems
■
Synchronous Internally Self Timed Writes
■
DDR II Operates with 1.5 Cycle Read Latency when DOFF is
Asserted HIGH
■
Operates Similar to DDR I Device with 1 Cycle Read Latency
when DOFF is Asserted LOW
■
1.8V Core Power Supply with HSTL Inputs and Outputs
■
Variable Drive HSTL Output Buffers
■
Expanded HSTL Output Voltage (1.4V–VDD)
❐ Supports both 1.5V and 1.8V I/O supply
■
Available in 165-Ball FBGA Package (13 x 15 x 1.4 mm)
■
Offered in both Pb-free and Non Pb-free Packages
■
JTAG 1149.1 Compatible Test Access Port
■
Phase Locked Loop (PLL) for Accurate Data Placement
Asynchronous inputs include an output impedance matching
input (ZQ). Synchronous data outputs (Q, sharing the same
physical pins as the data inputs D) are tightly matched to the two
output echo clocks CQ/CQ, eliminating the need for separately
capturing data from each individual DDR SRAM in the system
design. Output data clocks (C/C) enable maximum system
clocking and data synchronization flexibility.
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the C or C (or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
This device is down bonded from the 65 nm 72M QDRII device
and has the same IDD/ISB1 values and JTAG ID code as the
equivalent 72M device option. For details refer to the application
note AN53189, 65 nm Technology Interim QDRII/DDRII SRAM
Device Family Description.
Configuration
CY7C13201KV18 – 512K x 36
Table 1. Selection Guide
Description
333 MHz
300 MHz
250 MHz
200 MHz
167 MHz
Unit
Maximum Operating Frequency
333
300
250
200
167
MHz
Maximum Operating Current
640
600
530
450
400
mA
Cypress Semiconductor Corporation
Document Number: 001-54142 Rev. *B
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised September 11, 2009
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CY7C13201KV18
Logic Block Diagram (CY7C13201KV18)
Burst
Logic
19
Write
Reg
18
K
Address
Register
CLK
Gen.
K
DOFF
256K x 36 Array
LD
Write
Reg
256K x 36 Array
A(18:1)
Write Add. Decode
A(18:0)
Read Add. Decode
A0
36
Output
Logic
Control
R/W
C
Read Data Reg.
72
VREF
R/W
BWS[3:0]
Control
Logic
C
36
Reg.
36
CQ
Reg. 36
36
Reg.
CQ
36
DQ[35:0]
Pin Configuration
The pin configuration for CY7C13201KV18 follows.[1]
Figure 1. 165-Ball FBGA (13 x 15 x 1.4 mm) Pinout
1
2
3
NC/144M NC/36M
4
5
6
7
8
9
10
11
R/W
BWS2
K
BWS1
LD
A
NC/72M
CQ
A
CQ
B
NC
DQ27
DQ18
A
BWS3
K
BWS0
A
NC
NC
DQ8
C
NC
NC
DQ28
VSS
A
A0
A
VSS
NC
DQ17
DQ7
D
NC
DQ29
DQ19
VSS
VSS
VSS
VSS
VSS
NC
NC
DQ16
E
NC
NC
DQ20
VDDQ
VSS
VSS
VSS
VDDQ
NC
DQ15
DQ6
F
NC
DQ30
DQ21
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
DQ5
G
NC
DQ31
DQ22
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
DQ14
H
DOFF
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
NC
NC
DQ32
VDDQ
VDD
VSS
VDD
VDDQ
NC
DQ13
DQ4
K
NC
NC
DQ23
VDDQ
VDD
VSS
VDD
VDDQ
NC
DQ12
DQ3
L
NC
DQ33
DQ24
VDDQ
VSS
VSS
VSS
VDDQ
NC
NC
DQ2
M
NC
NC
DQ34
VSS
VSS
VSS
VSS
VSS
NC
DQ11
DQ1
N
NC
DQ35
DQ25
VSS
A
A
A
VSS
NC
NC
DQ10
P
NC
NC
DQ26
A
A
C
A
A
NC
DQ9
DQ0
R
TDO
TCK
A
A
A
C
A
A
A
TMS
TDI
Document Number: 001-54142 Rev. *B
Page 2 of 23
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CY7C13201KV18
Pin Definitions
Pin Name
I/O
Pin Description
DQ[x:0]
Input Output- Data Input Output Signals. Inputs are sampled on the rising edge of K and K clocks during valid write
Synchronous operations. These pins drive out the requested data when the read operation is active. Valid data is driven
out on the rising edge of both the C and C clocks during read operations or K and K when in single clock
mode. When read access is deselected, Q[x:0] are automatically tristated.
LD
InputSynchronous Load. This input is brought LOW when a bus cycle sequence is defined. This definition
Synchronous includes address and read/write direction. All transactions operate on a burst of 2 data.
BWS0,
BWS1,
BWS2,
BWS3
InputByte Write Select 0, 1, 2, and 3 − Active LOW. Sampled on the rising edge of the K and K clocks during
Synchronous write operations. Used to select which byte is written into the device during the current portion of the write
operations. Bytes not written remain unaltered.BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2
controls D[26:18] and BWS3 controls D[35:27].
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select
ignores the corresponding byte of data and it is not written into the device.
A, A0
InputAddress Inputs. These address inputs are multiplexed for both read and write operations. Internally, the
Synchronous device is organized as 512K x 36 (2 arrays each of 256K x 36). A0 is the input to the burst counter. These
are incremented in a linear fashion internally. 19 address inputs are needed to access the entire memory
array. All the address inputs are ignored when the appropriate port is deselected.
R/W
InputSynchronous Read or Write Input. When LD is LOW, this input designates the access type (read when
Synchronous R/W is HIGH, write when R/W is LOW) for loaded address. R/W must meet the setup and hold times
around edge of K.
C
Input Clock
Positive Input Clock for Output Data. C is used in conjunction with C to clock out the read data from
the device. C and C can be used together to deskew the flight times of various devices on the board back
to the controller. See application example for further details.
C
Input Clock
Negative Input Clock for Output Data. C is used in conjunction with C to clock out the read data from
the device. C and C can be used together to deskew the flight times of various devices on the board back
to the controller. See Application Example on page 6 for further details.
K
Input Clock
Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device
and to drive out data through Q[x:0] when in single clock mode. All accesses are initiated on the rising
edge of K.
K
Input Clock
Negative Input Clock Input. K is used to capture synchronous data being presented to the device and
to drive out data through Q[x:0] when in single clock mode.
CQ
Output Clock CQ Referenced with Respect to C. This is a free running clock and is synchronized to the input clock
for output data (C) of the DDR II. In the single clock mode, CQ is generated with respect to K. The timing
for the echo clocks is shown in the AC Timing table.
CQ
Output Clock CQ Referenced with Respect to C. This is a free running clock and is synchronized to the input clock
for output data (C) of the DDR II. In the single clock mode, CQ is generated with respect to K. The timing
for the echo clocks is shown in the AC Timing table.
ZQ
Input
Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus
impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 x RQ, where RQ is a resistor connected
between ZQ and ground. Alternatively, this pin can be connected directly to VDDQ, which enables the
minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.
DOFF
Input
PLL Turn Off − Active LOW. Connecting this pin to ground turns off the PLL inside the device. The timing
in the PLL turned off operation differs from those listed in this data sheet. For normal operation, this pin
is connected to a pull up through a 10 KΩ or less pull up resistor. The device behaves in DDR I mode
when the PLL is turned off. In this mode, the device can be operated at a frequency of up to 167 MHz
with DDR I timing.
Note
1. NC/36M, NC/72M, NC/144M, and NC/288M are not connected to the die and can be tied to any voltage level.
Document Number: 001-54142 Rev. *B
Page 3 of 23
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CY7C13201KV18
Pin Definitions
Pin Name
(continued)
I/O
Pin Description
TDO
Output
TCK
Input
TCK Pin for JTAG.
TDI
Input
TDI Pin for JTAG.
TMS
Input
TMS Pin for JTAG.
NC
N/A
Not Connected to the Die. Can be tied to any voltage level.
NC/36M
Input
Not Connected to the Die. Can be tied to any voltage level.
NC/72M
Input
Not Connected to the Die. Can be tied to any voltage level.
NC/144M
Input
Not Connected to the Die. Can be tied to any voltage level.
NC/288M
Input
Not Connected to the Die. Can be tied to any voltage level.
VREF
VDD
VSS
VDDQ
InputReference
TDO for JTAG.
Reference Voltage Input. Static input used to set the reference level for HSTL inputs, outputs, and AC
measurement points.
Power Supply Power Supply Inputs to the Core of the Device.
Ground
Ground for the Device.
Power Supply Power Supply Inputs for Outputs of the Device.
Document Number: 001-54142 Rev. *B
Page 4 of 23
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CY7C13201KV18
Functional Overview
The CY7C13201KV18 is synchronous pipelined Burst SRAM
equipped with a DDR interface, which operates with a read
latency of one and a half cycles when DOFF pin is tied HIGH.
When DOFF pin is set LOW or connected to VSS the device
behaves in DDR I mode with a read latency of one clock cycle.
Accesses are initiated on the rising edge of the positive input
clock (K). All synchronous input timing is referenced from the
rising edge of the input clocks (K and K) and all output timing is
referenced to the rising edge of the output clocks (C/C, or K/K
when in single clock mode).
All synchronous data inputs (D[x:0]) pass through input registers
controlled by the rising edge of the input clocks (K and K). All
synchronous data outputs (Q[x:0]) pass through output registers
controlled by the rising edge of the output clocks (C/C, or K/K
when in single clock mode).
All synchronous control (R/W, LD, BWS[0:X]) inputs pass through
input registers controlled by the rising edge of the input clock (K).
CY7C13201KV18 is described in the following sections.
Read Operations
The CY7C13201KV18 is organized internally as a two arrays of
256K x 36. Accesses are completed in a burst of 2 sequential
36-bit data words. Read operations are initiated by asserting
R/W HIGH and LD LOW at the rising edge of the positive input
clock (K). The address presented to address inputs is stored in
the read address register and the least significant bit of the
address is presented to the burst counter. The burst counter
increments the address in a linear fashion. Following the next K
clock rise, the corresponding 36-bit word of data from this
address location is driven onto the Q[35:0] using C as the output
timing reference. On the subsequent rising edge of C the next
36-bit data word from the address location generated by the
burst counter is driven onto the Q[35:0]. The requested data is
valid 0.45 ns from the rising edge of the output clock (C or C, or
K and K when in single clock mode, 200 MHz, 250 MHz, and 300
MHz device). To maintain the internal logic, each read access
must be allowed to complete. Read accesses can be initiated on
every rising edge of the positive input clock (K).
When read access is deselected, the CY7C13201KV18 first
completes the pending read transactions. Synchronous internal
circuitry automatically tristates the output following the next rising
edge of the positive output clock (C). This enables for a transition
between devices without the insertion of wait states in a depth
expanded memory.
Write Operations
Write operations are initiated by asserting R/W LOW and LD
LOW at the rising edge of the positive input clock (K). The
address presented to address inputs is stored in the write
address register and the least significant bit of the address is
presented to the burst counter. The burst counter increments the
address in a linear fashion. On the following K clock rise, the data
presented to D[35:0] is latched and stored into the 36-bit write
data register, provided BWS[3:0] are asserted active. On the
subsequent rising edge of the Negative Input Clock (K) the infor-
Document Number: 001-54142 Rev. *B
mation presented to D[35:0] is also stored into the write data
register, provided BWS[3:0] are asserted active. The 72 bits of
data are then written into the memory array at the specified
location. Write accesses can be initiated on every rising edge of
the positive input clock (K). This pipelines the data flow such that
36 bits of data can be transferred into the device on every rising
edge of the input clocks (K and K).
When the write access is deselected, the device ignores all
inputs after the pending write operations are completed.
Byte Write Operations
Byte write operations are supported by the CY7C13201KV18. A
write operation is initiated as described in the Write Operations
section. The bytes that are written are determined by BWS0,
BWS1, BWS2, and BWS3 which are sampled with each set of
36-bit data words. Asserting the appropriate Byte Write Select
input during the data portion of a write latches the data being
presented and writes it into the device. Deasserting the Byte
Write Select input during the data portion of a write enables the
data stored in the device for that byte to remain unaltered. This
feature is used to simplify read, modify, or write operations to a
byte write operation.
Single Clock Mode
The CY7C13201KV18 is used with a single clock that controls
both the input and output registers. In this mode, the device
recognizes only a single pair of input clocks (K and K) that control
both the input and output registers. This operation is identical to
the operation if the device had zero skew between the K/K and
C/C clocks. All timing parameters remain the same in this mode.
To use this mode of operation, tie C and C HIGH at power on.
This function is a strap option and not alterable during device
operation.
DDR Operation
The CY7C13201KV18 enables high performance operation
through high clock frequencies (achieved through pipelining) and
DDR mode of operation. The CY7C13201KV18 requires a single
No Operation (NOP) cycle during transition from a read to a write
cycle. At higher frequencies, some applications may require a
second NOP cycle to avoid contention.
If a read occurs after a write cycle, address and data for the write
are stored in registers. The write information must be stored
because the SRAM cannot perform the last word write to the
array without conflicting with the read. The data stays in this
register until the next write cycle occurs. On the first write cycle
after the reads, the stored data from the earlier write is written
into the SRAM array. This is called a posted write.
If a read is performed on the same address on which a write is
performed in the previous cycle, the SRAM reads out the most
current data. The SRAM does this by bypassing the memory
array and reading the data from the registers.
Depth Expansion
Depth expansion requires replicating the LD control signal for
each bank. All other control signals can be common between
banks as appropriate.
Page 5 of 23
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CY7C13201KV18
Programmable Impedance
PLL
An external resistor, RQ, must be connected between the ZQ pin
on the SRAM and VSS to allow the SRAM to adjust its output
driver impedance. The value of RQ must be 5x the value of the
intended line impedance driven by the SRAM. The allowable
range of RQ to guarantee impedance matching with a tolerance
of ±15% is between 175Ω and 350Ω, with VDDQ = 1.5V. The
output impedance is adjusted every 1024 cycles during power
up to account for drifts in supply voltage and temperature.
These chips use a PLL that is designed to function between
120 MHz and the specified maximum clock frequency. During
power up, when the DOFF is tied HIGH, the PLL is locked after
20 μs of stable clock. The PLL can also be reset by slowing or
stopping the input clock K and K for a minimum of 30 ns.
However, it is not necessary to reset the PLL to lock to the
desired frequency. The PLL automatically locks 20 μs after a
stable clock is presented. The PLL may be disabled by applying
ground to the DOFF pin. When the PLL is turned off, the device
behaves in DDR I mode (with one cycle latency and a longer
access time).
Echo Clocks
Echo clocks are provided on the DDR II to simplify data capture
on high speed systems. Two echo clocks are generated by the
DDR II. CQ is referenced with respect to C and CQ is referenced
with respect to C. These are free running clocks and are synchronized to the output clock of the DDR II. In single clock mode, CQ
is generated with respect to K and CQ is generated with respect
to K. The timing for the echo clocks is shown in the Switching
Characteristics on page 19.
Application Example
Figure 2 shows two DDR II used in an application.
Figure 2. Application Example
SRAM#1
DQ
A
DQ
Addresses
Cycle Start#
R/W#
Return CLK
Source CLK
Return CLK#
Source CLK#
Echo Clock1/Echo Clock#1
Echo Clock2/Echo Clock#2
BUS
MASTER
(CPU
or
ASIC)
ZQ
CQ/CQ#
LD# R/W# C C# K K#
R = 250ohms
SRAM#2
DQ
A
ZQ
CQ/CQ#
LD# R/W# C C# K K#
R = 250ohms
Vterm = 0.75V
R = 50ohms
Vterm = 0.75V
Document Number: 001-54142 Rev. *B
Page 6 of 23
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CY7C13201KV18
Truth Table
The truth table for CY7C13201KV18 follows.[2, 3, 4, 5, 6, 7]
Operation
K
LD
R/W
Write Cycle:
Load address; wait one cycle;
input write data on consecutive K and K rising edges.
L-H
L
L
D(A1) at K(t + 1) ↑ D(A2) at K(t + 1) ↑
Read Cycle:
Load address; wait one and a half cycle;
read data on consecutive C and C rising edges.
L-H
L
H
Q(A1) at C(t + 1)↑ Q(A2) at C(t + 2) ↑
L-H
H
X
High-Z
High-Z
Stopped
X
X
Previous State
Previous State
NOP: No Operation
Standby: Clock Stopped
DQ
DQ
Burst Address Table
First Address (External)
Second Address (Internal)
X..X0
X..X1
X..X1
X..X0
Write Cycle Descriptions
The write cycle description table for CY7C13201KV18 follows.[2, 8]
BWS0
BWS1
BWS2
BWS3
K
K
Comments
L
L
L
L
L–H
–
During the data portion of a write sequence, all four bytes (D[35:0]) are written into
the device.
L
L
L
L
–
L–H
During the data portion of a write sequence, all four bytes (D[35:0]) are written into
the device.
L
H
H
H
L–H
–
During the data portion of a write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] remains unaltered.
L
H
H
H
–
L–H
During the data portion of a write sequence, only the lower byte (D[8:0]) is written
into the device. D[35:9] remains unaltered.
H
L
H
H
L–H
–
During the data portion of a write sequence, only the byte (D[17:9]) is written into
the device. D[8:0] and D[35:18] remains unaltered.
H
L
H
H
–
L–H
During the data portion of a write sequence, only the byte (D[17:9]) is written into
the device. D[8:0] and D[35:18] remains unaltered.
H
H
L
H
L–H
–
During the data portion of a write sequence, only the byte (D[26:18]) is written into
the device. D[17:0] and D[35:27] remains unaltered.
H
H
L
H
–
L–H
During the data portion of a write sequence, only the byte (D[26:18]) is written into
the device. D[17:0] and D[35:27] remains unaltered.
H
H
H
L
L–H
–
During the data portion of a write sequence, only the byte (D[35:27]) is written into
the device. D[26:0] remains unaltered.
H
H
H
L
–
L–H
During the data portion of a write sequence, only the byte (D[35:27]) is written into
the device. D[26:0] remains unaltered.
H
H
H
H
L–H
–
No data is written into the device during this portion of a write operation.
H
H
H
H
–
L–H
No data is written into the device during this portion of a write operation.
Notes
2. X = “Don’t Care,” H = Logic HIGH, L = Logic LOW, ↑ represents rising edge.
3. Device powers up deselected with the outputs in a tristate condition.
4. “A1” represents address location latched by the device when transaction is initiated and “A2” represents the addresses sequence in the burst.
5. “t” represents the cycle at which a read/write operation is started. t + 1 and t + 2 are the first and second clock cycles succeeding the “t” clock cycle.
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
7. Ensure that when the clock is stopped K = K and C = C = HIGH. This is not essential, but permits most rapid restart by overcoming transmission line charging
symmetrically.
8. Is based on a write cycle that is initiated in accordance with the Write Cycle Descriptions table. BWS0, BWS1, BWS2, and BWS3 can be altered on different portions of
a write cycle, as long as the setup and hold requirements are achieved.
Document Number: 001-54142 Rev. *B
Page 7 of 23
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CY7C13201KV18
IEEE 1149.1 Serial Boundary Scan (JTAG)
These SRAMs incorporate a serial boundary scan Test Access
Port (TAP) in the FBGA package. This part is fully compliant with
IEEE Standard #1149.1-2001. The TAP operates using JEDEC
standard 1.8V I/O logic levels.
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternatively
be connected to VDD through a pull up resistor. TDO must be left
unconnected. During power up, the device comes up in a reset
state, which does not interfere with the operation of the device.
Test Access Port—Test Clock
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Test Mode Select (TMS)
The TMS input is used to give commands to the TAP controller
and is sampled on the rising edge of TCK. This pin may be left
unconnected if the TAP is not used. The pin is pulled up internally, resulting in a logic HIGH level.
Test Data-In (TDI)
The TDI pin is used to serially input information into the registers
and can be connected to the input of any of the registers. The
register between TDI and TDO is chosen by the instruction that
is loaded into the TAP instruction register. For information about
loading the instruction register, see the TAP Controller State
Diagram on page 10. TDI is internally pulled up and can be
unconnected if the TAP is unused in an application. TDI is
connected to the most significant bit (MSB) on any register.
Instruction Register
Three-bit instructions are serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO pins, as shown in TAP Controller Block Diagram on
page 11. During power up, the instruction register is loaded with
the IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state, as described
in the previous section.
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary “01” pattern to allow for
fault isolation of the board level serial test path.
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between TDI
and TDO pins. This enables shifting of data through the SRAM
with minimal delay. The bypass register is set LOW (VSS) when
the BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all the input and
output pins on the SRAM. Several No Connect (NC) pins are also
included in the scan register to reserve pins for higher density
devices.
The boundary scan register is loaded with the contents of the
RAM input and output ring when the TAP controller is in the
Capture-DR state and is then placed between the TDI and TDO
pins when the controller is moved to the Shift-DR state. The
EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions are
used to capture the contents of the input and output ring.
The Boundary Scan Order on page 14 shows the order in which
the bits are connected. Each bit corresponds to one of the bumps
on the SRAM package. The MSB of the register is connected to
TDI, and the LSB is connected to TDO.
Test Data-Out (TDO)
Identification (ID) Register
The TDO output pin is used to serially clock data out from the
registers. The output is active, depending upon the current state
of the TAP state machine (see Instruction Codes on page 13).
The output changes on the falling edge of TCK. TDO is
connected to the least significant bit (LSB) of any register.
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and is shifted out when the TAP controller is in the
Shift-DR state. The ID register has a vendor code and other information described in Identification Register Definitions on page
13.
Performing a TAP Reset
A Reset is performed by forcing TMS HIGH (VDD) for five rising
edges of TCK. This reset does not affect the operation of the
SRAM and is performed when the SRAM is operating. At power
up, the TAP is reset internally to ensure that TDO comes up in a
High-Z state.
TAP Registers
Registers are connected between the TDI and TDO pins to scan
the data in and out of the SRAM test circuitry. Only one register
can be selected at a time through the instruction registers. Data
is serially loaded into the TDI pin on the rising edge of TCK. Data
is output on the TDO pin on the falling edge of TCK.
Document Number: 001-54142 Rev. *B
TAP Instruction Set
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in Instruction
Codes on page 13. Three of these instructions are listed as
RESERVED and must not be used. The other five instructions
are described in this section in detail.
Instructions are loaded into the TAP controller during the Shift-IR
state when the instruction register is placed between TDI and
TDO. During this state, instructions are shifted through the
instruction register through the TDI and TDO pins. To execute
the instruction after it is shifted in, the TAP controller must be
moved into the Update-IR state.
Page 8 of 23
[+] Feedback
CY7C13201KV18
IDCODE
The IDCODE instruction loads a vendor-specific, 32-bit code into
the instruction register. It also places the instruction register
between the TDI and TDO pins and shifts the IDCODE out of the
device when the TAP controller enters the Shift-DR state. The
IDCODE instruction is loaded into the instruction register at
power up or whenever the TAP controller is supplied a
Test-Logic-Reset state.
SAMPLE Z
The SAMPLE Z instruction connects the boundary scan register
between the TDI and TDO pins when the TAP controller is in a
Shift-DR state. The SAMPLE Z command puts the output bus
into a High-Z state until the next command is supplied during the
Update IR state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When
the SAMPLE/PRELOAD instructions are loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the input and output pins is captured
in the boundary scan register.
The TAP controller clock can only operate at a frequency up to
20 MHz, while the SRAM clock operates more than an order of
magnitude faster. Because there is a large difference in the clock
frequencies, it is possible that during the Capture-DR state, an
input or output undergoes a transition. The TAP may then try to
capture a signal while in transition (metastable state). This does
not harm the device, but there is no guarantee as to the value
that is captured. Repeatable results may not be possible.
To guarantee that the boundary scan register captures the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller's capture setup plus hold
times (tCS and tCH). The SRAM clock input might not be captured
correctly if there is no way in a design to stop (or slow) the clock
during a SAMPLE/PRELOAD instruction. If this is an issue, it is
still possible to capture all other signals and simply ignore the
value of the CK and CK captured in the boundary scan register.
After the data is captured, it is possible to shift out the data by
putting the TAP into the Shift-DR state. This places the boundary
scan register between the TDI and TDO pins.
Document Number: 001-54142 Rev. *B
PRELOAD places an initial data pattern at the latched parallel
outputs of the boundary scan register cells before the selection
of another boundary scan test operation.
The shifting of data for the SAMPLE and PRELOAD phases can
occur concurrently when required, that is, while the data
captured is shifted out, the preloaded data can be shifted in.
BYPASS
When the BYPASS instruction is loaded in the instruction register
and the TAP is placed in a Shift-DR state, the bypass register is
placed between the TDI and TDO pins. The advantage of the
BYPASS instruction is that it shortens the boundary scan path
when multiple devices are connected together on a board.
EXTEST
The EXTEST instruction drives the preloaded data out through
the system output pins. This instruction also connects the
boundary scan register for serial access between the TDI and
TDO in the Shift-DR controller state.
EXTEST OUTPUT BUS TRISTATE
IEEE Standard 1149.1 mandates that the TAP controller be able
to put the output bus into a tristate mode.
The boundary scan register has a special bit located at bit #108.
When this scan cell, called the “extest output bus tristate,” is
latched into the preload register during the Update-DR state in
the TAP controller, it directly controls the state of the output
(Q-bus) pins, when the EXTEST is entered as the current
instruction. When HIGH, it enables the output buffers to drive the
output bus. When LOW, this bit places the output bus into a
High-Z condition.
This bit is set by entering the SAMPLE/PRELOAD or EXTEST
command, and then shifting the desired bit into that cell, during
the Shift-DR state. During Update-DR, the value loaded into that
shift-register cell latches into the preload register. When the
EXTEST instruction is entered, this bit directly controls the output
Q-bus pins. Note that this bit is preset HIGH to enable the output
when the device is powered up, and also when the TAP controller
is in the Test-Logic-Reset state.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
Page 9 of 23
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CY7C13201KV18
TAP Controller State Diagram
The state diagram for the TAP controller follows.[9]
1
TEST-LOGIC
RESET
0
0
TEST-LOGIC/
IDLE
1
SELECT
DR-SCAN
1
1
SELECT
IR-SCAN
0
0
1
1
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
0
SHIFT-IR
1
1
EXIT1-DR
1
EXIT1-IR
0
0
PAUSE-IR
1
0
1
EXIT2-DR
0
EXIT2-IR
1
1
UPDATE-IR
UPDATE-DR
1
1
0
PAUSE-DR
0
0
0
1
0
Note
9. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
Document Number: 001-54142 Rev. *B
Page 10 of 23
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CY7C13201KV18
TAP Controller Block Diagram
0
Bypass Register
2
Selection
Circuitry
TDI
1
0
Selection
Circuitry
Instruction Register
31
30
29
.
.
2
1
0
1
0
TDO
Identification Register
108
.
.
.
.
2
Boundary Scan Register
TCK
TAP Controller
TMS
TAP Electrical Characteristics
Over the Operating Range[10, 11, 12]
Parameter
Description
Test Conditions
Min
Max
Unit
VOH1
Output HIGH Voltage
IOH = −2.0 mA
1.4
V
VOH2
Output HIGH Voltage
IOH = −100 μA
1.6
V
VOL1
Output LOW Voltage
IOL = 2.0 mA
0.4
V
VOL2
Output LOW Voltage
IOL = 100 μA
0.2
V
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
IX
Input and Output Load Current
0.65VDD VDD + 0.3
GND ≤ VI ≤ VDD
V
–0.3
0.35VDD
V
–5
5
μA
Notes
10. These characteristics pertain to the TAP inputs (TMS, TCK, TDI, and TDO). Parallel load levels are specified in the Electrical Characteristics Table.
11. Overshoot: VIH(AC) < VDDQ + 0.85V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > −1.5V (Pulse width less than tCYC/2).
12. All voltage referenced to Ground.
Document Number: 001-54142 Rev. *B
Page 11 of 23
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CY7C13201KV18
TAP AC Switching Characteristics
Over the Operating Range[13, 14]
Parameter
Description
Min
Max
Unit
20
MHz
tTCYC
TCK Clock Cycle Time
tTF
TCK Clock Frequency
tTH
TCK Clock HIGH
20
ns
tTL
TCK Clock LOW
20
ns
tTMSS
TMS Setup to TCK Clock Rise
5
ns
tTDIS
TDI Setup to TCK Clock Rise
5
ns
tCS
Capture Setup to TCK Rise
5
ns
tTMSH
TMS Hold after TCK Clock Rise
5
ns
tTDIH
TDI Hold after Clock Rise
5
ns
tCH
Capture Hold after Clock Rise
5
ns
50
ns
Setup Times
Hold Times
Output Times
tTDOV
TCK Clock LOW to TDO Valid
tTDOX
TCK Clock LOW to TDO Invalid
10
0
ns
ns
TAP Timing and Test Conditions
Figure 3 shows the TAP timing and test conditions.[14]
Figure 3. TAP Timing and Test Conditions
0.9V
ALL INPUT PULSES
1.8V
50Ω
0.9V
TDO
0V
Z0 = 50Ω
(a)
CL = 20 pF
tTH
GND
tTL
Test Clock
TCK
tTCYC
tTMSH
tTMSS
Test Mode Select
TMS
tTDIS
tTDIH
Test Data In
TDI
Test Data Out
TDO
tTDOV
tTDOX
Notes
13. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.
14. Test conditions are specified using the load in TAP AC Test Conditions. tR/tF = 1 ns.
Document Number: 001-54142 Rev. *B
Page 12 of 23
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CY7C13201KV18
Identification Register Definitions
Value
Instruction Field
Description
CY7C13201KV18
Revision Number (31:29)
000
Cypress Device ID (28:12)
11010100010100100
Cypress JEDEC ID (11:1)
00000110100
ID Register Presence (0)
1
Version number.
Defines the type of SRAM.
Allows unique identification of SRAM
vendor.
Indicates the presence of an ID register.
Scan Register Sizes
Register Name
Bit Size
Instruction
3
Bypass
1
ID
32
Boundary Scan
109
Instruction Codes
Instruction
Code
Description
EXTEST
000
Captures the input and output ring contents.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operation.
SAMPLE Z
010
Captures the input and output contents. Places the boundary scan register between TDI
and TDO. Forces all SRAM output drivers to a High-Z state.
RESERVED
011
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
100
Captures the input and output ring contents. Places the boundary scan register between
TDI and TDO. Does not affect the SRAM operation.
RESERVED
101
Do Not Use: This instruction is reserved for future use.
RESERVED
110
Do Not Use: This instruction is reserved for future use.
BYPASS
111
Places the bypass register between TDI and TDO. This operation does not affect SRAM
operation.
Document Number: 001-54142 Rev. *B
Page 13 of 23
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CY7C13201KV18
Boundary Scan Order
Bit #
Bump ID
Bit #
Bump ID
Bit #
Bump ID
Bit #
Bump ID
0
6R
28
10G
56
6A
84
1J
1
6P
29
9G
57
5B
85
2J
2
6N
30
11F
58
5A
86
3K
3
7P
31
11G
59
4A
87
3J
4
7N
32
9F
60
5C
88
2K
5
7R
33
10F
61
4B
89
1K
6
8R
34
11E
62
3A
90
2L
7
8P
35
10E
63
2A
91
3L
8
9R
36
10D
64
1A
92
1M
9
11P
37
9E
65
2B
93
1L
10
10P
38
10C
66
3B
94
3N
3M
11
10N
39
11D
67
1C
95
12
9P
40
9C
68
1B
96
1N
13
10M
41
9D
69
3D
97
2M
14
11N
42
11B
70
3C
98
3P
15
9M
43
11C
71
1D
99
2N
16
9N
44
9B
72
2C
100
2P
17
11L
45
10B
73
3E
101
1P
18
11M
46
11A
74
2D
102
3R
19
9L
47
10A
75
2E
103
4R
20
10L
48
9A
76
1E
104
4P
21
11K
49
8B
77
2F
105
5P
22
10K
50
7C
78
3F
106
5N
23
9J
51
6C
79
1G
107
5R
24
9K
52
8A
80
1F
108
Internal
25
10J
53
7A
81
3G
26
11J
54
7B
82
2G
27
11H
55
6B
83
1H
Document Number: 001-54142 Rev. *B
Page 14 of 23
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CY7C13201KV18
Power Up Sequence in DDR II SRAM
PLL Constraints
DDR II SRAMs must be powered up and initialized in a
predefined manner to prevent undefined operations.
■
PLL uses K clock as its synchronizing input. The input must
have low phase jitter, which is specified as tKC Var.
■
The PLL functions at frequencies down to 120 MHz.
■
If the input clock is unstable and the PLL is enabled, then the
PLL may lock onto an incorrect frequency, causing unstable
SRAM behavior. To avoid this, provide 20 μs of stable clock to
relock to the desired clock frequency.
Power Up Sequence
■
Apply power and drive DOFF either HIGH or LOW (All other
inputs can be HIGH or LOW).
❐ Apply VDD before VDDQ.
❐ Apply VDDQ before VREF or at the same time as VREF.
❐ Drive DOFF HIGH.
■
Provide stable DOFF (HIGH), power and clock (K, K) for 20 μs
to lock the PLL.
~
~
Figure 4. Power Up Waveforms
K
K
~
~
Unstable Clock
> 20Ps Stable clock
Start Normal
Operation
Clock Start (Clock Starts after V DD / V DDQ Stable)
VDD / VDDQ
DOFF
Document Number: 001-54142 Rev. *B
V DD / V DDQ Stable (< +/- 0.1V DC per 50ns )
Fix HIGH (or tie to VDDQ)
Page 15 of 23
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CY7C13201KV18
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ................................. –65°C to +150°C
Neutron Soft Error Immunity
Description
Test
Conditions
Typ
Max*
Unit
LSBU
Logical
Single-Bit
Upsets
25°C
197
216
FIT/
Mb
LMBU
Logical
Multi-Bit
Upsets
25°C
0
0.01
FIT/
Mb
SEL
Single
Event
Latchup
85°C
0
0.1
FIT/
Dev
Parameter
Ambient Temperature with Power Applied.. –55°C to +125°C
Supply Voltage on VDD Relative to GND ........–0.5V to +2.9V
Supply Voltage on VDDQ Relative to GND.......–0.5V to +VDD
DC Applied to Outputs in High-Z ......... –0.5V to VDDQ + 0.3V
DC Input Voltage[11] ............................... –0.5V to VDD + 0.3V
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage (MIL-STD-883, M 3015).... >2001V
Latch up Current..................................................... >200 mA
Operating Range
Range
Commercial
Industrial
Ambient
Temperature (TA)
VDD[15]
VDDQ[15]
0°C to +70°C
1.8 ± 0.1V
1.4V to
VDD
–40°C to +85°C
* No LMBU or SEL events occurred during testing; this column represents a
statistical χ2, 95% confidence limit calculation. For more details refer to Application Note AN 54908 “Accelerated Neutron SER Testing and Calculation of
Terrestrial Failure Rates”
Electrical Characteristics
DC Electrical Characteristics
Over the Operating Range[12]
Parameter
Description
Test Conditions
Min
Typ
Max
Unit
VDD
Power Supply Voltage
1.7
1.8
1.9
V
VDDQ
I/O Supply Voltage
1.4
1.5
VDD
V
VOH
Output HIGH Voltage
Note 16
VDDQ/2 – 0.12
VDDQ/2 + 0.12
V
VOL
Output LOW Voltage
Note 17
VDDQ/2 – 0.12
VDDQ/2 + 0.12
V
VOH(LOW)
Output HIGH Voltage
IOH = −0.1 mA, Nominal Impedance
VDDQ – 0.2
VDDQ
V
VOL(LOW)
Output LOW Voltage
IOL = 0.1 mA, Nominal Impedance
VSS
0.2
V
VIH
Input HIGH Voltage
VREF + 0.1
VDDQ + 0.3
V
VIL
Input LOW Voltage
–0.3
VREF – 0.1
V
IX
Input Leakage Current
GND ≤ VI ≤ VDDQ
−5
5
μA
IOZ
Output Leakage Current
GND ≤ VI ≤ VDDQ, Output Disabled
−5
5
μA
0.95
V
VREF
Input Reference Voltage
[18]
Typical Value = 0.75V
0.68
0.75
Notes
15. Power up assumes a linear ramp from 0V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
16. Outputs are impedance controlled. IOH = –(VDDQ/2)/(RQ/5) for values of 175Ω < RQ < 350Ω.
17. Outputs are impedance controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175Ω < RQ < 350Ω.
18. VREF(min) = 0.68V or 0.46VDDQ, whichever is larger, VREF(max) = 0.95V or 0.54VDDQ, whichever is smaller.
Document Number: 001-54142 Rev. *B
Page 16 of 23
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CY7C13201KV18
Electrical Characteristics
(continued)
DC Electrical Characteristics
Over the Operating Range[12]
Parameter
IDD
[19]
ISB1
Description
VDD Operating Supply
Automatic Power Down
Current
Test Conditions
VDD = Max,
IOUT = 0 mA,
f = fMAX = 1/tCYC
Max VDD,
Both Ports
Deselected,
VIN ≥ VIH or VIN ≤ VIL
f = fMAX = 1/tCYC,
Inputs Static
Min
Typ
Max
Unit
333 MHz
640
mA
300 MHz
600
mA
250 MHz
530
mA
200 MHz
450
mA
167 MHz
400
mA
333 MHz
290
mA
300 MHz
280
mA
250 MHz
270
mA
200 MHz
250
mA
167 MHz
250
mA
AC Electrical Characteristics
Over the Operating Range[11]
Parameter
Description
Test Conditions
Min
Typ
Max
Unit
VIH
Input HIGH Voltage
VREF + 0.2
–
–
V
VIL
Input LOW Voltage
–
–
VREF – 0.2
V
Note
19. The operation current is calculated with 50% read cycle and 50% write cycle.
Document Number: 001-54142 Rev. *B
Page 17 of 23
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CY7C13201KV18
Capacitance
Tested initially and after any design or process change that may affect these parameters.
Parameter
Description
CIN
Input Capacitance
CO
Output Capacitance
Test Conditions
Max
TA = 25°C, f = 1 MHz, VDD = 1.8V, VDDQ = 1.5V
Unit
4
pF
4
pF
Thermal Resistance
Tested initially and after any design or process change that may affect these parameters.
Parameter
Test Conditions
165 FBGA Package
Unit
Test conditions follow standard test methods and
procedures for measuring thermal impedance, in
accordance with EIA/JESD51.
13.7
°C/W
3.73
°C/W
Description
ΘJA
Thermal Resistance
(Junction to Ambient)
ΘJC
Thermal Resistance
(Junction to Case)
Figure 5. AC Test Loads and Waveforms
VREF = 0.75V
VREF
0.75V
VREF
OUTPUT
Z0 = 50Ω
Device
Under
Test
ZQ
RL = 50Ω
VREF = 0.75V
R = 50Ω
ALL INPUT PULSES
1.25V
0.75V
OUTPUT
Device
Under
Test ZQ
RQ =
250Ω
(a)
0.75V
INCLUDING
JIG AND
SCOPE
5 pF
[20]
0.25V
Slew Rate = 2 V/ns
RQ =
250Ω
(b)
Note
20. Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V, VREF = 0.75V, RQ = 250Ω, VDDQ = 1.5V, input pulse
levels of 0.25V to 1.25V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of AC Test Loads and Waveforms.
Document Number: 001-54142 Rev. *B
Page 18 of 23
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CY7C13201KV18
Switching Characteristics
Over the Operating Range[20, 21]
Cypress Consortium
Parameter Parameter
Description
VDD(Typical) to the First Access[22]
tPOWER
333 MHz
300 MHz
250 MHz
200 MHz
167 MHz
Min Max Min Max Min Max Min Max Min Max
1
–
1
–
1
–
1
–
1
–
Unit
ms
tCYC
tKHKH
K Clock and C Clock Cycle Time
3.0
8.4
3.3
8.4
4.0
8.4
5.0
8.4
6.0
8.4
ns
tKH
tKHKL
Input Clock (K/K and C/C) HIGH
1.20
–
1.32
–
1.6
–
2.0
–
2.4
–
ns
tKL
tKLKH
Input Clock (K/K and C/C) LOW
1.20
–
1.32
–
1.6
–
2.0
–
2.4
–
ns
tKHKH
tKHKH
K Clock Rise to K Clock Rise and C 1.35
to C Rise (Rising Edge to Rising
Edge)
–
1.49
–
1.8
–
2.2
–
2.7
–
ns
tKHCH
tKHCH
K/K Clock Rise t o C/C Clock Rise
(Rising Edge to Rising Edge)
1.30
0.0
1.45
0.0
1.8
0.0
2.2
0.0
2.7
ns
0.0
Setup Times
tSA
tAVKH
Address Setup to K Clock Rise
0.4
–
0.4
–
0.5
–
0.6
–
0.7
–
ns
tSC
tIVKH
Control Setup to K Clock Rise
(LD, R/W)
0.4
–
0.4
–
0.5
–
0.6
–
0.7
–
ns
tSCDDR
tIVKH
Double Data Rate Control Setup to
Clock (K/K) Rise
(BWS0, BWS1, BWS2, BWS3)
0.3
–
0.3
–
0.35
–
0.4
–
0.5
–
ns
tSD
tDVKH
D[X:0] Setup to Clock (K/K) Rise
0.3
–
0.3
–
0.35
–
0.4
–
0.5
–
ns
Hold Times
tHA
tKHAX
Address Hold after K Clock Rise
0.4
–
0.4
–
0.5
–
0.6
–
0.7
–
ns
tHC
tKHIX
Control Hold after K Clock Rise
(LD, R/W)
0.4
–
0.4
–
0.5
–
0.6
–
0.7
–
ns
tHCDDR
tKHIX
Double Data Rate Control Hold after 0.3
Clock (K/K) Rise
(BWS0, BWS1, BWS2, BWS3)
–
0.3
–
0.35
–
0.4
–
0.5
–
ns
tHD
tKHDX
D[X:0] Hold after Clock (K/K) Rise
–
0.3
–
0.35
–
0.4
–
0.5
–
ns
0.3
Notes
21. When a part with a maximum frequency above 167 MHz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is operated
and outputs data with the output timings of that frequency range.
22. This part has an internal voltage regulator; tPOWER is the time that the power is supplied above VDD min initially before a read or write operation can be initiated.
Document Number: 001-54142 Rev. *B
Page 19 of 23
[+] Feedback
CY7C13201KV18
Switching Characteristics (continued)
Over the Operating Range[20, 21]
Cypress Consortium
Parameter Parameter
333 MHz
Description
300 MHz
250 MHz
200 MHz
167 MHz
Min Max Min Max Min Max Min Max Min Max
Unit
Output Times
tCO
tCHQV
C/C Clock Rise (or K/K in Single
Clock Mode) to Data Valid
–
0.45
–
0.45
–
0.45
–
0.45
–
0.50
ns
tDOH
tCHQX
Data Output Hold after Output C/C –0.45
Clock Rise (Active to Active)
–
–0.45
–
–0.45
–
–0.45
–
–0.50
–
ns
tCCQO
tCHCQV
C/C Clock Rise to Echo Clock Valid
–
0.45
–
0.45
–
0.45
–
0.45
–
0.50
ns
tCQOH
tCHCQX
Echo Clock Hold after C/C Clock
Rise
–0.45
–
–0.45
–
–0.45
–
–0.45
–
–0.50
–
ns
tCQD
tCQHQV
Echo Clock High to Data Valid
–
0.25
–
0.27
–
0.30
–
0.35
–
0.40
ns
tCQDOH
tCQHQX
Echo Clock High to Data Invalid
–0.25
–
–0.27
–
–0.30
–
–0.35
–
–0.40
–
ns
[23]
1.25
–
1.40
–
1.75
–
2.25
–
2.75
–
ns
1.25
–
1.40
–
1.75
–
2.25
–
2.75
–
ns
–
0.45
–
0.45
–
0.45
–
0.45
–
0.50
ns
–0.45
–
–0.45
–
–0.45
–
–0.45
–
–0.50
–
ns
tCQH
tCQHCQL
Output Clock (CQ/CQ) HIGH
tCQHCQH
tCQHCQH
CQ Clock Rise to CQ Clock Rise
(Rising Edge to Rising Edge) [23]
tCHZ
tCHQZ
Clock (C/C) Rise to High-Z
(Active to High-Z) [24, 25]
tCLZ
tCHQX1
Clock (C/C) Rise to Low-Z [24, 25]
PLL Timing
tKC Var
tKC Var
Clock Phase Jitter
–
0.20
–
0.20
–
0.20
–
0.20
–
0.20
ns
tKC lock
tKC lock
PLL Lock Time (K, C)
20
–
20
–
20
–
20
–
20
–
μs
tKC Reset
tKC Reset
K Static to PLL Reset
30
–
30
–
30
–
30
–
30
–
ns
Notes
23. These parameters are extrapolated from the input timing parameters (tCYC/2 - 250 ps, where 250 ps is the internal jitter). These parameters are only guaranteed by
design and are not tested in production.
24. tCHZ, tCLZ are specified with a load capacitance of 5 pF as in (b) of AC Test Loads and Waveforms. Transition is measured ±100 mV from steady-state voltage.
25. At any voltage and temperature tCHZ is less than tCLZ and tCHZ less than tCO.
Document Number: 001-54142 Rev. *B
Page 20 of 23
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CY7C13201KV18
Switching Waveforms
Figure 6. Read/Write/Deselect Sequence[26, 27, 28]
READ
2
NOP
1
READ
3
NOP
4
NOP
5
WRITE
6
WRITE
7
READ
8
A3
A4
9
10
K
tKH
tKL
tKHKH
tCYC
K
LD
tSC tHC
R/W
A
A0
tSA
A2
A1
tHD
tHA
tHD
tSD
DQ
Q00
t KHCH
t CLZ
Q01
Q10
Q11
tSD
D20
D21
D30
D31
Q40
Q41
t CQDOH
t CHZ
tDOH
tCO
t CQD
C
t KHCH
tKH
tKL
tCYC
tKHKH
C#
tCQOH
tCCQO
CQ
tCQOH
tCCQO
tCQH
tCQHCQH
CQ#
DON’T CARE
UNDEFINED
Notes
26. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, that is, A0 + 1.
27. Outputs are disabled (High-Z) one clock cycle after a NOP.
28. In this example, if address A4 = A3, then data Q40 = D30 and Q41 = D31. Write data is forwarded immediately as read results. This note applies to the whole diagram.
Document Number: 001-54142 Rev. *B
Page 21 of 23
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CY7C13201KV18
Ordering Information
The following table contains only the parts that are currently available. If you do not see what you are looking for, contact your local
sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary page at
http://www.cypress.com/products
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office
closest to you, visit us at http://www.cypress.com/go/datasheet/offices.
Table 2. Ordering Information
Speed
(MHz)
Package
Diagram
Ordering Code
333
CY7C13201KV18-333BZXC
300
CY7C13201KV18-300BZXC
Operating
Range
Package Type
51-85180 165-Ball Fine Pitch Ball Grid Array (13 x 15 x 1.4 mm) Pb-Free Commercial
Package Diagram
Figure 7. 165-Ball FBGA (13 x 15 x 1.4 mm), 51-85180
-
TOP VIEW
BOTTOM VIEW
PIN 1 CORNER
PIN 1 CORNER
Ø0.08 M C
1
2
3
4
5
6
7
8
9
10
11
Ø0.25 M C A B
A
-0.06 (165X)
Ø0.50
+0.14
B
11
C
10
9
8
7
6
5
4
3
1
B
E
C
1.00
F
D
G
15.00±0.10
2
A
D
E
H
F
K
L
M
G
14.00
15.00±0.10
J
H
J
K
N
L
7.00
P
M
R
N
A
P
R
A
B
1.00
5.00
13.00±0.10
Document Number: 001-54142 Rev. *B
0.35±0.06
C
SEATING PLANE
0.15 C
1.40 MAX.
0.53±0.05
0.36
0.25 C
10.00
B
13.00±0.10
0.15(4X)
NOTES :
SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD)
PACKAGE WEIGHT : 0.475g
JEDEC REFERENCE : MO-216 / ISSUE E
PACKAGE CODE : BB0AC
51-85180 *B
Page 22 of 23
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CY7C13201KV18
Document History Page
Document Title: CY7C13201KV18, 18 Mbit DDR II SRAM 2-Word Burst Architecture
Document Number: 001-54142
Rev.
ECN No.
Orig. of
Change
Submission Description of Change
Date
**
2723978
VKN/AESA
06/25/09
*A
2747707
VKN/AESA
08/03/2009
Converted from preliminary to final
Included Soft Error Immunity Data
Modified Ordering Information table by including parts that are available and
modified the disclaimer for the Ordering information
*B
2762555
NJY
09/11/2009
Updated Input and Output Capacitance.
Modified Ordering code disclaimer.
New Data Sheet
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at cypress.com/sales.
Products
PSoC
psoc.cypress.com
Clocks & Buffers
clocks.cypress.com
Wireless
wireless.cypress.com
Memories
memory.cypress.com
Image Sensors
image.cypress.com
© Cypress Semiconductor Corporation, 2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any
circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical,
life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical
components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-54142 Rev. *B
Revised September 11, 2009
Page 23 of 23
QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All product and company names mentioned in this document
are the trademarks of their respective holders.
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