CY7C1324H-133AXCKJ

324 CY7C1324 3.3V 128K x 18 Synchronous Cache RAM Features Functional Description • Supports 117-MHz microprocessor cache systems with zero wait states • 128K by 18 common I/O • Fast clock-to-output times — 7.5 ns (117 MHz) • Two-bit wrap-around counter supporting either interleaved or linear burst sequence • Separate processor and controller address strobes provides direct interface with the processor and external cache controller • Synchronous self-timed write • Asynchronous output enable • I/Os capable of 2.5–3.3V operation • JEDEC-standard pinout • 100-pin TQFP packaging • ZZ “sleep” mode Logic Block Diagram GW The CY7C1324 allows both interleaved or linear burst sequences, selected by the MODE input pin. A HIGH input on MODE selects an interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses can be initiated with the Processor Address Strobe (ADSP) or the cache Controller Address Strobe (ADSC) inputs. Address advancement is controlled by the Address Advancement (ADV) input. A synchronous self-timed write mechanism is provided to simplify the write interface. A synchronous chip enable input and an asynchronous output enable input provide easy control for bank selection and output three-state control. MODE (A0,A1) 2 BURST Q0 CE COUNTER Q1 CLR CLK ADV ADSC ADSP A[16:0] The CY7C1324 is a 3.3V, 128K by 18 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 7.5 ns (117-MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. Q 17 15 BWE ADDRESS CE REGISTER D BW 0 CE1 CE2 CE3 17 128K X 18 MEMORY ARRAY D Q DQ[15:8] BYTEWRITE REGISTERS D Q DQ[7:0] BYTEWRITE REGISTERS BW 1 15 D ENABLE Q CE REGISTER CLK 18 18 INPUT REGISTERS CLK OE ZZ SLEEP CONTROL DQ[15:0] DP[1:0] Pin Selection Guide 7C1324–117 7C1324–100 7C1324–80 7C1324–50 Maximum Access Time (ns) 7.5 8.0 8.5 11.0 Maximum Operating Current (mA) 350 325 300 250 Maximum Standby Current (mA) 1.0 1.0 1.0 1.0 Pentium is a registered trademark of Intel Corporation. Cypress Semiconductor Corporation Document #: 38-05077 Rev. ** • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised September 4, 2001 CY7C1324 Pin Configuration A9 A8 81 82 ADSP ADV 83 84 BWE GW CLK OE ADSC 85 86 87 88 VSS 89 VDD 90 CE3 91 BWS0 92 93 NC NC BWS1 94 95 CE2 96 97 A7 CE1 98 NC 1 80 NC 2 79 A10 NC NC 3 78 NC VDDQ 4 77 VDDQ VSS NC 5 76 6 75 VSS NC 7 74 DP0 8 73 DQ7 DQ9 9 72 DQ6 VSS 10 71 VSS VDDQ 11 70 VDDQ DQ10 12 69 DQ5 DQ11 13 68 DQ4 NC 14 67 VDD NC 15 66 VSS NC 16 65 VSS 17 64 VDD ZZ DQ12 18 63 DQ3 DQ13 19 62 DQ2 VDDQ 20 61 VDDQ VSS 21 60 VSS DQ14 22 59 DQ1 DQ15 23 58 DP1 NC 24 57 DQ0 NC 25 56 NC VSS 26 55 VSS VDDQ NC 27 54 28 53 VDDQ NC NC 29 52 NC NC 30 51 NC Document #: 38-05077 Rev. ** 35 36 37 38 39 40 41 42 45 46 47 48 49 50 A2 A1 A0 DNU DNU VSS VDD DNU DNU A11 A12 A13 A14 A15 A16 NC 44 34 A3 43 33 A4 CY7C1324 32 31 NC DQ8 MODE A5 BYTE1 99 100 A6 100-Lead TQFP BYTE0 Page 2 of 16 CY7C1324 Functional Description (continued) Single Write Accesses Initiated by ADSP This access is initiated when the following conditions are satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted active, and (2) ADSP is asserted LOW. The addresses presented are loaded into the address register and the burst counter/control logic and delivered to the RAM core. The write inputs (GW, BWE, and BWS[1:0]) are ignored during this first clock cycle. If the write inputs are asserted active (see Write Cycle Descriptions table for appropriate states that indicate a write) on the next clock rise, the appropriate data will be latched and written into the device. Byte writes are allowed. During byte writes, BWS0 controls DQ[7:0] and DP0 while BWS1 controls DQ[15:8] and DP1. All I/Os are three-stated during a byte write. Since these are common I/O devices, the asynchronous OE input signal must be deasserted and the I/Os must be three-stated prior to the presentation of data to DQ[15:0] and DP[1:0]. As a safety precaution, the data lines are three-stated once a write cycle is detected, regardless of the state of OE. Single Write Accesses Initiated by ADSC This write access is initiated when the following conditions are satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted active, (2) ADSC is asserted LOW, (3) ADSP is deasserted HIGH, and (4) the write input signals (GW, BWE, and BWS[1:0]) indicate a write access. ADSC is ignored if ADSP is active LOW. The addresses presented are loaded into the address register, burst counter/control logic and delivered to the RAM core. The information presented to DQ[15:0] and DP[1:0] will be written into the specified address location. Byte writes are allowed, with BWS0 controlling DQ[7:0] and DP0 while BWS1 controlling DQ[15:8] and DP1. All I/Os are three-stated when a write is detected, even a byte write. Since these are common I/O devices, the asynchronous OE input signal must be deasserted and the I/Os must be three-stated prior to the presentation of data to DQ[15:0] and DP[1:0]. As a safety precaution, the data lines are three-stated once a write cycle is detected, regardless of the state of OE. Single Read Accesses A single read access is initiated when the following conditions are satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted active, and (2) ADSP or ADSC is asserted LOW (if the access is initiated by ADSC, the write inputs must be deasserted during this first cycle). The address presented to the address inputs is latched into the Address Register, burst counter /control logic and presented to the memory core. If the OE Document #: 38-05077 Rev. ** input is asserted LOW, the requested data will be available at the data outputs a maximum to tCDV after clock rise. ADSP is ignored if CE1 is HIGH. Burst Sequences This family of devices provide a 2-bit wrap around burst counter inside the SRAM. The burst counter is fed by A[1:0], and can follow either a linear or interleaved burst order. The burst order is determined by the state of the MODE input. A LOW on MODE will select a linear burst sequence. A HIGH on MODE will select an interleaved burst order. Leaving MODE unconnected will cause the device to default to a interleaved burst sequence. Table 1. Counter Implementation for the Intel Pentium®/80486 Processor’s Sequence First Address AX + 1, Ax 00 01 10 11 Second Address AX + 1, Ax 01 00 11 10 Third Address AX + 1, Ax 10 11 00 01 Fourth Address AX + 1, Ax 11 10 01 00 Table 2. Counter Implementation for a Linear Sequence First Address AX + 1, Ax 00 01 10 11 Second Address AX + 1, Ax 01 10 11 00 Third Address AX + 1, Ax 10 11 00 01 Fourth Address AX + 1, Ax 11 00 01 10 Sleep Mode The ZZ input pin is an asynchronous input. Asserting a HIGH input on ZZ places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the “sleep” mode. CE1, CE2, CE3, ADSP, and ADSC must remain inactive for the duration of tZZREC after the ZZ input returns low Page 3 of 16 CY7C1324 Cycle Description Table[1, 2, 3] Cycle Description ADD Used CE1 CE3 CE2 ZZ ADSP WE OE CLK DQ Deselected Cycle, Power-down None H X X L X L X X X L-H High-Z Deselected Cycle, Power-down None L X L L L X X X X L-H High-Z Deselected Cycle, Power-down None L H X L L X X X X L-H High-Z Deselected Cycle, Power-down None L X L L H L X X X L-H High-Z Deselected Cycle, Power-down None X X X L H L X X X L-H High-Z SNOOZE MODE, Power-down None X X X H X X X X X X HIGH-Z READ Cycle, Begin Burst External L L H L L X X X L L-H Q READ Cycle, Begin Burst External L L H L L X X X H L-H High-Z WRITE Cycle, Begin Burst External L L H L H L X L X L-H D READ Cycle, Begin Burst External L L H L H L X H L L-H Q READ Cycle, Begin Burst External L L H L H L X H H L-H High-Z READ Cycle, Continue Burst Next X X X L H H L H L L-H Q READ Cycle, Continue Burst Next X X X L H H L H H L-H High-Z READ Cycle, Continue Burst Next H X X L X H L H L L-H Q READ Cycle, Continue Burst Next H X X L X H L H H L-H High-Z WRITE Cycle, Continue Burst Next X X X L H H L L X L-H D WRITE Cycle, Continue Burst Next H X X L X H L L X L-H D READ Cycle, Suspend Burst Current X X X L H H H H L L-H Q READ Cycle, Suspend Burst Current X X X L H H H H H L-H High-Z READ Cycle, Suspend Burst Current H X X L X H H H L L-H Q READ Cycle, Suspend Burst Current H X X L X H H H H L-H High-Z WRITE Cycle, Suspend Burst Current X X X L H H H L X L-H D WRITE Cycle, Suspend Burst Current H X X L X H H L X L-H D ADSP ADV Notes: 1. X=Don’t Care”, 1=Logic HIGH, 0=Logic LOW. 2. The SRAM always initiates a read cycle when ADSP asserted, regardless of the state of GW, BWE, or BWS[1:0]. Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state. OE is a “Don't Care” for the remainder of the write cycle. 3. OE is asynchronous and is not sampled with the clock rise. During a read cycle DQ = High-Z when OE is inactive, and DQ=data when OE is active. Document #: 38-05077 Rev. ** Page 4 of 16 CY7C1324 Pin Descriptions TQFP Pin Number 85 Name ADSC I/O InputSynchronous 84 ADSP InputSynchronous 36, 37 A[1:0] InputSynchronous A1, A0 Address Inputs, These inputs feed the on-chip burst counter as the LSBs as well as being used to access a particular memory location in the memory array. 49–44, 80–82, 99, 100, 32–35 94, 93 A[16:2] InputSynchronous Address Inputs used in conjunction with A[1:0] to select one of the 128K address locations. Sampled at the rising edge of the CLK, if CE1, CE2, and CE3 are sampled active, and ADSP or ADSC is active LOW. BWS[1:0] InputSynchronous 83 ADV InputSynchronous Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes. Sampled on the rising edge. BWS0 controls DQ[7:0] and DP0, BWS1 controls DQ[15:8] and DP1. See Write Cycle Descriptions table for further details. Advance Input used to advance the on-chip address counter. When LOW the internal burst counter is advanced in a burst sequence. The burst sequence is selected using the MODE input. 87 BWE 88 GW InputSynchronous InputSynchronous Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted LOW to conduct a byte write. Global Write Input, active LOW. Sampled on the rising edge of CLK. This signal is used to conduct a global write, independent of the state of BWE and BWS[1:0]. Global writes override byte writes. 89 98 CLK CE1 97 CE2 Input-Clock InputSynchronous InputSynchronous Clock Input. Used to capture all synchronous inputs to the device. Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 and CE3, to select/deselect the device. CE1 gates ADSP. Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3 to select/deselect the device. 92 CE3 InputSynchronous Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select/deselect the device. 86 OE InputAsynchronous Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins. 64 ZZ InputAsynchronous 31 MODE - 23, 22, 19, 18, 13, 12, 9, 8, 73, 72, 69, 68, 63, 62, 59, 58 DQ[15:0] I/OSynchronous Snooze Input. Active HIGH asynchronous. When HIGH, the device enters a low-power standby mode in which all other inputs are ignored, but the data in the memory array is maintained. Leaving ZZ floating or NC will default the device into an active state. Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order. Pulled LOW selects the linear burst order. When left floating or NC, defaults to interleaved burst order. Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by A[17:0] during the previous clock rise of the read cycle. The direction of the pins is controlled by OE in conjunction with the internal control logic. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQ[15:0] and DP[1:0] are placed in a three-state condition. The outputs are automatically three-stated when a WRITE cycle is detected. 74, 24 DP[1:0] I/OSynchronous Bidirectional Data Parity lines. These behave identical to DQ[15:0] described above. These signals can be used as parity bits for bytes 0 and 1 respectively. 15, 41, 65, 91 VDD Power Supply Power supply inputs to the core of the device. Should be connected to 3.3V power supply. Document #: 38-05077 Rev. ** Description Address Strobe from Controller, sampled on the rising edge of CLK. When asserted LOW, A[16:0] is captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. Address Strobe from Processor, sampled on the rising edge of CLK. When asserted LOW, A[16:0] is captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH. Page 5 of 16 CY7C1324 Pin Descriptions TQFP Pin Number Name I/O Description 5, 10, 17, 21, 26, 40, 55, 60, 67, 71, 76, 90 4, 11, 20, 27, 54, 61, 70, 77 1–3, 6, 7, 14, 16, 25, 28–30, 50–53, 56, 57, 66, 75, 78, 79, 95–96 VSS NC - No connects. 38, 39, 42, 43 DNU - Do not use pins. Should be left unconnected or tied LOW. VDDQ Ground Ground for the device. Should be connected to ground of the system. I/O Power Supply Power supply for the I/O circuitry. Should be connected to a 2.5 or 3.3V power supply. Write Cycle Descriptions[1, 2, 3, 4] GW BWE BWS1 BWS0 Read Function 1 1 X X Read 1 0 1 1 Write Byte 0 - DQ[7:0] and DP0 1 0 1 0 Write Byte 1 - DQ[15:8] and DP1 1 0 0 1 Write All Bytes 1 0 0 0 Write All Bytes 0 X X X ZZ Mode Electrical Characteristics Parameter Description Test Conditions IDDZZ Snooze mode standby current ZZ > VDD − 0.2V 10 mA tZZS Device operation to ZZ ZZ > VDD − 0.2V 2tCYC ns tZZREC ZZ recovery time ZZ < 0.2V Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Min Max 2tCYC Unit ns Current into Outputs (LOW) ........................................ 20 mA Static Discharge Voltage .......................................... >2001V (per MIL-STD-883, Method 3015) Storage Temperature ...................................–65°C to +150°C Latch-Up Current.................................................... >200 mA Ambient Temperature with Power Applied...............................................–55°C to +125°C Operating Range Supply Voltage on VDD Relative to GND ............... –0.5V to +4.6V Range Ambient Temperature[6] DC Voltage Applied to Outputs in High Z State[5] ...............................................–0.5V to VDD + 0.5V Com’l 0°C to +70°C VDD VDDQ 3.135V to 3.6V 2.375V to VDD DC Input Voltage[5] ...........................................–0.5V to VDD + 0.5V Notes: 4. When a write cycle is detected, all I/Os are three-stated, even during byte writes. 5. Minimum voltage equals –2.0V for pulse durations of less than 20 ns. 6. TA is the case temperature. Document #: 38-05077 Rev. ** Page 6 of 16 CY7C1324 Electrical Characteristics Over the Operating Range 7C1324 Parameter VOH VOL Description Test Conditions Output HIGH Voltage Output LOW Voltage Min. Max. Unit VDDQ = 3.3V, VDD = Min., IOH = –4.0 mA 2.4 V VDDQ = 2.5V, VDD = Min., IOH = –2.0 mA 1.7 V VDDQ = 3.3V, VDD = Min., IOL = 8.0 mA 0.4 V VDDQ = 2.5V, VDD = Min., IOL = 2.0 mA 0.7 V VIH Input HIGH Voltage 1.7 VDD + 0.3V V VIL Input LOW Voltage[5] –0.3 0.8 V IX Input Load Current (except ZZ and MODE) GND ≤ VI ≤ VDDQ −1 1 µA Input Current of MODE Input = VSS –30 Input Current of ZZ Input = VSS GND ≤ VI ≤ VDD, Output Disabled [7] IOS Output Short Circuit Current VDD=Max., VOUT=GND IDD VDD Operating Supply Current VDD=Max., Iout=0mA, f=fMAX =1/tCYC. ISB1 Automatic CE Power-Down Current—TTL Inputs Max. VDD, Device Deselected, VIN ≥ VIH or VIN ≤ VIL, f=fMAX, inputs switching –5 µA 5 µA –300 mA 325 mA 10-ns cycle, 100 MHz 300 mA 11-ns cycle, 90 MHz 275 mA 20-ns cycle, 50 MHz 225 mA 8.5-ns cycle, 117 MHz 35 mA 10-ns cycle, 100 MHz 30 mA 11-ns cycle, 90 MHz 25 mA 20-ns cycle, 50 MHz 20 mA 10 mA 8.5-ns cycle, 117 MHz 10 mA 10-ns cycle, 100 MHz 10 mA 11-ns cycle, 90 MHz 10 mA 20-ns cycle, 50 MHz 10 mA All speeds 18 mA Automatic CE Power-Down Current — CMOS Inputs All speeds Max. VDD, Device Deselected, VIN ≥ VDD –0.3V or VIN ≤ 0.3V, f=0, inputs static ISB3 Automatic CE Power-Down Current—CMOS Inputs Max. VDD, Device Deselected, VIN ≥ VDDQ- 0.3V or VIN ≤ 0.3V, f=fMAX, inputs switching Automatic CE Max. VDD, Device Deselected, Power-Down Current — TTL In- VIN ≥ VIH or VIN ≤ VIL, f=0, inputs static puts static, F=0 30 8.5-ns cycle, 117 MHz ISB2 ISB4 µA –5 Input = VDDQ Output Leakage Current µA 5 Input = VDDQ IOZ µA Capacitance[8] Parameter Description CIN Input Capacitance CI/O I/O Capacitance Test Conditions TA = 25°C, f = 1 MHz, VDD = 5.0V Max. Unit 4 pF 4 pF Notes: 7. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. 8. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05077 Rev. ** Page 7 of 16 CY7C1324 AC Test Loads and Waveforms[10] R1 2.5V OUTPUT ALL INPUT PULSES OUTPUT Z0 =50Ω 2.5V RL =50Ω VL =1.5V INCLUDING JIG AND SCOPE (a) 90% 10% 90% 10% R2 5 pF GND ≤ 2.5 ns ≤ 2.5 ns (b) [9] 1324–3 1324–4 Switching Characteristics Over the Operating Range[10] -117 Parameter Description Min. Max. -100 Min. Max. -90 Min. -50 Max. Min. Max. Unit tCYC Clock Cycle Time 8.5 10 11 20 ns tCH Clock HIGH 3.0 4.0 4.5 4.5 ns tCL Clock LOW 3.0 4.0 4.5 4.5 ns tAS Address Set-Up Before CLK Rise 2.0 2.0 2.0 2.0 ns tAH Address Hold After CLK Rise 0.5 0.5 0.5 0.5 ns tCDV Data Output Valid After CLK Rise tDOH Data Output Hold After CLK Rise 2.0 2.0 2.0 2.0 ns 7.5 8.0 8.5 11.0 ns tADS ADSP, ADSC Set-Up Before CLK Rise 2.0 2.0 2.0 2.0 ns tADH ADSP, ADSC Hold After CLK Rise 0.5 0.5 0.5 0.5 ns tWES BWS[1:0], GW,BWE Set-Up Before CLK Rise 2.0 2.0 2.0 2.0 ns tWEH BWS[1:0], GW,BWE Hold After CLK Rise 0.5 0.5 0.5 0.5 ns tADVS ADV Set-Up Before CLK Rise 2.0 2.0 2.0 2.0 ns tADVH ADV Hold After CLK Rise 0.5 0.5 0.5 0.5 ns tDS Data Input Set-Up Before CLK Rise 2.0 2.0 2.0 2.0 ns tDH Data Input Hold After CLK Rise 0.5 0.5 0.5 0.5 ns tCES Chip Enable Set-Up 2.0 2.0 2.0 2.0 ns tCEH Chip Enable Hold After CLK Rise 0.5 0.5 0.5 0.5 ns tCHZ tCLZ [11,12] Clock to High-Z 3.5 [11,12] Clock to Low-Z 0 [11,13] tEOHZ OE HIGH to Output High-Z tEOLZ OE LOW to Output Low-Z[11,13] tEOV OE LOW to Output Valid 3.5 0 3.5 0 0 3.5 0 3.5 3.5 0 3.5 0 3.5 3.5 ns 3.5 0 3.5 ns ns ns 3.5 ns Notes: 9. R1=1667Ω and R2=1538Ω for IOH/IOL= –4/8mA, R1=521Ω and R2=481Ω for IOH/IOL= –2/2mA. 10. Unless otherwise noted, test conditions assume signal transition time of 2.5ns or less, timing reference levels of 1.25V, input pulse levels of 0 to 2.5V, and output loading of the specified IOL/IOH and load capacitance. Shown in (a) and (b) of AC test loads. 11. tCHZ, tCLZ, tEOHZ, and tEOLZ are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage. 12. At any given voltage and temperature, tCHZ (max) is less than tCLZ (min). 13. This parameter is sampled and not 100% tested. Document #: 38-05077 Rev. ** Page 8 of 16 CY7C1324 Timing Diagrams Write Cycle Timing[14, 15] Single Write Burst Write Pipelined Write tCH Unselected tCYC CLK tADH tADS tCL ADSP ignored with CE1 inactive ADSP tADH tADS ADSC initiated write ADSC tADVH tADVS ADV tAS ADD ADV Must Be Inactive for ADSP Write WD1 WD3 WD2 tAH GW tWS tWH WE tCES tWH tWS tCEH CE1 masks ADSP CE1 tCES tCEH Unselected with CE2 CE2 CE3 tCES tCEH OE tDH tDS Data- High-Z In 1a 1a 2a = UNDEFINED 2b 2c 2d 3a High-Z = DON’T CARE Note: 14. WE is the combination of BWE, BW[3:0] and GW to define a write cycle (see Write Cycle Descriptions table). 15. WDx stands for Write Data to Address X. Document #: 38-05077 Rev. ** Page 9 of 16 CY7C1324 Timing Diagrams (continued) Read Cycle Timing[14, 16] Burst Read Single Read tCYC Unselected tCH Pipelined Read CLK tADH tADS tCL ADSP ignored with CE1 inactive ADSP tADS ADSC initiated read ADSC tADVS tADH Suspend Burst ADV tADVH tAS ADD RD1 RD3 RD2 tAH GW tWS tWS tWH WE tCES tCEH tWH CE1 masks ADSP CE1 Unselected with CE2 CE2 tCES tCEH CE3 tCES OE Data Out tCEH tEOV tCDV tOEHZ tDOH 2a 1a 1a 2b 2c 2c 2d 3a tCLZ tCHZ = DON’T CARE = UNDEFINED Note: 16. RDx stands for Read Data from Address X. Document #: 38-05077 Rev. ** Page 10 of 16 CY7C1324 Timing Diagrams (continued) READ/WRITE Timing tCYC tCH tCL CLK tAH tAS ADD A B D C tADH tADS ADSP tADH tADS ADSC tADVH tADVS ADV tCEH tCES CE1 tCEH tCES CE tWEH tWES WE ADSP ignored with CE1 HIGH OE tEOHZ tCLZ Data Q(A) In/Out Q(B) Q (B+1) Q (B+2) Q (B+3) Q(B) D(C) D (C+1) D (C+2) D (C+3) Q(D) tCDV tDOH tCHZ Device originally deselected WE is the combination of BWE, BWS[1:0] and GW to define a write cycle (see Write Cycle Definitions table). CE is the combination of CE2 and CE3. All chip selects need to be active in order to select the device. RAx stands for Read Address X, WA stands for Write Address X, Dx stands for Data-in X, Qx stands for Data-out X. = DON’T CARE Document #: 38-05077 Rev. ** = UNDEFINED Page 11 of 16 CY7C1324 Timing Diagrams (continued) Pipeline Timing tCH tCYC tCL CLK tAS ADD C B A E D F G H tADH tADS ADSP ADSC ADV tCEH tCES CE1 CE tWEH tWES WE ADSP ignored with CE1 HIGH OE tCLZ Data Q(A) Q(B) Q(C) D (E) Q(D) D (F) D (G) D (H) D(C) tCDV tDOH tCHZ Device originally deselected CE is the combination of CE2 and CE3. All chip selects need to be active in order to select the device. RAx stands for Read Address X, WAx stands for Write Address X, Dx stands for Data-in X, Qx stands for Data-out X. = DON’T CARE Document #: 38-05077 Rev. ** = UNDEFINED Page 12 of 16 CY7C1324 Timing Diagrams (continued) OE Switching Waveforms OE tEOV tEOHZ I/Os three-state tEOLZ Document #: 38-05077 Rev. ** Page 13 of 16 CY7C1324 Timing Diagrams (continued) ZZ Mode Timing [17 ,18 CLK ADSP HIGH ADSC CE1 CE2 LOW HIGH CE3 ZZ ICC tZZS ICC(active) ICCZZ tZZREC I/Os Three-state Notes: 17. Device must be deselected when entering ZZ mode. See Cycle Description table for all possible signal conditions to deselect the device. 18. I/Os are in three-state when exiting ZZ sleep mode. Document #: 38-05077 Rev. ** Page 14 of 16 CY7C1324 Ordering Information Speed (MHz) Ordering Code 117 CY7C1324–117AC 100 80 50 Package Name Package Type Operating Range A101 100-Lead Thin Quad Flat Pack Commercial CY7C1324–100AC A101 100-Lead Thin Quad Flat Pack Commercial CY7C1324–80AC A101 100-Lead Thin Quad Flat Pack Commercial CY7C1324–50AC A101 100-Lead Thin Quad Flat Pack Commercial Package Diagram 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101 51-85050-A Document #: 38-05077 Rev. ** Page 15 of 16 © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C1324 Document Title: CY7C1324 3.3V 128K x 18 Synchronous Cache RAM Document Number: 38-05077 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 107337 09/15/01 SZV Change from Spec number: 38-00651 to 38-05077 Document #: 38-05077 Rev. ** Page 16 of 16