032
CY7C1325B
256K x 18 Synchronous
3.3V Cache RAM
Features
Functional Description
• Supports 117-MHz microprocessor cache systems with
zero wait states
• 256K by 18 common I/O
• Fast clock-to-output times
— 7.5 ns (117-MHz version)
• Two-bit wrap-around counter supporting either interleaved or linear burst sequence
• Separate processor and controller address strobes
provide direct interface with the processor and external
cache controller
• Synchronous self-timed write
• Asynchronous output enable
• I/Os capable of 2.5–3.3V operation
• JEDEC-standard pinout
• 100-pin TQFP packaging
• ZZ “sleep” mode
Logic Block Diagram
GW
The CY7C1325B allows both interleaved or linear burst sequences, selected by the MODE input pin. A HIGH selects an
interleaved burst sequence, while a LOW selects a linear burst
sequence. Burst accesses can be initiated with the Processor
Address Strobe (ADSP) or the Cache Controller Address
Strobe (ADSC) inputs. Address advancement is controlled by
the Address Advancement (ADV) input.
A synchronous self-timed write mechanism is provided to simplify the write interface. A synchronous chip enable input and
an asynchronous output enable input provide easy control for
bank selection and output three-state control.
MODE
(A0,A1) 2
BURST Q0
CE COUNTER
Q1
CLR
CLK
ADV
ADSC
ADSP
A[17:0]
The CY7C1325B is a 3.3V, 256K by 18 synchronous cache
RAM designed to interface with high-speed microprocessors
with minimum glue logic. Maximum access delay from clock
rise is 7.5 ns (117-MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address
automatically for the rest of the burst access.
Q
18
16
BWE
ADDRESS
CE REGISTER
D
D
Q
DQ[15:8]
BYTEWRITE
REGISTERS
D
Q
DQ[7:0]
BYTEWRITE
REGISTERS
BW 1
BW 0
CE1
CE2
CE3
16
18
256K X 18
MEMORY
ARRAY
D
ENABLE Q
CE REGISTER
CLK
18
18
INPUT
REGISTERS
CLK
OE
ZZ
SLEEP
CONTROL
DQ[15:0]
DP[1:0]
Selection Guide
7C1325B-117
7C1325B-100
Maximum Access Time (ns)
7.5
8.0
Maximum Operating Current (mA)
350
325
Maximum Standby Current (mA)
10.0
10.0
Intel and Pentium are registered trademarks of Intel Corporation.
Cypress Semiconductor Corporation
Document #: 38-05146 Rev. *A
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised January 18, 2003
CY7C1325B
Pin Configurations
A8
A9
81
82
ADSP
ADV
83
84
BWE
GW
CLK
VSS
VDD
CE3
BWS0
OE
ADSC
85
86
87
88
89
90
91
92
93
NC
NC
CE2
BWS1
94
95
96
97
A7
CE1
98
NC
1
80
NC
2
79
A10
NC
NC
3
78
NC
VDDQ
4
77
VDDQ
VSS
NC
5
76
6
75
VSS
NC
7
74
DP0
8
73
DQ7
DQ9
9
72
DQ6
VSS
10
71
VSS
VDDQ
11
70
VDDQ
DQ10
12
69
DQ5
DQ11
13
68
DQ4
NC
14
67
VDD
NC
15
66
VSS
NC
16
65
VSS
17
64
VDD
ZZ
DQ12
18
63
DQ3
DQ13
19
62
DQ2
VDDQ
20
61
VDDQ
VSS
21
60
VSS
DQ14
22
59
DQ1
DQ15
23
58
DP1
NC
24
57
DQ0
NC
25
56
NC
VSS
26
55
VSS
VDDQ
NC
27
54
28
53
VDDQ
NC
NC
29
52
NC
NC
30
51
NC
Document #: 38-05146 Rev. *A
35
36
37
38
39
40
41
42
45
46
47
48
49
50
A2
A1
A0
DNU
DNU
VSS
VDD
DNU
DNU
A11
A12
A13
A14
A15
A16
A17
44
34
A3
43
33
A4
CY7C1325B
32
31
NC
DQ8
MODE
A5
BYTE1
99
100
A6
100-Lead TQFP
BYTE0
Page 2 of 18
CY7C1325B
Pin Configurations (continued)
119-Ball BGA
1
2
3
4
5
6
7
A
VDDQ
A
A
ADSP
A
A
VDDQ
B
C
NC
NC
CE2
A
A
A
ADSC
VDD
A
A
CE3
A
NC
NC
D
DQb
NC
VSS
NC
VSS
DQPa
NC
E
F
NC
VDDQ
DQb
NC
VSS
VSS
CE1
OE
VSS
VSS
NC
DQa
DQa
VDDQ
G
H
J
NC
DQb
VDDQ
DQb
NC
VDD
BWb
VSS
NC
ADV
GW
VDD
Vss
VSS
NC
NC
DQa
VDD
DQa
NC
VDDQ
K
NC
DQb
VSS
CLK
VSS
NC
DQa
L
DQb
NC
Vss
NC
BWa
DQa
NC
M
N
VDDQ
DQb
DQb
NC
VSS
VSS
BWE
A1
VSS
VSS
NC
DQa
VDDQ
NC
P
NC
DQPb
VSS
A0
VSS
NC
DQa
R
T
NC
A
MODE
VDD
VSS
A
NC
NC
A
A
NC
A
A
ZZ
U
VDDQ
NC
NC
NC
NC
NC
VDDQ
Pin Descriptions
Name
I/O
Description
ADSC
InputSynchronous
Address Strobe from Controller, sampled on the rising edge of CLK. When asserted LOW, A[17:0]
is captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and
ADSC are both asserted, only ADSP is recognized.
ADSP
InputSynchronous
Address Strobe from Processor, sampled on the rising edge of CLK. When asserted LOW, A[17:0]
is captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and
ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH.
A[1:0]
InputSynchronous
A1, A0 address inputs, These inputs feed the on-chip burst counter as the LSBs as well as being
used to access a particular memory location in the memory array.
A[17:2]
InputSynchronous
Address Inputs used in conjunction with A[1:0] to select one of the 256K address locations. Sampled
at the rising edge of the CLK, if CE1, CE2, and CE3 are sampled active, and ADSP or ADSC is active
LOW.
BWS[1:0]
InputSynchronous
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes. Sampled on the
rising edge. BWS0 controls DQ[7:0] and DP0, BWS1 controls DQ[15:8] and DP1. See Write Cycle
Descriptions table for further details.
ADV
InputSynchronous
Advance input used to advance the on-chip address counter. When LOW the internal burst counter
is advanced in a burst sequence. The burst sequence is selected using the MODE input.
BWE
InputSynchronous
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be
asserted LOW to conduct a byte write.
GW
InputSynchronous
Global Write Input, active LOW. Sampled on the rising edge of CLK. This signal is used to conduct
a global write, independent of the state of BWE and BWS[1:0]. Global writes override byte writes.
CLK
Input-Clock
CE1
InputSynchronous
Clock input. Used to capture all synchronous inputs to the device.
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2
and CE3 to select/deselect the device. CE1 gates ADSP.
Document #: 38-05146 Rev. *A
Page 3 of 18
CY7C1325B
Pin Descriptions (continued)
Name
I/O
Description
CE2
InputSynchronous
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with
CE1 and CE3 to select/deselect the device.
CE3
InputSynchronous
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1
and CE2 to select/deselect the device.
OE
InputOutput Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When LOW,
Asynchronous the I/O pins behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input
data pins.
ZZ
InputSnooze Input. Active HIGH asynchronous. When HIGH, the device enters a low-power standby
Asynchronous mode in which all other inputs are ignored, but the data in the memory array is maintained. Leaving
ZZ floating or NC will default the device into an active state. ZZ pin has an internal pull-down.
MODE
-
Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order.
Pulled LOW selects the linear burst order. When left floating or NC, defaults to interleaved burst
order. Mode pin has an internal pull-up.
DQ[15:0]
I/OSynchronous
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by
the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified
by A[17:0] during the previous clock rise of the read cycle. The direction of the pins is controlled by
OE in conjunction with the internal control logic. When OE is asserted LOW, the pins behave as
outputs. When HIGH, DQ[15:0] and DP[1:0] are placed in a three-state condition. The outputs are
automatically three-stated when a WRITE cycle is detected.
DP[1:0]
I/OSynchronous
Bidirectional Data Parity lines. These behave identical to DQ[15:0] described above. These signals
can be used as parity bits for bytes 0 and 1 respectively.
VDD
Power Supply
Power supply inputs to the core of the device. Should be connected to 3.3V power supply.
VSS
Ground
VDDQ
I/O Power
Supply
Ground for the device. Should be connected to ground of the system.
Power supply for the I/O circuitry. Should be connected to a 2.5 or 3.3V power supply.
NC
-
No connects.
DNU
-
Do not use pins. Should be left unconnected or tied LOW.
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. Maximum access delay from
the clock rise (t CDV) is 7.5 ns (117-MHz device).
The CY7C1325B supports secondary cache in systems utilizing either a linear or interleaved burst sequence. The interleaved burst order supports Pentium and i486 processors. The
linear burst sequence is suited for processors that utilize a
linear burst sequence. The burst order is user selectable, and
is determined by sampling the MODE input. Accesses can be
initiated with either the Processor Address Strobe (ADSP) or
the Controller Address Strobe (ADSC). Address advancement
through the burst sequence is controlled by the ADV input. A
two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the
address for the rest of the burst access.
Byte write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BW[3:0]) inputs. A Global Write
Enable (GW) overrides all byte write inputs and writes data to
all four bytes. All writes are simplified with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Selects (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank selection and output three-state control. ADSP is ignored if CE1
is HIGH.
Document #: 38-05146 Rev. *A
Single Read Accesses
A single read access is initiated when the following conditions
are satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted active, and (2) ADSP or ADSC is asserted LOW (if the
access is initiated by ADSC, the write inputs must be deasserted during this first cycle). The address presented to the address inputs is latched into the address register and the burst
counter/control logic and presented to the memory core. If the
OE input is asserted LOW, the requested data will be available
at the data outputs a maximum to tCDV after clock rise. ADSP
is ignored if CE1 is HIGH.
Single Write Accesses Initiated by ADSP
This access is initiated when the following conditions are satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted
active, and (2) ADSP is asserted LOW. The addresses presented are loaded into the address register and the burst
counter/control logic and delivered to the RAM core. The write
inputs (GW, BWE, and BWS[1:0]) are ignored during this first
clock cycle. If the write inputs are asserted active (see Write
Cycle Descriptions table for appropriate states that indicate a
write) on the next clock rise, the appropriate data will be
latched and written into the device. Byte writes are allowed.
During byte writes, BWS0 controls DQ[7:0] and DP0 while
BWS1 controls DQ[15:8] and DP1. All I/Os are three-stated during a byte write. Since these are common I/O devices, the
asynchronous OE input signal must be deasserted and the
Page 4 of 18
CY7C1325B
I/Os must be three-stated prior to the presentation of data to
DQ[15:0] and DP[1:0]. As a safety precaution, the data lines are
three-stated once a write cycle is detected, regardless of the
state of OE.
Single Write Accesses Initiated by ADSC
This write access is initiated when the following conditions are
satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted
active, (2) ADSC is asserted LOW, (3) ADSP is deasserted
HIGH, and (4) the write input signals (GW, BWE, and BWS[1:0])
indicate a write access. ADSC is ignored if ADSP is active LOW.
The addresses presented are loaded into the address register,
burst counter/control logic and delivered to the RAM core. The
information presented to DQ[15:0] and DP[1:0] will be written
into the specified address location. Byte writes are allowed,
with BWS0 controlling DQ[7:0] and DP0 while BWS1 controlling
DQ[15:8] and DP1. All I/Os are three-stated when a write is
detected, even a byte write. Since these are common I/O devices, the asynchronous OE input signal must be deasserted
and the I/Os must be three-stated prior to the presentation of
data to DQ[15:0] and DP[1:0]. As a safety precaution, the data
lines are three-stated once a write cycle is detected, regardless of the state of OE.
Burst Sequences
This family of devices provides a 2-bit wrap-around burst
counter inside the SRAM. The burst counter is fed by A[1:0],
and can follow either a linear or interleaved burst order. The
burst order is determined by the state of the MODE input. A
LOW on MODE will select a linear burst sequence. A HIGH on
MODE will select an interleaved burst order. Leaving MODE
unconnected will cause the device to default to an interleaved
burst sequence.
Document #: 38-05146 Rev. *A
Table 1. Counter Implementation for the Intel®
Pentium®/80486 Processor’s Sequence
First
Address
Second
Address
Third
Address
Fourth
Address
AX + 1, Ax
AX + 1, Ax
AX + 1, Ax
AX + 1, Ax
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Table 2. Counter Implementation for a Linear Sequence
First
Address
Second
Address
Third
Address
Fourth
Address
AX + 1, Ax
AX + 1, Ax
AX + 1, Ax
AX + 1, Ax
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ HIGH
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the
“sleep” mode. CE1, CE2, CE3, ADSP, and ADSC must remain
inactive for the duration of tZZREC after the ZZ input returns
LOW.
Page 5 of 18
CY7C1325B
Cycle Description Table[1, 2, 3]
Cycle Description
ADD
Used
CE1
CE3
CE2
ZZ
ADSP
ADSC
ADV
WE
OE
CLK
DQ
Deselected Cycle, Power-down
None
H
X
X
L
X
L
X
X
X
L-H
High-Z
Deselected Cycle, Power-down
None
L
X
L
L
L
X
X
X
X
L-H
High-Z
Deselected Cycle, Power-down
None
L
H
X
L
L
X
X
X
X
L-H
High-Z
Deselected Cycle, Power-down
None
L
X
L
L
H
L
X
X
X
L-H
High-Z
Deselected Cycle, Power-down
None
X
X
X
L
H
L
X
X
X
L-H
High-Z
SNOOZE MODE, Power-Down
None
X
X
X
H
X
X
X
X
X
X
High-Z
READ Cycle, Begin Burst
External
L
L
H
L
L
X
X
X
L
L-H
Q
READ Cycle, Begin Burst
External
L
L
H
L
L
X
X
X
H
L-H
High-Z
WRITE Cycle, Begin Burst
External
L
L
H
L
H
L
X
L
X
L-H
D
READ Cycle, Begin Burst
External
L
L
H
L
H
L
X
H
L
L-H
Q
READ Cycle, Begin Burst
External
L
L
H
L
H
L
X
H
H
L-H
High-Z
READ Cycle, Continue Burst
Next
X
X
X
L
H
H
L
H
L
L-H
Q
READ Cycle, Continue Burst
Next
X
X
X
L
H
H
L
H
H
L-H
High-Z
READ Cycle, Continue Burst
Next
H
X
X
L
X
H
L
H
L
L-H
Q
READ Cycle, Continue Burst
Next
H
X
X
L
X
H
L
H
H
L-H
High-Z
WRITE Cycle, Continue Burst
Next
X
X
X
L
H
H
L
L
X
L-H
D
WRITE Cycle, Continue Burst
Next
H
X
X
L
X
H
L
L
X
L-H
D
READ Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
L
L-H
Q
READ Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
H
L-H
High-Z
READ Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
L
L-H
Q
READ Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
H
L-H
High-Z
WRITE Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
L
X
L-H
D
WRITE Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
L
X
L-H
D
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
tZZS
tZZREC
Description
Test Conditions
Max
Unit
Snooze mode
standby current
ZZ > VDD − 0.2V
Min
10
mA
Device operation to
ZZ
ZZ > VDD − 0.2V
2tCYC
ns
ZZ recovery time
ZZ < 0.2V
2tCYC
ns
Notes:
1. X = “Don't Care,” 1 = Logic HIGH, 0 = Logic LOW.
2. The SRAM always initiates a read cycle when ADSP asserted, regardless of the state of GW, BWE, or BWS[1:0]. Writes may occur only on subsequent clocks
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state. OE
is a “Don't Care” for the remainder of the write cycle.
3. OE is asynchronous and is not sampled with the clock rise. During a read cycle DQ = High-Z when OE is inactive, and DQ=data when OE is active.
Document #: 38-05146 Rev. *A
Page 6 of 18
CY7C1325B
Write Cycle Descriptions[1, 2, 3, 4]
Function
GW
BWE
BWS1
BWS0
Read
1
1
X
X
Read
1
0
1
1
Write Byte 0 - DQ[7:0] and DP0
1
0
1
0
Write Byte 1 - DQ[15:8] and DP1
1
0
0
1
Write All Bytes
1
0
0
0
Write All Bytes
0
X
X
X
Maximum Ratings
Current into Outputs (LOW) ........................................ 20 mA
(Above which the useful life may be impaired. For user guidelines, not tested.)
Storage Temperature ...................................–65°C to +150°C
Ambient Temperature with
Power Applied...............................................–55°C to +125°C
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.................................................... >200 mA
Operating Range
Ambient
Temperature[6]
VDD
VDDQ
Com’l
0°C to +70°C
3.135V to 3.6V
2.375V to VDD
Ind’l
–40°C +70°C
Supply Voltage on VDD Relative to GND ............... –0.5V to +4.6V
Range
DC Voltage Applied to Outputs
in High Z State[5] ...............................................–0.5V to VDD + 0.5V
DC Input Voltage[5] ...........................................–0.5V to VDD + 0.5V
Electrical Characteristics Over the Operating Range
7C1325B
Parameter
Description
Test Conditions
Min.
VDDQ = 3.3V, VDD = Min., IOH = –4.0 mA
2.4
VDDQ = 2.5V, VDD = Min., IOH = –2.0 mA
2.0
Max.
Unit
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
VDDQ = 3.3V, VDD = Min., IOL = 8.0 mA
0.7
V
VIH
Input HIGH Voltage
VDDQ = 3.3V
2.0
VDD +
0.3V
V
VIH
Input HIGH Voltage
VDDQ = 2.5V
1.7
VDD +
0.3V
V
VIL
Input LOW Voltage[5]
VDDQ = 3.3V
–0.3
0.8
V
VIL
Input LOW Voltage
[5]
VDDQ = 2.5V
–0.3
0.7
V
IX
Input Load Current
(except ZZ and MODE)
GND ≤ VI ≤ VDDQ
−1
1
µA
Input Current of MODE
Input = VSS
–30
Input Current of ZZ
Input = VSS
Input = VDDQ
GND ≤ VI ≤ VDD, Output Disabled
5
–5
V
µA
µA
µA
–5
Input = VDDQ
Output Leakage Current
V
0.4
VDDQ = 2.5V, VDD = Min., IOL = 2.0 mA
IOZ
V
30
µA
5
µA
Notes:
4. When a write cycle is detected, all I/Os are three-stated, even during byte writes.
5. Minimum voltage equals –2.0V for pulse durations of less than 20 ns.
6. TA is the case temperature.
Document #: 38-05146 Rev. *A
Page 7 of 18
CY7C1325B
Electrical Characteristics Over the Operating Range (continued)
7C1325B
Parameter
Description
Test Conditions
Min.
Max.
Unit
–300
mA
IOS
Output Short Circuit Current[7]
VDD = Max., VOUT = GND
IDD
VDD Operating Supply Current
VDD = Max., IOUT = 0 mA,
f = fMAX= 1/tCYC
8.5-ns cycle, 117 MHz
350
mA
10-ns cycle, 100 MHz
325
mA
Automatic CE Power-Down
Current—TTL Inputs
Max. VDD, Device Deselected,
VIN ≥ VIH or VIN ≤ VIL, f = fMAX,
inputs switching
8.5-ns cycle, 117 MHz
125
mA
10-ns cycle, 100 MHz
110
mA
ISB2
Automatic CE Power-Down
Current—CMOS Inputs
Max. VDD, Device Deselected,
VIN ≥ VDD – 0.3V or VIN ≤ 0.3V,
f = 0, inputs static
All speeds
10
mA
ISB3
Automatic CE Power-Down
Current—CMOS Inputs
8.5-ns cycle, 117 MHz
Max. VDD, Device Deselected,
VIN ≥ VDDQ – 0.3V or VIN ≤ 0.3V, 10-ns cycle, 100 MHz
f = fMAX, inputs switching
Automatic CE Power-Down
Current—TTL Inputs
Max. VDD, Device Deselected,
VIN ≥ VDD – 0.3V or VIN ≤ 0.3V,
f = 0, inputs static
ISB1
ISB4
All speeds
95
mA
85
mA
30
mA
Capacitance[8]
Parameter
Description
CIN
Input Capacitance
CI/O
I/O Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VDD = 5.0V
Max.
Unit
4
pF
4
pF
AC Test Loads and Waveforms [9]
R1
2.5V
OUTPUT
Z0 =50Ω
ALL INPUT PULSES
OUTPUT
2.5V
RL =50Ω
R2
5 pF
VL =1.5V
(a)
INCLUDING
JIGAND
SCOPE
10%
GND
Rise Time: 1 V/ns
90%
90%
10%
Fall Time: 1 V/ns
[10]
(b)
Notes:
7. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
8. Tested initially and after any design or process changes that may affect these parameters.
9. Overshoot: VIH(AC) < VDD + 1.5V for t < tTCYC/2; undershoot: VIL(AC) < 0.5V for t < tTCYC/2; power-up: VIH < 2.6V and VDD < 2.4V and VDDQ < 1.4V for
t < 200 ms.
10. R1=1667Ω and R2=1538Ω for IOH/IOL=–4/8 mA, R1=521Ω and R2=481Ω for IOH/IOL=–2/2 mA.
Document #: 38-05146 Rev. *A
Page 8 of 18
CY7C1325B
Switching Characteristics Over the Operating Range[11]
-117
Parameter
Description
Min.
-100
Max.
Min.
Max.
Unit
tCYC
Clock Cycle Time
8.5
10
ns
tCH
Clock HIGH
3.0
4.0
ns
tCL
Clock LOW
3.0
4.0
ns
tAS
Address Set-Up Before CLK Rise
2.0
2.0
ns
tAH
Address Hold After CLK Rise
0.5
0.5
ns
tCDV
Data Output Valid After CLK Rise
tDOH
Data Output Hold After CLK Rise
2.0
2.0
ns
tADS
ADSP, ADSC Set-Up Before CLK Rise
2.0
2.0
ns
tADH
ADSP, ADSC Hold After CLK Rise
0.5
0.5
ns
7.5
8.0
ns
tWES
BWS[1:0], GW, BWE Set-Up Before CLK Rise
2.0
2.0
ns
tWEH
BWS[1:0], GW, BWE Hold After CLK Rise
0.5
0.5
ns
tADVS
ADV Set-Up Before CLK Rise
2.0
2.0
ns
tADVH
ADV Hold After CLK Rise
0.5
0.5
ns
tDS
Data Input Set-Up Before CLK Rise
2.0
2.0
ns
tDH
Data Input Hold After CLK Rise
0.5
0.5
ns
tCES
Chip Enable Set-Up
2.0
2.0
ns
tCEH
Chip Enable Hold After CLK Rise
0.5
0.5
ns
[12, 13]
tCHZ
Clock to High-Z
tCLZ
Clock to Low-Z[12, 13]
tEOHZ
3.5
0
OE HIGH to Output High-Z
tEOLZ
OE LOW to Output Low-Z
tEOV
OE LOW to Output Valid
[12, 14]
[12, 14]
3.5
0
3.5
0
ns
3.5
0
3.5
ns
ns
ns
3.5
ns
Notes:
11. Unless otherwise noted, test conditions assume signal transition time of 2.5 ns or less, timing reference levels of 1.25V, input pulse levels of 0 to 2.5V, and
output loading of the specified IOL/IOH and load capacitance. Shown in (a) and (b) of AC Test Loads.
12. tCHZ, tCLZ, tEOHZ, and tEOLZ are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state
voltage.
13. At any given voltage and temperature, tCHZ (max.) is less than tCLZ (min.).
14. This parameter is sampled and not 100% tested.
Document #: 38-05146 Rev. *A
Page 9 of 18
CY7C1325B
Timing Diagrams
Write Cycle Timing [15, 16]
Single Write
Burst Write
Pipelined Write
tCH
Unselected
tCYC
CLK
tADH
tADS
tCL
ADSP ignored with CE1 inactive
ADSP
tADH
tADS
ADSC initiated write
ADSC
tADVH
tADVS
ADV
tAS
ADD
ADV Must Be Inactive for ADSP Write
WD1
WD3
WD2
tAH
GW
tWS
tWH
WE
tCES
tWH
tWS
tCEH
CE1 masks ADSP
CE1
tCES
tCEH
Unselected with CE2
CE2
CE3
tCES
tCEH
OE
tDH
tDS
Data In
High-Z
1a
1a
2a
= UNDEFINED
2b
2c
2d
3a
High-Z
= DON’T CARE
Notes:
15. WE is the combination of BWE, BW[3:0], and GW to define a write cycle (see Write Cycle Descriptions table).
16. WDx stands for Write Data to Address X.
Document #: 38-05146 Rev. *A
Page 10 of 18
CY7C1325B
Timing Diagrams (continued)
Read Cycle Timing[15, 17]
Burst Read
Single Read
tCYC
Unselected
tCH
Pipelined Read
CLK
tADH
tADS
tCL
ADSP ignored with CE1 inactive
ADSP
tADS
ADSC initiated read
ADSC
tADVS
tADH
Suspend Burst
ADV
tADVH
tAS
ADD
RD1
RD3
RD2
tAH
GW
tWS
tWS
tWH
WE
tCES
tCEH
tWH
CE1 masks ADSP
CE1
Unselected with CE2
CE2
tCES
tCEH
CE3
tCES
OE
Data Out
tCEH
tEOV
tCDV
tOEHZ
tDOH
2a
1a
1a
2b
2c 2c
2d
3a
tCLZ
tCHZ
= DON’T CARE
= UNDEFINED
Note:
17. RDx stands for Read Data from Address X.
Document #: 38-05146 Rev. *A
Page 11 of 18
CY7C1325B
Timing Diagrams (continued)
Read/Write Cycle Timing
tCYC
tCH
tCL
CLK
tAH
tAS
ADD
A
B
D
C
tADH
tADS
ADSP
tADH
tADS
ADSC
tADVH
tADVS
ADV
tCEH
tCES
CE1
tCEH
tCES
CE
tWEH
tWES
WE
ADSP ignored
with CE1 HIGH
OE
tEOHZ
tCLZ
Data
In/Out
Q(A)
Q(B)
Q
(B+1)
Q
(B+2)
Q
(B+3)
Q(B)
D(C)
D
(C+1)
D
(C+2)
D
(C+3)
Q(D)
tCDV
tDOH
tCHZ
Device originally
deselected
WE is the combination of BWE, BWS[1:0], and GW to define a write cycle (see Write Cycle Descriptions table).
CE is the combination of CE2 and CE3. All chip selects need to be active in order to select
the device. RAx stands for Read Address X, WAx stands for Write Address X, Dx stands for Data-in X,
Qx stands for Data-out X.
Document #: 38-05146 Rev. *A
Page 12 of 18
CY7C1325B
Timing Diagrams (continued)
Pipeline Timing
tCH
tCYC
tCL
CLK
tAS
ADD
C
B
A
E
D
F
G
H
tADH
tADS
ADSP
ADSC
ADV
tCEH
tCES
CE1
CE
tWEH
tWES
WE
ADSP ignored
with CE1 HIGH
OE
tCLZ
Data
Q(A)
Q(B)
Q(C)
D (E)
Q(D)
D (F)
D (G)
D
(H)
D(C)
tCDV
tDOH
tCHZ
Device originally
deselected
CE is the combination of CE2 and CE3. All chip selects need to be active in order to select
the device. RAx stands for Read Address X, WAx stands for Write Address X, Dx stands for Data-in X,
Qx stands for Data-out X.
= DON’T CARE
Document #: 38-05146 Rev. *A
= UNDEFINED
Page 13 of 18
CY7C1325B
Timing Diagrams (continued)
OE Switching Waveforms
OE
tEOV
tEOHZ
I/Os
three-state
tEOLZ
Document #: 38-05146 Rev. *A
Page 14 of 18
CY7C1325B
Timing Diagrams (continued)
ZZ Mode Timing [18, 19]
CLK
ADSP
HIGH
ADSC
CE1
CE2
LOW
HIGH
CE3
ZZ
ICC
tZZS
ICC(active)
ICCZZ
tZZREC
I/Os
Three-state
Notes:
18. Device must be deselected when entering ZZ mode. See Cycle Description Table for all possible signal conditions to deselect the device.
19. I/Os are in three-state when exiting ZZ sleep mode.
Document #: 38-05146 Rev. *A
Page 15 of 18
CY7C1325B
Ordering Information
Speed
(MHz)
Ordering Code
117
CY7C1325B-117AC
100
CY7C1325B-100AC
CY7C1325B-100BGC
CY7C1325B-100AI
CY7C1325B-100BGI
Package
Name
A101
A101
BG119
A101
BG119
Package Type
100-Lead Thin Quad Flat Pack
Operating
Range
Commercial
100-Lead Thin Quad Flat Pack
119-Ball BGA
100-Lead Thin Quad Flat Pack
Industrial
119-Ball BGA
Package Diagrams
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
51-85050-A
Document #: 38-05146 Rev. *A
Page 16 of 18
CY7C1325B
Package Diagrams (continued)
119-Lead FBGA (14 x 22 x 2.4 mm) BG119
51-85115
Document #: 38-05146 Rev. *A
Page 17 of 18
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1325B
Document Title: CY7C1325B 256K x 18 Synchronous 3.3V Cache RAM
Document Number: 38-05146
REV.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
109890
09/22/01
SZV
Change from Spec number: 38-00952 to 38-05146
*A
123114
01/18/03
RBI
Added power up requirements to AC test loads and waveforms information.
Document #: 38-05146 Rev. *A
Page 18 of 18
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