CY7C1325H
4-Mbit (256K × 18) Flow-Through
Sync SRAM
4-Mbit (256K × 18) Flow-Through Sync SRAM
Features
6.5 ns (133 MHz version). A 2-bit on-chip counter captures the
first address in a burst and increments the address automatically
for the rest of the burst access. All synchronous inputs are gated
by registers controlled by a positive-edge-triggered Clock Input
(CLK). The synchronous inputs include all addresses, all data
inputs, address-pipelining chip enable (CE1), depth-expansion
chip enables (CE2 and CE3), burst control inputs (ADSC, ADSP,
and ADV), write enables (BW[A:B], and BWE), and global write
(GW). Asynchronous inputs include the output enable (OE) and
the ZZ pin.
■
256K × 18 common I/O
■
3.3 V core power supply (VDD)
■
2.5 V or 3.3 V I/O power supply (VDDQ)
■
Fast clock-to-output times
■
6.5 ns (133 MHz version)
■
Provide high performance 2-1-1-1 access rate
■
User selectable burst counter supporting Intel Pentium
interleaved or linear burst sequences
■
Separate processor and controller address strobes
■
Synchronous self timed write
■
Asynchronous output enable
■
Available in Pb-free 100-pin TQFP package
■
“ZZ” sleep mode option
Functional Description
The CY7C1325H is a 256K × 18 synchronous cache RAM
designed to interface with high speed microprocessors with
minimum glue logic. Maximum access delay from clock rise is
The CY7C1325H allows either interleaved or linear burst
sequences, selected by the MODE input pin. A HIGH selects an
interleaved burst sequence, while a LOW selects a linear burst
sequence. Burst accesses can be initiated with the processor
address strobe (ADSP) or the cache controller address strobe
(ADSC) inputs.
Addresses and chip enables are registered at rising edge of
clock when either address strobe processor (ADSP) or address
strobe controller (ADSC) are active. Subsequent burst
addresses can be internally generated as controlled by the
advance pin (ADV).
The CY7C1325H operates from a +3.3 V core power supply
while all outputs may operate with either a +2.5 or +3.3 V supply.
All
inputs
and
outputs
are
JEDEC-standard
JESD8-5-compatible.
For a complete list of related documentation, click here.
Logic Block Diagram
A 0,A1,A
ADDRESS
REGISTER
A[1:0]
MODE
BURST Q1
COUNTER AND
LOGIC
CLR
Q0
ADV
CLK
ADSC
ADSP
BW B
BW A
DQ B ,DQP B
WRITE DRIVER
DQ B ,DQP B
WRITE REGISTER
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
BUFFERS
DQs
DQP A
DQP B
DQ A ,DQP A
WRITE DRIVER
DQ A ,DQP A
WRITE REGISTER
BWE
GW
CE 1
CE 2
CE 3
INPUT
REGISTERS
ENABLE
REGISTER
OE
ZZ
SLEEP
CONTROL
Cypress Semiconductor Corporation
Document Number: 001-86114 Rev. *D
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 23, 2016
CY7C1325H
Contents
Selection Guide ................................................................ 3
Pin Configurations ........................................................... 3
Pin Definitions .................................................................. 4
Functional Overview ........................................................ 5
Single Read Accesses ................................................ 5
Single Write Accesses Initiated by ADSP ................... 5
Single Write Accesses Initiated by ADSC ................... 5
Burst Sequences ......................................................... 5
Sleep Mode ................................................................. 5
Interleaved Burst Address Table ................................. 6
Linear Burst Address Table ......................................... 6
ZZ Mode Electrical Characteristics .............................. 6
Truth Table ........................................................................ 7
Truth Table for Read/Write .............................................. 8
Maximum Ratings ............................................................. 9
Operating Range ............................................................... 9
Neutron Soft Error Immunity ........................................... 9
Electrical Characteristics ................................................. 9
Document Number: 001-86114 Rev. *D
Capacitance .................................................................... 10
Thermal Resistance ........................................................ 10
AC Test Loads and Waveforms ..................................... 11
Switching Characteristics .............................................. 12
Timing Diagrams ............................................................ 13
Ordering Information ...................................................... 17
Ordering Code Definitions ......................................... 17
Package Diagrams .......................................................... 18
Acronyms ........................................................................ 19
Document Conventions ................................................. 19
Units of Measure ....................................................... 19
Document History Page ................................................. 20
Sales, Solutions, and Legal Information ...................... 21
Worldwide Sales and Design Support ....................... 21
Products .................................................................... 21
PSoC®Solutions ....................................................... 21
Cypress Developer Community ................................. 21
Technical Support ..................................................... 21
Page 2 of 21
CY7C1325H
Selection Guide
Description
133 MHz
Unit
Maximum access time
6.5
ns
Maximum operating current
225
mA
Maximum standby current
40
mA
Pin Configurations
A
45
46
47
48
49
50
A
A
A
A
A
44
43
NC/9M
A
A
41
VDD
NC/18M
42
40
37
A0
VSS
36
A1
39
35
A
38
34
NC/72M
NC/36M
33
Document Number: 001-86114 Rev. *D
81
82
83
84
BWE
GW
OE
ADSC
ADSP
ADV
A
85
86
87
CLK
89
88
VDD
VSS
91
90
BWA
CE3
93
92
NC
96
BWB
NC
97
94
CE2
98
95
A
CE1
99
A
31
VSS
VDDQ
NC
NC
NC
A
VSS
DQB
DQB
VDDQ
VSS
DQB
DQB
DQPB
NC
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
CY7C1325H
A
BYTE B
DQB
DQB
VSS
VDDQ
DQB
DQB
NC
VDD
NC
32
VDDQ
VSS
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
A
NC
NC
NC
100
Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout
A
NC
NC
VDDQ
VSS
NC
DQPA
DQA
DQA
VSS
VDDQ
DQA
DQA
VSS
NC
BYTE A
VDD
ZZ
DQA
DQA
VDDQ
VSS
DQA
DQA
NC
NC
VSS
VDDQ
NC
NC
NC
Page 3 of 21
CY7C1325H
Pin Definitions
Name
I/O
Description
A0, A1, A
InputAddress inputs used to select one of the 256 K address locations. Sampled at the rising edge of
synchronous the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A[1:0] feed the 2
bit counter.
BWA,BWB
InputByte write select inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM. Sampled
synchronous on the rising edge of CLK.
GW
InputGlobal write enable input, active LOW. When asserted LOW on the rising edge of CLK, a global write
synchronous is conducted (all bytes are written, regardless of the values on BW[A:B] and BWE).
BWE
InputByte write enable input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted
synchronous LOW to conduct a byte write.
CLK
Input-clock
Clock input. Used to capture all synchronous inputs to the device. Also used to increment the burst
counter when ADV is asserted LOW, during a burst operation.
CE1
InputChip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2
synchronous and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only when a
new external address is loaded.
CE2
InputChip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1
synchronous and CE3 to select/deselect the device. CE2 is sampled only when a new external address is loaded.
CE3
InputChip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1
synchronous and CE2 to select/deselect the device. CE3 is sampled only when a new external address is loaded.
OE
InputOutput enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When LOW,
asynchronous the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tristated, and act as input data
pins. OE is masked during the first clock of a read cycle when emerging from a deselected state.
ADV
InputAdvance input signal, sampled on the rising edge of CLK. When asserted, it automatically
synchronous increments the address in a burst cycle.
ADSP
InputAddress strobe from processor, sampled on the rising edge of CLK, active LOW. When asserted
synchronous LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded
into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is
ignored when CE1 is deasserted HIGH.
ADSC
InputAddress strobe from controller, sampled on the rising edge of CLK, active LOW. When asserted
synchronous LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded
into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized.
ZZ
InputZZ “sleep” input, active HIGH. When asserted HIGH places the device in a non-time-critical “sleep”
asynchronous condition with data integrity preserved.During normal operation, this pin has to be low or left floating. ZZ
pin has an internal pull-down.
DQs
DQPA,
DQPB
I/OBidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the
synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the
addresses presented during the previous clock rise of the read cycle. The direction of the pins is
controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and
DQP[A:B] are placed in a tristate condition.
VDD
Power supply Power supply inputs to the core of the device.
Ground
Ground for the core of the device.
VDDQ
I/O power
supply
Power supply for the I/O circuitry.
MODE
Inputstatic
VSS
NC
–
Selects burst order. When tied to GND selects linear burst sequence. When tied to VDD or left floating
selects interleaved burst sequence. This is a strap pin and should remain static during device operation.
Mode pin has an internal pull-up.
No connects. Not Internally connected to the die.
Document Number: 001-86114 Rev. *D
Page 4 of 21
CY7C1325H
Pin Definitions (continued)
Name
NC/9M,
NC/18M,
NC/36M,
NC/72M,
NC/144M,
NC/288M,
NC/576M,
NC/1G
I/O
Description
–
No connects. Not internally connected to the die. NC/9M, NC/18M, NC/36M, NC/72M, NC/144M,
NC/288M, NC/576M and NC/1G are address expansion pins that are not internally connected to the die.
Functional Overview
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. Maximum access delay from the
clock rise (t CDV) is 6.5 ns (133 MHz device).
The CY7C1325H supports secondary cache in systems utilizing
either a linear or interleaved burst sequence. The interleaved
burst order supports Pentium and i486 processors. The linear
burst sequence is suited for processors that utilize a linear burst
sequence. The burst order is user-selectable, and is determined
by sampling the MODE input. Accesses can be initiated with
either the processor address strobe (ADSP) or the controller
address strobe (ADSC). Address advancement through the
burst sequence is controlled by the ADV input. A two bit on-chip
wraparound burst counter captures the first address in a burst
sequence and automatically increments the address for the rest
of the burst access.
Byte write operations are qualified with the byte write enable
(BWE) and byte write select (BW[A:B]) inputs. A global write
enable (GW) overrides all byte write inputs and writes data to all
four bytes. All writes are simplified with on-chip synchronous self
timed write circuitry.
Three synchronous chip selects (CE1, CE2, CE3) and an
asynchronous output enable (OE) provide for easy bank
selection and output tristate control. ADSP is ignored if CE1 is
HIGH.
Single Read Accesses
A single read access is initiated when the following conditions
are satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted
active, and (2) ADSP or ADSC is asserted LOW (if the access is
initiated by ADSC, the write inputs must be deasserted during
this first cycle). The address presented to the address inputs is
latched into the address register and the burst counter/control
logic and presented to the memory core. If the OE input is
asserted LOW, the requested data is available at the data
outputs, a maximum to tCDV after clock rise. ADSP is ignored if
CE1 is HIGH.
Single Write Accesses Initiated by ADSP
This access is initiated when the following conditions are
satisfied at clock rise: (1) CE1, CE2, CE3 are all asserted active,
and (2) ADSP is asserted LOW. The addresses presented are
loaded into the address register and the burst inputs (GW, BWE,
and BW[A:B]) are ignored during this first clock cycle. If the write
inputs are asserted active (see Write Cycle Descriptions table for
appropriate states that indicate a write) on the next clock rise, the
Document Number: 001-86114 Rev. *D
appropriate data is latched and written into the device. Byte
writes are allowed. During byte writes, BWA controls DQA and
BWB controls DQB. All I/Os are tristated during a byte write.Since
this is a common I/O device, the asynchronous OE input signal
must be deasserted and the I/Os must be tristated prior to the
presentation of data to DQs. As a safety precaution, the data
lines are tristated after a write cycle is detected, regardless of the
state of OE.
Single Write Accesses Initiated by ADSC
This write access is initiated when the following conditions are
satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted
active, (2) ADSC is asserted LOW, (3) ADSP is deasserted
HIGH, and (4) the write input signals (GW, BWE, and BW[A:B])
indicate a write access. ADSC is ignored if ADSP is active LOW.
The addresses presented are loaded into the address register
and the burst counter/control logic and delivered to the memory
core. The information presented to DQ[A:D] is written into the
specified address location. Byte writes are allowed. During byte
writes, BWA controls DQA, BWB controls DQB. All I/Os are
tristated when a write is detected, even a byte write. Since this
is a common I/O device, the asynchronous OE input signal must
be deasserted and the I/Os must be tristated prior to the presentation of data to DQs. As a safety precaution, the data lines are
tristated after a write cycle is detected, regardless of the state of
OE.
Burst Sequences
The CY7C1325H provides an on-chip two bit wraparound burst
counter inside the SRAM. The burst counter is fed by A[1:0], and
can follow either a linear or interleaved burst order. The burst
order is determined by the state of the MODE input. A LOW on
MODE selects a linear burst sequence. A HIGH on MODE
selects an interleaved burst order. Leaving MODE unconnected
causes the device to default to a interleaved burst sequence.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected prior to entering the “sleep” mode. CEs,
ADSP, and ADSC must remain inactive for the duration of tZZREC
after the ZZ input returns LOW.
Page 5 of 21
CY7C1325H
Interleaved Burst Address Table
Linear Burst Address Table
(MODE = Floating or VDD)
(MODE = GND)
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
Fourth
Address
A1:A0
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
00
01
01
00
Fourth
Address
A1:A0
10
11
00
01
10
11
11
10
01
10
11
00
10
11
00
01
10
11
00
01
11
10
01
00
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
Min
Max
Unit
IDDZZ
Sleep mode standby current
ZZ > VDD– 0.2 V
–
40
mA
tZZS
Device operation to ZZ
ZZ > VDD – 0.2 V
–
2tCYC
ns
tZZREC
ZZ recovery time
ZZ < 0.2 V
2tCYC
–
ns
tZZI
ZZ active to sleep current
This parameter is sampled
–
2tCYC
ns
tRZZI
ZZ inactive to exit sleep current
This parameter is sampled
0
–
ns
Document Number: 001-86114 Rev. *D
Page 6 of 21
CY7C1325H
Truth Table
The Truth Table for part CY7C1325H is as follows. [1, 2, 3, 4, 5]
Cycle Description
Address Used CE1 CE2 CE3 ZZ
ADSP
ADSC ADV WRITE OE CLK
DQ
Deselected cycle, power-down
None
H
X
X
L
X
L
X
X
X
L–H
Tri-state
Deselected cycle, power-down
None
L
L
X
L
L
X
X
X
X
L–H
Tri-state
Deselected cycle, power-down
None
L
X
H
L
L
X
X
X
X
L–H
Tri-state
Deselected cycle, power-down
None
L
L
X
L
H
L
X
X
X
L–H
Tri-state
Deselected cycle, power-down
None
X
X
H
L
H
L
X
X
X
L–H
Tri-state
Sleep mode, power-down
None
X
X
X
H
X
X
X
X
X
X
Tri-state
Read cycle, begin burst
External
L
H
L
L
L
X
X
X
L
L–H
Q
Read cycle, begin burst
External
L
H
L
L
L
X
X
X
H
L–H
Tri-state
Write cycle, begin burst
External
L
H
L
L
H
L
X
L
X
L–H
D
Read cycle, begin burst
External
L
H
L
L
H
L
X
H
L
L–H
Q
Read cycle, begin burst
External
L
H
L
L
H
L
X
H
H
L–H
Tri-state
Read cycle, continue burst
Next
X
X
X
L
H
H
L
H
L
L–H
Q
Read cycle, continue burst
Next
X
X
X
L
H
H
L
H
H
L–H
Tri-state
Read cycle, continue burst
Next
H
X
X
L
X
H
L
H
L
L–H
Q
Read cycle, continue burst
Next
H
X
X
L
X
H
L
H
H
L–H
Tri-state
Write cycle, continue burst
Next
X
X
X
L
H
H
L
L
X
L–H
D
Write cycle, continue burst
Next
H
X
X
L
X
H
L
L
X
L–H
D
Read cycle, suspend burst
Current
X
X
X
L
H
H
H
H
L
L–H
Q
Read cycle, suspend burst
Current
X
X
X
L
H
H
H
H
H
L–H
Tri-state
Read cycle, suspend burst
Current
H
X
X
L
X
H
H
H
L
L–H
Q
Read cycle, suspend burst
Current
H
X
X
L
X
H
H
H
H
L–H
Tri-state
Write cycle, suspend burst
Current
X
X
X
L
H
H
H
L
X
L–H
D
Write cycle, suspend burst
Current
H
X
X
L
X
H
H
L
X
L–H
D
Notes
1. X = “Don’t Care.” H = Logic HIGH, L = Logic LOW.
2. WRITE = L when any one or more Byte Write enable signals (BWA, BWB) and BWE = L or GW = L. WRITE = H when all Byte write enable signals (BWA, BWB),
BWE, GW = H.
3. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
4. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW[A: B]. Writes may occur only on subsequent clocks
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tristate. OE is a don't
care for the remainder of the write cycle.
5. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tristate when OE is inactive
or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document Number: 001-86114 Rev. *D
Page 7 of 21
CY7C1325H
Truth Table for Read/Write
The Truth Table for Read/Write for part CY7C1325H is as follows. [6]
Function
GW
BWE
BWB
BWA
Read
H
H
X
X
Read
H
L
H
H
Write byte A – (DQA and DQPA)
H
L
H
L
Write byte B – (DQB and DQPB)
H
L
L
H
Write all bytes
H
L
L
L
Write all bytes
L
X
X
X
Note
6. X = “Don’t Care.” H = Logic HIGH, L = Logic LOW.
Document Number: 001-86114 Rev. *D
Page 8 of 21
CY7C1325H
Maximum Ratings
Operating Range
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage temperature ................................ –65 °C to +150 °C
Range
Ambient
Temperature
Industrial
–40 °C to +85 °C
Ambient temperature
with power applied ................................... –55 °C to +125 °C
Supply voltage on VDD relative to GND .......–0.5 V to +4.6 V
Supply voltage on VDDQ relative to GND ...... –0.5 V to +VDD
DC voltage applied to outputs
in tristate ...........................................–0.5 V to VDDQ + 0.5 V
DC input voltage ................................. –0.5 V to VDD + 0.5 V
Current into outputs (LOW) ........................................ 20 mA
Static discharge voltage
(per MIL-STD-883, method 3015) .......................... > 2001 V
Latch-up current .................................................... > 200 mA
VDD
VDDQ
3.3 V5% / 2.5 V – 5% to
+ 10%
VDD
Neutron Soft Error Immunity
Parameter
Description
Test
Conditions Typ
Max*
Unit
LSBU
Logical single
bit upsets
25 °C
361
394
FIT/
Mb
LMBU
Logical multi
bit upsets
25 °C
0
0.01
FIT/
Mb
SEL
Single event
latch up
85 °C
0
0.1
FIT/
Dev
* No LMBU or SEL events occurred during testing; this column represents a
statistical 2, 95% confidence limit calculation. For more details refer to Application
Note AN54908 “Accelerated Neutron SER Testing and Calculation of Terrestrial
Failure Rates”.
Electrical Characteristics
Over the Operating Range
Parameter [7, 8]
Description
Test Conditions
Min
Max
Unit
VDD
Power supply voltage
3.135
3.6
V
VDDQ
I/O supply voltage
2.375
VDD
V
VOH
Output HIGH voltage
for 3.3 V I/O, IOH = –4.0 mA
2.4
–
V
for 2.5 V I/O, IOH = –1.0 mA
2.0
–
V
for 3.3 V I/O, IOL = 8.0 mA
–
0.4
V
for 2.5 V I/O, IOL = 1.0 mA
–
0.4
V
for 3.3 V I/O
2.0
VDD + 0.3
V
for 2.5 V I/O
1.7
VDD + 0.3
V
for 3.3 V I/O
–0.3
0.8
V
for 2.5 V I/O
–0.3
0.7
V
Input leakage current except ZZ GND VI VDDQ
and MODE
5
5
A
Input current of MODE
Input = VSS
–30
–
A
Input = VDD
–
5
A
Input current of ZZ
Input = VSS
–5
–
A
Input = VDD
–
30
A
IOZ
Output leakage current
GND VI VDDQ, output disabled
–5
5
A
IDD
VDD operating supply current
VDD = Max, IOUT = 0 mA,
f = fMAX= 1/tCYC
–
225
mA
VOL
VIH
VIL
IX
Output LOW voltage
Input HIGH voltage
Input LOW
voltage[7]
7.5 ns cycle,
133 MHz
Notes
7. Overshoot: VIH(AC) < VDD + 1.5 V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2 V (Pulse width less than tCYC/2).
8. Tpower up: Assumes a linear ramp from 0 V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
Document Number: 001-86114 Rev. *D
Page 9 of 21
CY7C1325H
Electrical Characteristics (continued)
Over the Operating Range
Parameter [7, 8]
Description
Test Conditions
Min
Max
Unit
ISB1
Automatic CE power-down
current – TTL inputs
Max VDD, device deselected,
VIN VIH or VIN VIL, f = fMAX,
inputs switching
7.5 ns cycle,
133 MHz
–
90
mA
ISB2
Automatic CE power-down
current – CMOS inputs
Max VDD, device deselected,
7.5 ns cycle,
VIN VDD – 0.3 V or VIN 0.3 V, 133 MHz
f = 0, inputs static
–
40
mA
ISB3
Automatic CE power-down
current – CMOS inputs
7.5 ns cycle,
Max VDD, device deselected,
VIN VDDQ – 0.3 V or VIN 0.3 V, 133 MHz
f = fMAX, inputs switching
–
75
mA
ISB4
Automatic CE power-down
current – TTL inputs
7.5 ns cycle,
Max VDD, device deselected,
VIN VDD – 0.3 V or VIN 0.3 V, 133 MHz
f = 0, inputs static
–
45
mA
Capacitance
Parameter [9]
Description
CIN
Input capacitance
CCLK
Clock input capacitance
CI/O
Input/Output capacitance
100-pin TQFP
Max
Unit
5
pF
5
pF
5
pF
Test Conditions
100-pin TQFP
Package
Unit
Test conditions follow standard test methods and
procedures for measuring thermal impedance, per
EIA/JESD51.
30.32
°C/W
6.85
°C/W
Test Conditions
TA = 25 C, f = 1 MHz,
VDD = 3.3 V, VDDQ = 3.3 V
Thermal Resistance
Parameter [9]
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
Note
9. Tested initially and after any design or process change that may affect these parameters.
Document Number: 001-86114 Rev. *D
Page 10 of 21
CY7C1325H
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms
3.3 V I/O Test Load
3.3 V
OUTPUT
R = 317
Z0 = 50
VT = 1.5 V
(a)
2.5 V I/O Test Load
5 pF
INCLUDING
JIG AND
SCOPE
2.5 V
OUTPUT
GND
R = 351
VT = 1.25 V
(a)
Document Number: 001-86114 Rev. *D
5 pF
INCLUDING
JIG AND
SCOPE
10%
1 ns
1 ns
(c)
R = 1667
ALL INPUT PULSES
VDDQ
GND
R = 1538
(b)
90%
10%
90%
(b)
OUTPUT
RL = 50
Z0 = 50
ALL INPUT PULSES
VDDQ
OUTPUT
RL = 50
10%
90%
10%
90%
1 ns
1 ns
(c)
Page 11 of 21
CY7C1325H
Switching Characteristics
Over the Operating Range
Parameter [10, 11]
tPOWER
Description
VDD(typical) to the first access [12]
-133
Unit
Min
Max
1
–
ms
Clock
tCYC
Clock cycle time
7.5
–
ns
tCH
Clock HIGH
2.5
–
ns
tCL
Clock LOW
2.5
–
ns
Output Times
tCDV
Data output valid after CLK rise
–
6.5
ns
tDOH
Data output hold after CLK rise
2.0
–
ns
0
–
ns
–
3.5
ns
–
3.5
ns
0
–
ns
–
3.5
ns
[13, 14, 15]
tCLZ
Clock to low Z
tCHZ
Clock to high Z [13, 14, 15]
tOEV
OE LOW to output valid
tOELZ
tOEHZ
OE LOW to output low Z
[13, 14, 15]
OE HIGH to output high Z
[13, 14, 15]
Setup Times
tAS
Address setup before CLK rise
1.5
–
ns
tADS
ADSP, ADSC setup before CLK rise
1.5
–
ns
tADVS
ADV setup before CLK rise
1.5
–
ns
tWES
GW, BWE, BWX setup before CLK rise
1.5
–
ns
tDS
Data input setup before CLK rise
1.5
–
ns
tCES
Chip enable setup
1.5
–
ns
tAH
Address hold after CLK rise
0.5
–
ns
tADH
ADSP, ADSC hold after CLK rise
0.5
–
ns
tWEH
GW, BWE, BWX hold after CLK rise
0.5
–
ns
tADVH
ADV hold after CLK rise
0.5
–
ns
tDH
Data input hold after CLK rise
0.5
–
ns
tCEH
Chip enable hold after CLK rise
0.5
–
ns
Hold Times
Notes
10. Timing reference level is 1.5 V when VDDQ = 3.3 V and is 1.25 V when VDDQ = 2.5 V.
11. Test conditions shown in (a) of Figure 2 on page 11 unless otherwise noted.
12. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a read or write operation can
be initiated.
13. tCHZ, tCLZ, tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of Figure 2 on page 11. Transition is measured ± 200 mV from steady-state voltage.
14. At any voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus.
These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve high
Z prior to low Z under the same system conditions.
15. This parameter is sampled and not 100% tested.
Document Number: 001-86114 Rev. *D
Page 12 of 21
CY7C1325H
Timing Diagrams
Figure 3. Read Cycle Timing [16]
tCYC
CLK
t
t ADS
CH
t CL
tADH
ADSP
t ADS
tADH
ADSC
t AS
tAH
A1
ADDRESS
A2
t
GW, BWE,BW
WES
t
WEH
[A:B]
t CES
Deselect Cycle
t CEH
CE
t
ADVS
t
ADVH
ADV
ADV suspends burst
OE
t OEV
t OEHZ
t CLZ
Data Out (Q)
High-Z
Q(A1)
t CDV
t OELZ
t CHZ
t DOH
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
t CDV
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Burst wraps around
to its initial state
Single READ
BURST
READ
DON’T CARE
UNDEFINED
Note
16. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
Document Number: 001-86114 Rev. *D
Page 13 of 21
CY7C1325H
Timing Diagrams (continued)
Figure 4. Write Cycle Timing [17, 18]
t CYC
CLK
t
t ADS
CH
t
CL
tADH
ADSP
t ADS
ADSC extends burst
tADH
t ADS
tADH
ADSC
t AS
tAH
A1
ADDRESS
A2
A3
Byte write signals are ignored for first cycle when
ADSP initiates burst
t WES tWEH
BWE,
[A:B]
BW
t
WES
t
WEH
GW
t CES
tCEH
CE
t ADVS tADVH
ADV
ADV suspends burst
OE
t
Data in (D)
High-Z
t
DS
t
DH
D(A1)
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
OEHZ
Data Out (Q)
BURST READ
Single WRITE
BURST WRITE
DON’T CARE
Extended BURST WRITE
UNDEFINED
Notes
17. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
18. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW[A:B] LOW.
Document Number: 001-86114 Rev. *D
Page 14 of 21
CY7C1325H
Timing Diagrams (continued)
Figure 5. Read/Write Timing [19, 20, 21]
tCYC
CLK
t
t ADS
CH
t
CL
tADH
ADSP
ADSC
t AS
ADDRESS
A1
tAH
A2
A3
A4
t
BWE, BW
WES
t
A5
A6
D(A5)
D(A6)
WEH
[A:B]
t CES
tCEH
CE
ADV
OE
t DS
Data In (D)
Data Out (Q)
High-Z
t
OEHZ
Q(A1)
tDH
t OELZ
D(A3)
t CDV
Q(A4)
Q(A2)
Back-to-Back READs
Single WRITE
Q(A4+1)
BURST READ
DON’T CARE
Q(A4+2)
Q(A4+3)
Back-to-Back
WRITEs
UNDEFINED
Notes
19. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
20. The data bus (Q) remains in High Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC.
21. GW is HIGH.
Document Number: 001-86114 Rev. *D
Page 15 of 21
CY7C1325H
Timing Diagrams (continued)
Figure 6. ZZ Mode Timing [22, 23]
CLK
t
ZZ
I
t
ZZ
ZZREC
t ZZI
SUPPLY
I
t RZZI
DDZZ
A LL INPUTS
(except ZZ)
Outputs (Q)
DESELECT or READ Only
High-Z
DON’T CARE
Notes
22. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.
23. DQs are in High Z when exiting ZZ sleep mode.
Document Number: 001-86114 Rev. *D
Page 16 of 21
CY7C1325H
Ordering Information
The table below contains only the parts that are currently available. If you don’t see what you are looking for, please contact your local
sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary page at
http://www.cypress.com/products
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office
closest to you, visit us at http://www.cypress.com/go/datasheet/offices
Speed
(MHz)
133
Package
Diagram
Ordering Code
CY7C1325H-133AXI
Part and Package Type
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
Operating
Range
Industrial
Ordering Code Definitions
CY
7
C
1325
H - 133
A
X
I
Temperature Range:
I = Industrial
Pb-free
Package Type:
A = 100-pin TQFP
Speed Grade: 133 MHz
Process Technology: H 90nm
Part Identifier: 1325 = FT, 256Kb × 18 (4Mb)
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 001-86114 Rev. *D
Page 17 of 21
CY7C1325H
Package Diagrams
Figure 7. 100-pin TQFP (14 × 20 × 1.4 mm) Package Outline, 51-85050
51-85050 *E
Document Number: 001-86114 Rev. *D
Page 18 of 21
CY7C1325H
Acronyms
Acronym
Document Conventions
Description
Units of Measure
CMOS
Complementary Metal Oxide Semiconductor
CE
Chip Enable
°C
degree Celsius
CEN
Clock Enable
MHz
megahertz
EIA
Electronic Industries Alliance
µA
microampere
I/O
Input/Output
mA
milliampere
JEDEC
Joint Electron Devices Engineering Council
mm
millimeter
OE
Output Enable
ms
millisecond
SRAM
Static Random Access Memory
mV
millivolt
TQFP
Thin Quad Flat Pack
ns
nanosecond
TTL
Transistor-Transistor Logic
WE
Write Enable
Document Number: 001-86114 Rev. *D
Symbol
Unit of Measure
ohm
%
percent
pF
picofarad
V
volt
W
watt
Page 19 of 21
CY7C1325H
Document History Page
Document Title: CY7C1325H, 4-Mbit (256K × 18) Flow-Through Sync SRAM
Document Number: 001-86114
Rev.
ECN No.
Orig. of
Change
Submission
Date
**
3908939
PRIT
02/20/2013
New data sheet.
*A
4291116
PRIT
02/25/2014
Updated Package Diagrams:
spec 51-85050 – Changed revision from *D to *E.
Updated to new template.
Completing Sunset Review.
*B
4571750
PRIT
11/18/2014
Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
*C
5097432
PRIT
01/21/2016
Updated to new template.
Completing Sunset Review.
*D
5321039
PRIT
06/23/2016
Updated Truth Table.
Updated to new template.
Document Number: 001-86114 Rev. *D
Description of Change
Page 20 of 21
CY7C1325H
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC®Solutions
Products
ARM® Cortex® Microcontrollers
Automotive
cypress.com/arm
cypress.com/automotive
Clocks & Buffers
Interface
Lighting & Power Control
Memory
cypress.com/clocks
cypress.com/interface
cypress.com/powerpsoc
cypress.com/memory
PSoC
Cypress Developer Community
Forums | Projects | Video | Blogs | Training | Components
Technical Support
cypress.com/support
cypress.com/psoc
Touch Sensing
cypress.com/touch
USB Controllers
Wireless/RF
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2013-2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United
States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 001-86114 Rev. *D
Revised June 23, 2016
Page 21 of 21
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