327
CY7C1327B
256K x 18 Synchronous-Pipelined Cache RAM
Features
The CY7C1327B I/O pins can operate at either the 2.5V or the
3.3V level. The I/O pins are 3.3V tolerant when VDDQ=2.5V.
• Supports 100-MHz bus for Pentium and PowerPC™
operations with zero wait states
• Fully registered inputs and outputs for pipelined
operation
• 256K by 18 common I/O architecture
• 3.3V core power supply
• 2.5V / 3.3V I/O operation
• Fast clock-to-output times
— 3.5 ns (for 166-MHz device)
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise is 3.5 ns (166-MHz
device).
The CY7C1327B supports either the interleaved burst sequence used by the Intel Pentium processor or a linear burst
sequence used by processors such as the PowerPC. The
burst sequence is selected through the MODE pin. Accesses
can be initiated by asserting either the Processor Address
Strobe (ADSP) or the Controller Address Strobe (ADSC) at
clock rise. Address advancement through the burst sequence
is controlled by the ADV input. A 2-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.
— 4.0 ns (for 133-MHz device)
•
•
•
•
•
•
— 5.5 ns (for 100-MHz device)
User-selectable burst counter supporting Intel
Pentium interleaved or linear burst sequences
Separate processor and controller address strobes
Synchronous self-timed writes
Asynchronous Output Enable
JEDEC-standard 100 TQFP pinout
“ZZ” Sleep Mode option and Stop Clock option
Byte write operations are qualified with the four Byte Write
Select (BW[1:0]) inputs. A Global Write Enable (GW) overrides
all byte write inputs and writes data to all four bytes. All writes
are conducted with on-chip synchronous self-timed write circuitry.
Functional Description
Three synchronous Chip Selects (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank selection and output three-state control. In order to provide proper data during depth expansion, OE is masked during the first
clock of a read cycle when emerging from a deselected state.
The CY7C1327B is a 3.3V, 256K by 18 synchronous-pipelined
cache SRAM designed to support zero wait state secondary
cache with minimal glue logic.
Logic Block Diagram
MODE
(A[1;0]) 2
BURST Q0
CE COUNTER
Q1
CLR
CLK
ADV
ADSC
ADSP
A[17:0]
GW
Q
18
16
ADDRESS
CE REGISTER
D
18
16
256KX18
MEMORY
ARRAY
D DQ[15:8], DP[1] Q
BYTEWRITE
REGISTERS
D DQ[7:0], DP[0] Q
BYTEWRITE
REGISTERS
BWE
BW 1
BW0
18
CE1
CE2
CE3
D
ENABLE CE
CE REGISTER
18
Q
D ENABLE DELAY Q
REGISTER
OUTPUT
REGISTERS
CLK
INPUT
REGISTERS
CLK
OE
ZZ
SLEEP
CONTROL
DQ[15:0]
DP[1:0]
Intel and Pentium are registered trademarks of Intel Corporation.
PowerPC is a trademark of IBM Corporation.
Cypress Semiconductor Corporation
Document #: 38-05140 Rev. **
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised September 6, 2001
CY7C1327B
Selection Guide
7C1327-166
Maximum Access Time (ns)
7C1327-133
7C1327-100
3.5
4.0
5.5
Maximum Operating Current (mA)
Commercial
420
375
325
Maximum CMOS Standby Current (mA)
Commercial
10
10
10
Pin Configurations
A8
A9
81
82
ADSP
ADV
83
84
BWE
GW
CLK
VSS
VDD
CE3
BWS0
OE
ADSC
85
86
87
88
89
90
91
92
93
NC
NC
CE2
BWS1
94
95
96
97
A7
CE1
98
NC
1
80
NC
2
79
A10
NC
NC
3
78
NC
VDDQ
VSS
NC
4
77
VDDQ
5
76
6
75
VSS
NC
7
74
DP0
8
73
DQ7
DQ9
9
72
DQ6
VSS
10
71
VSS
VDDQ
11
70
VDDQ
DQ10
12
69
DQ5
DQ11
13
68
DQ4
NC
14
67
VDD
NC
15
66
VSS
NC
16
65
VSS
17
64
VDD
ZZ
DQ12
18
63
DQ3
DQ13
19
62
DQ2
VDDQ
20
61
VDDQ
VSS
21
60
VSS
DQ14
22
59
DQ1
DQ15
23
58
DP1
NC
24
57
DQ0
NC
25
56
NC
VSS
26
55
VSS
VDDQ
NC
27
54
28
53
VDDQ
NC
NC
29
52
NC
NC
30
51
NC
Document #: 38-05140 Rev. **
35
36
37
38
39
40
41
42
45
46
47
48
49
50
A2
A1
A0
DNU
DNU
VSS
VDD
DNU
DNU
A11
A12
A13
A14
A15
A16
A17
44
34
A3
43
33
A4
CY7C1327B
32
31
NC
DQ8
MODE
A5
BYTE1
99
100
A6
100-Lead TQFP
BYTE0
Page 2 of 17
CY7C1327B
Pin Configurations (continued)
119-Ball BGA
1
2
3
4
5
6
7
A
VDDQ
A
A
ADSP
A
A
VDDQ
B
C
NC
NC
CE2
A
A
A
ADSC
VDD
A
A
CE3
A
NC
NC
D
DQb
NC
VSS
NC
VSS
DQPa
NC
E
F
NC
VDDQ
DQb
NC
VSS
VSS
CE1
OE
VSS
VSS
NC
DQa
DQa
VDDQ
G
H
J
NC
DQb
VDDQ
DQb
NC
VDD
BWb
VSS
NC
ADV
GW
VDD
Vss
VSS
NC
NC
DQa
VDD
DQa
NC
VDDQ
K
NC
DQb
VSS
CLK
VSS
NC
DQa
L
DQb
NC
Vss
NC
BWa
DQa
NC
M
N
VDDQ
DQb
DQb
NC
VSS
VSS
BWE
A1
VSS
VSS
NC
DQa
VDDQ
NC
P
NC
DQPb
VSS
A0
VSS
NC
DQa
R
T
NC
A
MODE
VDD
VSS
A
NC
NC
A
A
NC
A
A
ZZ
U
VDDQ
NC
NC
NC
NC
NC
VDDQ
Pin Definitions
Name
A[17:0]
BW[1:0]
GW
BWE
CLK
CE1
CE2
CE3
OE
ADV
ADSP
I/O
InputSynchronous
Description
Address Inputs used to select one of the 64K address locations. Sampled at the rising edge of the
CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A[1:0] feed the
2-bit counter.
InputByte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM.
Synchronous Sampled on the rising edge of CLK.
InputGlobal Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global
Synchronous write is conducted (ALL bytes are written, regardless of the values on BW[1:0] and BWE).
InputByte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be
Synchronous asserted LOW to conduct a byte write.
Input-Clock
Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst
counter when ADV is asserted LOW, during a burst operation.
InputChip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2
Synchronous and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH.
InputChip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1
Synchronous and CE3 to select/deselect the device.
InputChip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1
Synchronous and CE2 to select/deselect the device.
InputOutput Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When LOW,
Asynchronous the I/O pins behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input
data pins. OE is masked during the first clock of a read cycle when emerging from a deselected state.
InputAdvance Input Signal, sampled on the rising edge of CLK. When asserted, it automatically increSynchronous ments the address in a burst cycle.
InputAddress Strobe from Processor, sampled on the rising edge of CLK. When asserted LOW, A[17:0]
Synchronous is captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and
ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH.
Document #: 38-05140 Rev. **
Page 3 of 17
CY7C1327B
Pin Definitions (continued)
Name
ADSC
ZZ
DQ[15:0]
DP[1:0]
VDD
VSS
VDDQ
VSSQ
MODE
NC
I/O
InputSynchronous
Description
Address Strobe from Controller, sampled on the rising edge of CLK. When asserted LOW, A[17:0] is
captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and
ADSC are both asserted, only ADSP is recognized.
InputZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition
Asynchronous with data integrity preserved. Leaving ZZ floating or NC will default the device into an active state.
ZZ pin has an internal pull-down.
I/OBidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the
Synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by
A[17:0] during the previous clock rise of the read cycle. The direction of the pins is controlled by OE.
When OE is asserted LOW, the pins behave as outputs. When HIGH, DQ[15:0] and DP[1:0] are placed
in a three-state condition.
Power Supply Power Supply inputs to the core of the device. Should be connected to 3.3V power supply.
Ground
Ground for the core of the device. Should be connected to ground of the system.
I/O Power
Power Supply for the I/O circuitry. Should be connected to a 3.3V or 2.5V power supply.
Supply
I/O Ground
Ground for the I/O circuitry. Should be connected to ground of the system.
InputSelects Burst Order. When tied to GND selects linear burst sequence. When tied to VDDQ or left
Static
floating selects interleaved burst sequence. This is a strap pin and should remain static during device
operation. When left floating or NC, defaults to interleaved burst order. Mode pin has an internal
pull-up.
No Connects.
Introduction
Functional Overview
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (tCO) is 3.5 ns (166-MHz
device).
The CY7C1327B supports secondary cache in systems utilizing either a linear or interleaved burst sequence. The interleaved burst order supports Pentium and i486 processors. The
linear burst sequence is suited for processors that utilize a
linear burst sequence. The burst order is user selectable, and
is determined by sampling the MODE input. Accesses can be
initiated with either the Processor Address Strobe (ADSP) or
the Controller Address Strobe (ADSC). Address advancement
through the burst sequence is controlled by the ADV input. A
two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the
address for the rest of the burst access.
Byte write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BW[1:0]) inputs. A Global Write
Enable (GW) overrides all byte write inputs and writes data to
all four bytes. All writes are simplified with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Selects (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank selection and output three-state control. ADSP is ignored if CE1
is HIGH.
Single Read Accesses
This access is initiated when the following conditions are satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
CE1, CE2, CE3 are all asserted active, and (3) the write signals
(GW, BWE) are all deasserted HIGH. ADSP is ignored if CE1
Document #: 38-05140 Rev. **
is HIGH. The address presented to the address inputs (A[17:0])
is stored into the address advancement logic and the Address
Register while being presented to the memory core. The corresponding data is allowed to propagate to the input of the
Output Registers. At the rising edge of the next clock the data
is allowed to propagate through the output register and onto
the data bus within 3.5 ns (166-MHz device) if OE is active
LOW. The only exception occurs when the SRAM is emerging
from a deselected state to a selected state, its outputs are
always three-stated during the first cycle of the access. After
the first cycle of the access, the outputs are controlled by the
OE signal. Consecutive single read cycles are supported.
Once the SRAM is deselected at clock rise by the chip select
and either ADSP or ADSC signals, its output will three-state
immediately.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions
are satisfied at clock rise: (1) ADSP is asserted LOW, and (2)
CE1, CE2, CE3 are all asserted active. The address presented
to A[17:0] is loaded into the address register and the address
advancement logic while being delivered to the RAM core. The
write signals (GW, BWE, and BW[1:0]) and ADV inputs are ignored during this first cycle.
ADSP-triggered write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQ[15:0] and DP[1:0] inputs is written into
the corresponding address location in the RAM core. If GW is
HIGH, then the write operation is controlled by BWE and
BW[1:0] signals. The CY7C1327B provides byte write capability that is described in the Write Cycle Description table. Asserting the Byte Write Enable input (BWE) with the selected
Byte Write (BW[1:0]) input will selectively write to only the desired bytes. Bytes not selected during a byte write operation
will remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations.
Page 4 of 17
CY7C1327B
Because the CY7C1327B is a common I/O device, the Output
Enable (OE) must be deasserted HIGH before presenting data
to the DQ[15:0] and DP[1:0] inputs. Doing so will three-state the
output drivers. As a safety precaution, DQ[15:0] and DP[1:0] are
automatically three-stated whenever a write cycle is detected,
regardless of the state of OE.
ear burst sequence. The burst sequence is user selectable
through the MODE input.
Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both read and write burst operations are supported.
Interleaved Burst Sequence
Single Write Accesses Initiated by ADSC
ADSC write accesses are initiated when the following conditions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
deasserted HIGH, (3) CE1, CE2, CE3 are all asserted active,
and (4) the appropriate combination of the write inputs (GW,
BWE, and BW[1:0]) are asserted active to conduct a write to
the desired byte(s). ADSC-triggered write accesses require a
single clock cycle to complete. The address presented to
A[17:0] is loaded into the address register and the address advancement logic while being delivered to the RAM core. The
ADV input is ignored during this cycle. If a global write is conducted, the data presented to the DQ[15:0] and DP[1:0] is written
into the corresponding address location in the RAM core. If a
byte write is conducted, only the selected bytes are written.
Bytes not selected during a byte write operation will remain
unaltered. A synchronous self-timed write mechanism has
been provided to simplify the write operations.
Because the CY7C1327B is a common I/O device, the Output
Enable (OE) must be deasserted HIGH before presenting data
to the DQ[15:0] and DP[1:0] inputs. Doing so will three-state the
output drivers. As a safety precaution, DQ[15:0] and DP[1:0] are
automatically three-stated whenever a write cycle is detected,
regardless of the state of OE.
Burst Sequences
The CY7C1327B provides a two-bit wraparound counter, fed
by A[1:0], that implements either an interleaved or linear burst
sequence. The interleaved burst sequence is designed specifically to support Intel Pentium applications. The linear burst
sequence is designed to support processors that follow a lin-
First
Address
A[1:0]
00
01
10
11
Second
Address
Third
Address
A[1:0]
01
00
11
10
A[1:0]
10
11
00
01
Fourth
Address
A[1:0]
11
10
01
00
Linear Burst Sequence
First
Address
Second
Address
Third
Address
Fourth
Address
A[1:0]
A[1:0]
A[1:0]
A[1:0]
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered
valid nor is the completion of the operation guaranteed. The
device must be deselected prior to entering the “sleep” mode.
CE1, CE2, CE3, ADSP, and ADSC must remain inactive for the
duration of tZZREC after the ZZ input returns LOW.
ZZ Mode Electrical Characteristics
Parameter
IDDZZ
tZZS
tZZREC
Description
Test Conditions
Max.
Unit
Snooze mode
standby current
ZZ > VDD − 0.2V
3
mA
Device operation to
ZZ
ZZ > VDD − 0.2V
2tCYC
ns
ZZ recovery time
ZZ < 0.2V
Document #: 38-05140 Rev. **
Min.
2tCYC
ns
Page 5 of 17
CY7C1327B
Cycle Descriptions[1, 2, 3]
Next Cycle
Add. Used
ZZ
CE3
CE2
CE1
ADSP
ADSC
ADV
OE
DQ
Write
Unselected
None
L
X
X
1
X
0
X
X
Hi-Z
X
Unselected
None
L
1
X
0
0
X
X
X
Hi-Z
X
Unselected
None
L
X
0
0
0
X
X
X
Hi-Z
X
Unselected
None
L
1
X
0
1
0
X
X
Hi-Z
X
Unselected
None
L
X
0
0
1
0
X
X
Hi-Z
X
Begin Read
External
L
0
1
0
0
X
X
X
Hi-Z
X
Begin Read
External
L
0
1
0
1
0
X
X
Hi-Z
Read
Continue Read
Next
L
X
X
X
1
1
0
1
Hi-Z
Read
Continue Read
Next
L
X
X
X
1
1
0
0
DQ
Read
Continue Read
Next
L
X
X
1
X
1
0
1
Hi-Z
Read
Continue Read
Next
L
X
X
1
X
1
0
0
DQ
Read
Suspend Read
Current
L
X
X
X
1
1
1
1
Hi-Z
Read
Suspend Read
Current
L
X
X
X
1
1
1
0
DQ
Read
Suspend Read
Current
L
X
X
1
X
1
1
1
Hi-Z
Read
Suspend Read
Current
L
X
X
1
X
1
1
0
DQ
Read
Begin Write
Current
L
X
X
X
1
1
1
X
Hi-Z
Write
Begin Write
Current
L
X
X
1
X
1
1
X
Hi-Z
Write
Begin Write
External
L
0
1
0
1
0
X
X
Hi-Z
Write
Continue Write
Next
L
X
X
X
1
1
0
X
Hi-Z
Write
Continue Write
Next
L
X
X
1
X
1
0
X
Hi-Z
Write
Suspend Write
Current
L
X
X
X
1
1
1
X
Hi-Z
Write
Suspend Write
Current
L
X
X
1
X
1
1
X
Hi-Z
Write
ZZ “Sleep”
None
H
X
X
X
X
X
X
X
Hi-Z
X
Notes:
1. X = “Don't Care,” 1 = HIGH, 0 = LOW.
2. Write is defined by BWE, BW[1:0], and GW. See Write Cycle Description table.
3. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
Document #: 38-05140 Rev. **
Page 6 of 17
CY7C1327B
Write Cycle Description[4, 5, 6]
Function
GW
BWE
BW3
BW2
BW1
BW0
Read
1
1
X
X
X
X
Read
1
0
1
1
1
1
Write Byte 0 - DQ[7:0]
1
0
1
1
1
0
Write Byte 1 - DQ[15:8]
1
0
1
1
0
1
Write Bytes 1, 0
1
0
1
1
0
0
Write Byte 2 - DQ[23:16]
1
0
1
0
1
1
Write Bytes 2, 0
1
0
1
0
1
0
Write Bytes 2, 1
1
0
1
0
0
1
Write Bytes 2, 1, 0
1
0
1
0
0
0
Write Byte 3 - DQ[31:24]
1
0
0
1
1
1
Write Bytes 3, 0
1
0
0
1
1
0
Write Bytes 3, 1
1
0
0
1
0
1
Write Bytes 3, 1, 0
1
0
0
1
0
0
Write Bytes 3, 2
1
0
0
0
1
1
Write Bytes 3, 2, 0
1
0
0
0
1
0
Write Bytes 3, 2, 1
1
0
0
0
0
1
Write All Bytes
1
0
0
0
0
0
Write All Bytes
0
X
X
X
X
X
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.)
Current into Outputs (LOW) ........................................ 20 mA
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
Storage Temperature ..................................... −65°C to +150°C
Latch-Up Current.................................................... >200 mA
Ambient Temperature with
Power Applied.................................................. −55°C to +125°C
Operating Range
Supply Voltage on VDD Relative to GND.........−0.5V to +4.6V
Range
DC Voltage Applied to Outputs
in High Z State[7] ....................................... −0.5V to VDD + 0.5V
Com’l
DC Input Voltage[7] .................................... −0.5V to VDD + 0.5V
Industrial
Ambient
Temperature[8]
0°C to +70°C
–40°C to +85°C
VDD
VDDQ
3.3V
−5%/+10%
2.5V −5%
3.3V +10%
Notes:
4. X = “Don't Care,” 1 = Logic HIGH, 0 = Logic LOW.
5. The SRAM always initiates a read cycle when ADSP asserted, regardless of the state of GW, BWE, or BW[1:0]. Writes may occur only on subsequent clocks
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state. OE is
a don't care for the remainder of the write cycle.
6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQ[15:0];DP[1:0] = High-Z when OE is
inactive or when the device is deselected, and DQ[15:0];DP[1:0] = data when OE is active.
7. Minimum voltage equals −2.0V for pulse durations of less than 20 ns.
8. TA is the case temperature.
Document #: 38-05140 Rev. **
Page 7 of 17
CY7C1327B
Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
Min.
Max.
Unit
VDD
Power Supply Voltage
3.3V −5%/+10%
3.135
3.6
V
VDDQ
I/O Supply Voltage
2.5V −5% to 3.3V +10%
2.375
3.6
V
VOH
Output HIGH Voltage
VDDQ = 3.3V, VDD = Min., IOH = –4.0 mA
2.4
V
VDDQ = 2.5V, VDD = Min., IOH = –2.0 mA
2.0
V
VOL
Output LOW Voltage
VDDQ = 3.3V, VDD = Min., IOL = 8.0 mA
0.4
V
VDDQ = 2.5V, VDD = Min., IOL = 2.0 mA
0.7
V
VIH
Input HIGH Voltage
VDDQ = 3.3V
2.0
VDD + 0.3V
V
VIH
Input HIGH Voltage
VDDQ = 2.5V
1.7
VDD + 0.3V
V
VIL
[7]
Input LOW Voltage
VDDQ = 3.3V
–0.3
0.8
V
VIL
Input LOW Voltage[7]
VDDQ = 2.5V
–0.3
0.7
V
IX
Input Load Current
except ZZ and MODE
GND ≤ VI ≤ VDDQ
−5
5
µA
−30
Input Current of MODE Input = VSS
Input = VDDQ
Input Current of ZZ
−5
Input = VSS
Input = VDDQ
Output Leakage
Current
GND ≤ VI ≤ VDDQ, Output Disabled
IDD
VDD Operating Supply
Current
VDD = Max., IOUT = 0 mA,
f = fMAX = 1/tCYC
Automatic CS
Power-Down
Current—TTL Inputs
Max. VDD, Device Deselected,
VIN ≥ VIH or VIN ≤ VIL
f = fMAX = 1/tCYC
ISB2
Automatic CS
Max. VDD, Device Deselected,
Power-Down
VIN ≤ 0.3V or VIN > VDDQ – 0.3V,
Current—CMOS Inputs f = 0
ISB3
Automatic CS
Max. VDD, Device Deselected, or
Power-Down
VIN ≤ 0.3V or VIN > VDDQ – 0.3V
Current—CMOS Inputs f = fMAX = 1/tCYC
ISB4
Automatic CS
Power-Down
Current—TTL Inputs
µA
5
IOZ
ISB1
µA
−5
µA
30
µA
5
µA
6-ns cycle, 166 MHz
420
mA
7.5-ns cycle, 133 MHz
375
mA
10-ns cycle, 100 MHz
325
mA
6-ns cycle, 166 MHz
150
mA
7.5-ns cycle, 133 MHz
125
mA
10-ns cycle, 100 MHz
115
mA
10
mA
6-ns cycle, 166 MHz
120
mA
7.5-ns cycle, 133 MHz
95
mA
10-ns cycle, 100 MHz
85
mA
18
mA
Max. VDD, Device Deselected,
VIN ≥ VIH or VIN ≤ VIL, f = 0
Capacitance[9]
Parameter
Description
CIN
Input Capacitance
CCLK
Clock Input Capacitance
CI/O
Input/Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VDD = 3.3V,
VDDQ = 3.3V
Max.
Unit
4
pF
4
pF
4
pF
Note:
9. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05140 Rev. **
Page 8 of 17
CY7C1327B
AC Test Loads and Waveforms
R=317Ω
3.3V
OUTPUT
ALL INPUT PULSES
OUTPUT
Z0 =50Ω
RL =50Ω
2.5V
5 pF
VL = 1.5V
R=351Ω
INCLUDING
JIG AND
SCOPE
(a)
90%
10%
90%
10%
[10]
GND
≤ 2.5 ns
≤ 2.5 ns
(c)
(b)
Switching Characteristics Over the Operating Range[11, 12, 13]
-166
Parameter
Description
Min.
-133
Max.
Min.
-100
Max.
Min.
Max.
Unit
tCYC
Clock Cycle Time
6.0
7.5
10
ns
tCH
Clock HIGH
1.7
1.9
3.5
ns
tCL
Clock LOW
1.7
1.9
3.5
ns
tAS
Address Set-Up Before CLK Rise
2.0
2.5
2.5
ns
tAH
Address Hold After CLK Rise
0.5
0.5
0.5
ns
tCO
Data Output Valid After CLK Rise
tDOH
Data Output Hold After CLK Rise
1.5
2.0
2.0
ns
tADS
ADSP, ADSC Set-Up Before CLK Rise
2.0
2.5
2.5
ns
tADH
ADSP, ADSC Hold After CLK Rise
0.5
0.5
0.5
ns
tWES
BWE, GW, BW[1:0] Set-Up Before CLK
Rise
2.0
2.5
2.5
ns
tWEH
BWE, GW, BW[1:0] Hold After CLK Rise
0.5
0.5
0.5
ns
tADVS
ADV Set-Up Before CLK Rise
2.0
2.5
2.5
ns
tADVH
ADV Hold After CLK Rise
0.5
0.5
0.5
ns
tDS
Data Input Set-Up Before CLK Rise
2.0
2.5
2.5
ns
tDH
Data Input Hold After CLK Rise
0.5
0.5
0.5
ns
tCES
Chip Select Set-Up
2.0
2.5
2.5
ns
tCEH
Chip Select Hold After CLK Rise
0.5
0.5
0.5
ns
[12]
tCHZ
Clock to High-Z
tCLZ
Clock to Low-Z[12]
tEOHZ
tEOLZ
tEOV
3.5
3.5
0
OE HIGH to Output High-Z
OE LOW to Output Low-Z
OE LOW to Output Valid
4.0
[12, 13]
[12, 13]
[12]
3.5
0
3.5
0
3.5
0
3.5
0
3.5
5.5
ns
ns
5.5
0
4.0
ns
ns
ns
5.5
ns
Notes:
10. Input waveform should have a slew rate of 1 V/ns.
11. Unless otherwise noted, test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output
loading of the specified IOL/IOH and load capacitance. Shown in (a) and (b) of AC Test Loads.
12. tCHZ, tCLZ, tEOV, tEOLZ, and tEOHZ are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 200 mV from
steady-state voltage.
13. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ.
Document #: 38-05140 Rev. **
Page 9 of 17
CY7C1327B
Switching Waveforms
Write Cycle Timing[14, 15]
Single Write
Burst Write
Pipelined Write
tCH
Unselected
tCYC
CLK
tADH
tADS
tCL
ADSP ignored with CE1 inactive
ADSP
tADH
tADS
ADSC initiated write
ADSC
tADVH
tADVS
ADV
tAS
ADD
ADV Must Be Inactive for ADSP Write
WD1
WD3
WD2
tAH
GW
tWS
tWH
WE
tCES
tWH
tWS
tCEH
CE1 masks ADSP
CE1
tCES
tCEH
Unselected with CE2
CE2
CE3
tCES
tCEH
OE
tDH
tDS
Data
In
High-Z
1a
1a
2a
= UNDEFINED
2b
2c
2d
3a
High-Z
= DON’T CARE
Notes:
14. WE is the combination of BWE, BW[1:0], and GW to define a write cycle (see Write Cycle Description table).
15. WDx stands for Write Data to Address X.
Document #: 38-05140 Rev. **
Page 10 of 17
CY7C1327B
Switching Waveforms (continued)
Read Cycle Timing[14, 16]
Single Read
tCYC
Burst Read
Unselected
tCH
Pipelined Read
CLK
tADH
tADS
tCL
ADSP ignored with CE1 inactive
ADSP
tADS
ADSC initiated read
ADSC
tADVS
tADH
Suspend Burst
ADV
tADVH
tAS
ADD
RD1
RD3
RD2
tAH
GW
tWS
tWS
tWH
WE
tCES
tCEH
tWH
CE1 masks ADSP
CE1
Unselected with CE2
CE2
tCES
tCEH
CE3
tCES
OE
tCEH
tEOV
tOEHZ
tDOH
Data Out
tCO
1a
1a
2a
2b
2c 2c
2d
3a
tCLZ
= DON’T CARE
tCHZ
= UNDEFINED
Note:
16. RDx stands for Read Data from Address X.
Document #: 38-05140 Rev. **
Page 11 of 17
CY7C1327B
Switching Waveforms (continued)
Read/Write Cycle Timing[14, 15, 16, 17]
Single Read
tCYC
Single Write
Unselected
Burst Read
tCH
Pipelined Read
CLK
tADH
tADS
tCL
ADSP ignored with CE1 inactive
ADSP
tADS
ADSC
tADVS
tADH
ADV
tAS
ADD
tADVH
RD1
WD2
RD3
tAH
GW
tWS
tWS
tWH
WE
tCES
tCEH
tWH
CE1 masks ADSP
CE1
CE2
tCES
tCEH
CE3
tCES
tCEH
tEOV
OE
tEOHZ
See Note 17
Data In/Out
tEOLZ
tCO
1a
1a
Out
tDS
tDH
2a
In
2a
Out
= DON’T CARE
= UNDEFINED
3a
Out
tDOH
3b
Out
3c
Out
3d
Out
tCHZ
Note:
17. Data bus is driven by SRAM, but data is not guaranteed.
Document #: 38-05140 Rev. **
Page 12 of 17
CY7C1327B
Switching Waveforms (continued)
Pipeline Timing[18, 19]
tCH
tCYC
tCL
CLK
tAS
ADD
RD1
tADS
RD2
RD3
WD1
RD4
WD2
WD3
WD4
tADH
ADSC initiated Reads
ADSC
ADSP initiated Reads
ADSP
ADV
tCEH
tCES
CE1
CE
tWEH
tWES
WE
ADSP ignored
with CE1 HIGH
OE
tCLZ
Data In/Out
1a
Out
2a
Out
3a
Out
4a
Out
1a
In
2a
In
3a
In
4a
D(C)
In
tCO
Back to Back Reads
= DON’T CARE
tDOH
tCHZ
= UNDEFINED
Notes:
18. Device originally deselected.
19. CE is the combination of CE2 and CE3. All chip selects need to be active in order to select the device.
Document #: 38-05140 Rev. **
Page 13 of 17
CY7C1327B
Switching Waveforms (continued)
ZZ Mode Timing[20, 21]
CLK
ADSP
HIGH
ADSC
CE1
CE2
LOW
HIGH
CE3
ZZ
IDD
tZZS
IDD(active)
IDDZZ
tZZREC
I/Os
Three-state
Notes:
20. Device must be deselected when entering “ZZ” mode. See Cycle Description table for all possible signal conditions to deselect the device.
21. I/Os are in three-state when exiting “ZZ” sleep mode.
Document #: 38-05140 Rev. **
Page 14 of 17
CY7C1327B
Ordering Information
Speed
(MHz)
166
Ordering Code
CY7C1327B-166AC
CY7C1327B-166BGC
133
CY7C1327B-133AC
CY7C1327B-133BGC
CY7C1327B-133AI
100
Package
Name
A101
BG119
A101
BG119
A101
CY7C1327B-133BGI
BG119
CY7C1327B-100AC
A101
CY7C1327B-100BGC
CY7C1327B-100AI
CY7C1327B-100BGI
BG119
A101
BG119
Package Type
Operating
Range
100-Lead Thin Quad Flat Pack
Commercial
119-Ball BGA
100-Lead Thin Quad Flat Pack
Commercial
119-Ball BGA
100-Lead Thin Quad Flat Pack
Industrial
119-Ball BGA
100-Lead Thin Quad Flat Pack
Commercial
119-Ball BGA
100-Lead Thin Quad Flat Pack
Industrial
119-Ball BGA
Package Diagrams
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
51-85050-A
Document #: 38-05140 Rev. **
Page 15 of 17
CY7C1327B
Package Diagrams (continued)
119-Lead FBGA (14 x 22 x 2.4 mm) BG119
51-85115
Document #: 38-05140 Rev. **
Page 16 of 17
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1327B
Document Title: CY7C1327B 256K x 18 Synchronous-Pipelined Cache RAM
Document Number: 38-05140
REV.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
109884
09/10/01
SZV
Change from Spec number: 38-00935 to 38-05140
Document #: 38-05140 Rev. **
Page 17 of 17
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