CY7C1327G
4-Mbit (256K × 18) Pipelined Sync SRAM
4-Mbit (256K × 18) Pipelined Sync SRAM
Features
Functional Description
■
Registered inputs and outputs for pipelined operation
The CY7C1327G SRAM integrates 256K × 18 SRAM cells with
advanced synchronous peripheral circuitry and a two-bit counter
for internal burst operation. All synchronous inputs are gated by
registers controlled by a positive-edge-triggered clock input
(CLK). The synchronous inputs include all addresses, all data
inputs, address-pipelining chip enable (CE1), depth-expansion
chip enables (CE2 and CE3), burst control inputs (ADSC, ADSP,
and ADV), write enables (BW[A:B], and BWE), and global write
(GW). Asynchronous inputs include the output enable (OE) and
the ZZ pin.
■
256K × 18 common I/O Architecture
■
3.3 V core power supply (VDD)
■
2.5 V I/O power supply (VDDQ)
■
Fast clock-to-output times
❐ 3.5 ns (for 166-MHz device)
■
Provide high performance 3-1-1-1 access rate
■
User-selectable burst counter supporting Intel Pentium
interleaved or linear burst sequences
■
Separate processor and controller address strobes
■
Synchronous self-timed writes
■
Asynchronous output enable
■
Offered in Pb-free 100-pin TQFP package
■
“ZZ” sleep mode option
Addresses and chip enables are registered at rising edge of
clock when either address strobe processor (ADSP) or address
strobe controller (ADSC) are active. Subsequent burst
addresses can be internally generated as controlled by the
advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed Write cycle.This part supports byte write
operations (see Pin Descriptions and Truth Table for further
details). Write cycles can be one to two bytes wide as controlled
by the byte write control inputs. GW when active LOW causes all
bytes to be written.
The CY7C1327G operates from a +3.3 V core power supply
while all outputs also operate with a +3.3 V or a +2.5 V supply.
All inputs and outputs are JEDEC-standard JESD8-5compatible.
For a complete list of related documentation, click here.
Logic Block
A0, A1, A
ADDRESS
REGISTER
A[1:0]
2
MODE
BURST Q1
COUNTER AND
LOGIC
CLR
Q0
ADV
CLK
ADSC
ADSP
BW B
DQ B, DQP B
WRITE DRIVER
DQ B, DQP B
WRITE REGISTER
SENSE
AMPS
MEMORY
ARRAY
BW A
DQ A, DQP A
WRITE DRIVER
DQ A, DQP A
WRITE REGISTER
OUTPUT
REGISTERS
OUTPUT
BUFFERS
DQs
DQP A
DQP B
E
BWE
GW
CE 1
CE2
CE3
ENABLE
REGISTER
INPUT
REGISTERS
PIPELINED
ENABLE
OE
ZZ
SLEEP
CONTROL
Errata: For information on silicon errata, see "Errata" on page 21. Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation
Document Number: 38-05519 Rev. *Q
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised November 4, 2016
CY7C1327G
Contents
Selection Guide ................................................................ 3
Pin Configurations ........................................................... 3
Pin Definitions .................................................................. 4
Functional Overview ........................................................ 6
Single Read Accesses ................................................ 6
Single Write Accesses Initiated by ADSP ................... 6
Single Write Accesses Initiated by ADSC ................... 6
Burst Sequences ......................................................... 6
Sleep Mode ................................................................. 6
Interleaved Burst Address Table ................................. 7
Linear Burst Address Table ......................................... 7
ZZ Mode Electrical Characteristics .............................. 7
Truth Table ........................................................................ 8
Truth Table for Read/Write .............................................. 9
Maximum Ratings ........................................................... 10
Operating Range ............................................................. 10
Neutron Soft Error Immunity ......................................... 10
Electrical Characteristics ............................................... 10
Capacitance .................................................................... 11
Thermal Resistance ........................................................ 11
Document Number: 38-05519 Rev. *Q
AC Test Loads and Waveforms ..................................... 12
Switching Characteristics .............................................. 13
Switching Waveforms .................................................... 14
Ordering Information ...................................................... 18
Ordering Code Definitions ......................................... 18
Package Diagrams .......................................................... 19
Acronyms ........................................................................ 20
Document Conventions ................................................. 20
Units of Measure ....................................................... 20
Errata ............................................................................... 21
Part Numbers Affected .............................................. 21
Product Status ........................................................... 21
Ram9 Sync ZZ Pin Issues Errata Summary .............. 21
Document History Page ................................................. 22
Sales, Solutions, and Legal Information ...................... 24
Worldwide Sales and Design Support ....................... 24
Products .................................................................... 24
PSoC®Solutions ....................................................... 24
Cypress Developer Community ................................. 24
Technical Support ..................................................... 24
Page 2 of 24
CY7C1327G
Selection Guide
Description
166 MHz
133 MHz
Unit
Maximum access time
3.5
4.0
ns
Maximum operating current
240
225
mA
Maximum CMOS standby current
40
40
mA
Pin Configurations
NC
NC
NC
BYTE B
VDDQ
VSS
NC
NC
DQB
DQB
VSS
VDDQ
DQB
DQB
NC
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1327G
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
VDDQ
VSS
NC
DQPA
DQA
DQA
VSS
VDDQ
DQA
DQA
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSS
DQA
DQA
NC
NC
VSS
VDDQ
NC
NC
NC
BYTE A
MODE
A
A
A
A
A1
A0
NC/72M
NC/36M
VSS
VDD
NC/18M
NC/9M
A
A
A
A
A
A
A
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
NC
VSS
DQB
DQB
VDDQ
VSS
DQB
DQB
DQPB
NC
VSS
VDDQ
NC
NC
NC
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
CE1
CE2
NC
NC
BWB
BWA
CE3
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
Figure 1. 100-pin TQFP pinout [1]
Note
1. Errata: The ZZ pin (Pin 64) needs to be externally connected to ground. For more information, see "Errata" on page 21.
Document Number: 38-05519 Rev. *Q
Page 3 of 24
CY7C1327G
Pin Definitions
Name
I/O
Description
A0, A1, A
InputAddress inputs used to select one of the 256 K address locations. Sampled at the rising edge of
synchronous the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A1, A0 feed the
2-bit counter.
BWA, BWB
InputByte write select inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM. Sampled
synchronous on the rising edge of CLK.
GW
InputGlobal write enable input, active LOW. When asserted LOW on the rising edge of CLK, a global write
synchronous is conducted (all bytes are written, regardless of the values on BW[A:B] and BWE).
BWE
InputByte write enable input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted
synchronous LOW to conduct a byte write.
CLK
Inputclock
Clock input. Used to capture all synchronous inputs to the device. Also used to increment the burst
counter when ADV is asserted LOW, during a burst operation.
CE1
InputChip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2
synchronous and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only when a
new external address is loaded.
CE2
InputChip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1
synchronous and CE3 to select/deselect the device. CE2 is sampled only when a new external address is loaded.
CE3
InputChip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1
synchronous and CE2 to select/deselect the device. CE3 is sampled only when a new external address is loaded.
OE
InputOutput enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When LOW,
asynchronous the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tristated, and act as input data
pins. OE is masked during the first clock of a read cycle when emerging from a deselected state.
ADV
InputAdvance input signal, sampled on the rising edge of CLK, active LOW. When asserted, it
synchronous automatically increments the address in a burst cycle.
ADSP
InputAddress strobe from processor, sampled on the rising edge of CLK, active LOW. When asserted
synchronous LOW, A is captured in the address registers. A1:A0 are also loaded into the burst counter. When ADSP
and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH.
ZZ[2]
InputZZ “sleep” input, active HIGH. This input, when High places the device in a non-time-critical “sleep”
asynchronous condition with data integrity preserved. During normal operation, this pin has to be low or left floating. ZZ
pin has an internal pull-down.
Note
2. Errata: The ZZ pin (Pin 64) needs to be externally connected to ground. For more information, see "Errata" on page 21.
Document Number: 38-05519 Rev. *Q
Page 4 of 24
CY7C1327G
Pin Definitions (continued)
Name
I/O
Description
ADSC
InputAddress strobe from controller, sampled on the rising edge of CLK, active LOW. When asserted
synchronous LOW, A is captured in the address registers. A1:A0 are also loaded into the burst counter. When ADSP
and ADSC are both asserted, only ADSP is recognized.
DQA, DQB,
DQPA,
DQPB
I/OBidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the
synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by “A”
during the previous clock rise of the read cycle. The direction of the pins is controlled by OE. When OE
is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQP[A:B] are placed in a tristate
condition.
VDD
Power supply Power supply inputs to the core of the device.
VSS
Ground
Ground for the device.
VDDQ
I/O ground
MODE
Inputstatic
Selects burst order. When tied to GND selects linear burst sequence. When tied to VDD or left floating
selects interleaved burst sequence. This is a strap pin and should remain static during device operation.
Mode Pin has an internal pull-up.
–
No connects. Not internally connected to the die. NC/9M, NC/18M, NC/72M, NC/144M, NC/288M,
NC/576M and NC/1G are address expansion pins are not internally connected to the die.
NC,
NC/9M,
NC/18M,
NC/72M,
NC/144M,
NC/288M,
NC/576M,
NC/1G
Ground for the I/O circuitry.
Document Number: 38-05519 Rev. *Q
Page 5 of 24
CY7C1327G
Functional Overview
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock.
The CY7C1327G supports secondary cache in systems utilizing
either a linear or interleaved burst sequence. The interleaved
burst order supports Pentium and i486 processors. The linear
burst sequence is suited for processors that utilize a linear burst
sequence. The burst order is user selectable, and is determined
by sampling the MODE input. Accesses can be initiated with
either the processor address strobe (ADSP) or the controller
address strobe (ADSC). Address advancement through the
burst sequence is controlled by the ADV input. A two-bit on-chip
wraparound burst counter captures the first address in a burst
sequence and automatically increments the address for the rest
of the burst access.
Byte write operations are qualified with the byte write enable
(BWE) and byte write select (BW[A:B]) inputs. A global write
enable (GW) overrides all byte write inputs and writes data to all
four bytes. All writes are simplified with on-chip synchronous
self-timed write circuitry.
Three synchronous chip selects (CE1, CE2, CE3) and an
asynchronous output enable (OE) provide for easy bank
selection and output tristate control. ADSP is ignored if CE1 is
HIGH.
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
CE1, CE2, CE3 are all asserted active, and (3) the write signals
(GW, BWE) are all deserted HIGH. ADSP is ignored if CE1 is
HIGH. The address presented to the address inputs (A) is stored
into the address advancement logic and the address register
while being presented to the memory array. The corresponding
data is allowed to propagate to the input of the output registers.
At the rising edge of the next clock the data is allowed to
propagate through the output register and onto the data bus
within tCO if OE is active LOW. The only exception occurs when
the SRAM is emerging from a deselected state to a selected
state, its outputs are always tristated during the first cycle of the
access. After the first cycle of the access, the outputs are
controlled by the OE signal. Consecutive single read cycles are
supported. Once the SRAM is deselected at clock rise by the
chip select and either ADSP or ADSC signals, its output will
tristate immediately.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions are
satisfied at clock rise: (1) ADSP is asserted LOW, and (2) CE1,
CE2, CE3 are all asserted active. The address presented to A is
loaded into the address register and the address advancement
logic while being delivered to the memory array. The Write
signals (GW, BWE, and BW[A:B]) and ADV inputs are ignored
during this first cycle.
ADSP-triggered Write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQ inputs is written into the corresponding
address location in the memory array. If GW is HIGH, then the
Document Number: 38-05519 Rev. *Q
Write operation is controlled by BWE and BW[A:B] signals. The
CY7C1327G provides byte write capability that is described in
the Write Cycle Descriptions table. Asserting the byte write
enable input (BWE) with the selected byte write (BW[A:B]) input,
will selectively write to only the desired bytes. Bytes not selected
during a byte write operation will remain unaltered. A
synchronous self-timed Write mechanism has been provided to
simplify the write operations.
Because the CY7C1327G is a common I/O device, the output
enable (OE) must be deserted HIGH before presenting data to
the DQ inputs. Doing so will tristate the output drivers. As a safety
precaution, DQs are automatically tristated whenever a Write
cycle is detected, regardless of the state of OE.
Single Write Accesses Initiated by ADSC
ADSC write accesses are initiated when the following conditions
are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deserted
HIGH, (3) CE1, CE2, CE3 are all asserted active, and (4) the
appropriate combination of the write inputs (GW, BWE, and
BW[A:B]) are asserted active to conduct a write to the desired
byte(s). ADSC-triggered Write accesses require a single clock
cycle to complete. The address presented to A is loaded into the
address register and the address advancement logic while being
delivered to the memory array. The ADV input is ignored during
this cycle. If a global write is conducted, the data presented to
DQ is written into the corresponding address location in the
memory core. If a byte write is conducted, only the selected bytes
are written. Bytes not selected during a byte write operation will
remain unaltered. A synchronous self-timed write mechanism
has been provided to simplify the write operations.
Because the CY7C1327G is a common I/O device, the output
enable (OE) must be deserted HIGH before presenting data to
the DQ inputs. Doing so will tristate the output drivers. As a safety
precaution, DQs are automatically tristated whenever a Write
cycle is detected, regardless of the state of OE.
Burst Sequences
The CY7C1327G provides a two-bit wraparound counter, fed by
A1:A0, that implements either an interleaved or linear burst
sequence. The interleaved burst sequence is designed
specifically to support Intel Pentium applications. The linear
burst sequence is designed to support processors that follow a
linear burst sequence. The burst sequence is user selectable
through the MODE input.
Asserting ADV LOW at clock rise will automatically increment the
burst counter to the next address in the burst sequence. Both
Read and Write burst operations are supported.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected prior to entering the “sleep” mode. CE1, CE2,
CE3, ADSP, and ADSC must remain inactive for the duration of
tZZREC after the ZZ input returns LOW.
Page 6 of 24
CY7C1327G
Interleaved Burst Address Table
Linear Burst Address Table
(MODE = Floating or VDD)
(MODE = GND)
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
Fourth
Address
A1:A0
First
Address
A1:A0
Second
Address
A1:A0
Third
Address
A1:A0
00
01
01
00
Fourth
Address
A1:A0
10
11
00
01
10
11
11
10
01
10
11
00
10
11
00
01
10
11
00
01
11
10
01
00
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
Min
Max
Unit
IDDZZ
Snooze mode standby current
ZZ > VDD– 0.2 V
–
40
mA
tZZS
Device operation to ZZ
ZZ > VDD – 0.2 V
–
2tCYC
ns
tZZREC
ZZ recovery time
ZZ < 0.2 V
2tCYC
–
ns
tZZI
ZZ active to snooze current
This parameter is sampled
–
2tCYC
ns
tRZZI
ZZ Inactive to exit snooze current This parameter is sampled
0
–
ns
Document Number: 38-05519 Rev. *Q
Page 7 of 24
CY7C1327G
Truth Table
The Truth Table for CY7C1327G follows. [3, 4, 5, 6, 7]
Next Cycle
Add. Used
CE1
CE2
CE3
ZZ
ADSP ADSC ADV WRITE
OE
CLK
Deselect cycle, power-down
None
H
X
X
L
X
L
X
X
X
L–H Tristate
Deselect cycle, power-down
None
L
L
X
L
L
X
X
X
X
L–H Tristate
Deselect cycle, power-down
None
L
X
H
L
L
X
X
X
X
L–H Tristate
Deselect cycle, power-down
None
L
L
X
L
H
L
X
X
X
L–H Tristate
Deselect cycle, power-down
None
L
X
H
L
H
L
X
X
X
L–H Tristate
Snooze mode, power-down
None
X
X
X
H
X
X
X
X
X
Read Cycle, Begin Burst
External
L
H
L
L
L
X
X
X
L
L–H Q
Read Cycle, Begin Burst
External
L
H
L
L
L
X
X
X
H
L–H Tristate
Write Cycle, Begin Burst
External
L
H
L
L
H
L
X
L
X
L–H D
Read Cycle, Begin Burst
External
L
H
L
L
H
L
X
H
L
L–H Q
Read Cycle, Begin Burst
External
L
H
L
L
H
L
X
H
H
L–H Tristate
Read Cycle, Continue Burst
Next
X
X
X
L
H
H
L
H
H
L–H Tristate
Read Cycle, Continue Burst
Next
X
X
X
L
H
H
L
H
L
L–H Q
Read Cycle, Continue Burst
Next
H
X
X
L
X
H
L
H
L
L–H Q
Read Cycle, Continue Burst
Next
H
X
X
L
X
H
L
H
H
L–H Tristate
Write cycle, continue burst
Next
X
X
X
L
H
H
L
L
X
L–H D
Write cycle, continue burst
Next
H
X
X
L
X
H
L
L
X
L–H D
Read cycle, suspend burst
Current
X
X
X
L
H
H
H
H
L
L–H Q
Read cycle, suspend burst
Current
X
X
X
L
H
H
H
H
H
L–H Tristate
Read cycle, suspend burst
Current
H
X
X
L
X
H
H
H
L
L–H Q
Read cycle, suspend burst
Current
H
X
X
L
X
H
H
H
H
L–H Tristate
Write cycle, suspend burst
Current
X
X
X
L
H
H
H
L
X
L–H D
Write cycle, suspend burst
Current
H
X
X
L
X
H
H
L
X
L–H D
X
DQ
Tristate
Notes
3. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
4. WRITE = L when any one or more byte write enable signals (BWA, BWB) and BWE = L or GW = L. WRITE = H when all byte write enable signals (BWA, BWB), BWE,
GW = H.
5. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW[A: B]. Writes may occur only on subsequent clocks after
the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tristate. OE is a don't care for
the remainder of the write cycle.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tristate when OE is inactive
or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document Number: 38-05519 Rev. *Q
Page 8 of 24
CY7C1327G
Truth Table for Read/Write
The Truth Table for Read/Write follows. [8]
Function
GW
BWE
BWB
BWA
Read
H
H
X
X
Read
H
L
H
H
Write byte A – (DQA and DQPA)
H
L
H
L
Write byte B – (DQB and DQPB)
H
L
L
H
Write bytes B, A
H
L
L
L
Write all bytes
H
L
L
L
Write all bytes
L
X
X
X
Note
8. X = “Don't Care.” H = Logic HIGH, L = Logic LOW.
Document Number: 38-05519 Rev. *Q
Page 9 of 24
CY7C1327G
Maximum Ratings
Operating Range
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Range
Ambient
Temperature
0 C to +70 C
VDD
VDDQ
3.3 V– 5% /
+ 10%
2.5 V – 5% to
VDD
Storage temperature ................................ –65 C to +150 C
Commercial
Ambient temperature with
power applied .......................................... –55 C to +125 C
Industrial
Supply voltage on VDD relative to GND .......–0.5 V to +4.6 V
Neutron Soft Error Immunity
Supply voltage on VDDQ relative to GND ...... –0.5 V to +VDD
DC voltage applied to outputs
in tristate ...........................................–0.5 V to VDDQ + 0.5 V
DC input voltage ................................. –0.5 V to VDD + 0.5 V
Parameter
–40 C to +85 C
Description
Latch-up current .................................................... > 200 mA
Max*
Unit
LSBU
Logical
single-bit
upsets
25 °C
361
394
FIT/
Mb
LMBU
Logical
multi-bit
upsets
25 °C
0
0.01
FIT/
Mb
Single event
latch-up
85 °C
0
0.1
FIT/
Dev
Current into outputs (LOW) ........................................ 20 mA
Static discharge voltage
(per MIL-STD-883, method 3015) .......................... > 2001 V
Test
Conditions Typ
SEL
* No LMBU or SEL events occurred during testing; this column represents a
statistical 2, 95% confidence limit calculation. For more details refer to Application
Note AN54908 “Accelerated Neutron SER Testing and Calculation of Terrestrial
Failure Rates”.
Electrical Characteristics
Over the Operating Range
Parameter [9, 10]
Min
Max
Unit
VDD
Power supply voltage
Description
3.135
3.6
V
VDDQ
I/O supply voltage
2.375
VDD
V
VOH
Output HIGH voltage
for 3.3 V I/O, IOH = –4.0 mA
2.4
–
V
for 2.5 V I/O, IOH = –1.0 mA
VOL
Output LOW voltage
2.0
–
V
for 3.3 V I/O, IOL = 8.0 mA
–
0.4
V
for 2.5 V I/O, IOL = 1.0 mA
–
0.4
V
2.0
VDD + 0.3 V
V
for 2.5 V I/O
1.7
VDD + 0.3 V
V
for 3.3 V I/O
–0.3
0.8
V
for 2.5 V I/O
–0.3
0.7
V
Input leakage current except ZZ GND VI VDDQ
and MODE
–5
5
A
Input current of MODE
Input = VSS
–30
–
A
Input = VDD
–
5
A
[9.]
VIH
Input HIGH voltage
VIL
Input LOW voltage [9.]
IX
Input current of ZZ
IOZ
Test Conditions
Output leakage current
for 3.3 V I/O
Input = VSS
–5
–
A
Input = VDD
–
30
A
GND VI VDDQ, output disabled
–5
5
A
Notes
9. Overshoot: VIH(AC) < VDD + 1.5 V (Pulse width less than tCYC/2), undershoot: VIL(AC) > –2 V (Pulse width less than tCYC/2).
10. TPower-up: Assumes a linear ramp from 0 V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
Document Number: 38-05519 Rev. *Q
Page 10 of 24
CY7C1327G
Electrical Characteristics (continued)
Over the Operating Range
Parameter [9, 10]
Description
VDD operating supply current
IDD
ISB1
Automatic CE power-down
current – TTL inputs
Test Conditions
VDD = Max, IOUT = 0 mA,
f = fMAX = 1/tCYC
VDD = Max, device deselected,
VIN VIH or VIN VIL,
f = fMAX = 1/tCYC
Min
Max
Unit
6 ns cycle,
166 MHz
–
240
mA
7.5 ns cycle,
133 MHz
–
225
mA
6 ns cycle,
166 MHz
–
100
mA
7.5 ns cycle,
133 MHz
–
90
mA
ISB2
Automatic CE power-down
current – CMOS inputs
VDD = Max, device deselected, All speeds
VIN 0.3 V or VIN > VDDQ – 0.3 V,
f=0
–
40
mA
ISB3
Automatic CE power-down
current – CMOS inputs
VDD = Max, device deselected, 6 ns cycle,
VIN 0.3 V or VIN > VDDQ – 0.3 V, 166 MHz
f = fMAX = 1/tCYC
7.5 ns cycle,
133 MHz
–
85
mA
–
75
mA
VDD = Max, device deselected,
VIN VIH or VIN VIL, f = 0
–
45
mA
ISB4
Automatic CE power-down
current – TTL inputs
All speeds
Capacitance
Parameter [11]
Description
CIN
Input capacitance
CCLK
Clock input capacitance
CI/O
Input/output capacitance
100-pin TQFP
Max
Unit
5
pF
5
pF
5
pF
Test Conditions
100-pin TQFP
Package
Unit
Test conditions follow standard test methods and
procedures for measuring thermal impedance, per
EIA/JESD51.
30.32
°C/W
6.85
°C/W
Test Conditions
TA = 25 C, f = 1 MHz,
VDD = 3.3 V, VDDQ = 3.3 V
Thermal Resistance
Parameter [11]
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
Note
11. Tested initially and after any design or process change that may affect these parameters.
Document Number: 38-05519 Rev. *Q
Page 11 of 24
CY7C1327G
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms
3.3 V I/O Test Load
R = 317
3.3 V
OUTPUT
OUTPUT
RL = 50
Z0 = 50
GND
5 pF
R = 351
VT = 1.5 V
INCLUDING
JIG AND
SCOPE
(a)
2.5 V I/O Test Load
OUTPUT
RL = 50
Z0 = 50
Document Number: 38-05519 Rev. *Q
INCLUDING
JIG AND
SCOPE
1 ns
1 ns
(c)
ALL INPUT PULSES
VDDQ
GND
5 pF
R = 1538
(b)
90%
10%
90%
(b)
VT = 1.25 V
(a)
10%
R = 1667
2.5 V
OUTPUT
ALL INPUT PULSES
VDDQ
10%
90%
10%
90%
1 ns
1 ns
(c)
Page 12 of 24
CY7C1327G
Switching Characteristics
Over the Operating Range
Parameter [12, 13]
tPOWER
Description
VDD(typical) to the first access [14]
-166
-133
Unit
Min
Max
Min
Max
1
–
1
–
ms
Clock
tCYC
Clock cycle time
6.0
–
7.5
–
ns
tCH
Clock HIGH
2.5
–
3.0
–
ns
tCL
Clock LOW
2.5
–
3.0
–
ns
Output Times
tCO
Data output valid after CLK rise
–
3.5
–
4.0
ns
tDOH
Data output hold after CLK rise
1.5
–
1.5
–
ns
0
–
0
–
ns
–
3.5
–
4.0
ns
–
3.5
–
4.5
ns
0
–
0
–
ns
–
3.5
–
4.0
ns
[15, 16, 17]
tCLZ
Clock to low Z
tCHZ
Clock to high Z [15, 16, 17]
tOEV
OE LOW to output valid
tOELZ
tOEHZ
OE LOW to output low Z
[15, 16, 17]
OE HIGH to output high Z
[15, 16, 17]
Set-up Times
tAS
Address set-up before CLK rise
1.5
–
1.5
–
ns
tADS
ADSC, ADSP setup before CLK rise
1.5
–
1.5
–
ns
tADVS
ADV setup before CLK rise
1.5
–
1.5
–
ns
tWES
GW, BWE, BWX setup before CLK rise
1.5
–
1.5
–
ns
tDS
Data input setup before CLK rise
1.5
–
1.5
–
ns
tCES
Chip enable setup before CLK rise
1.5
–
1.5
–
ns
tAH
Address hold after CLK rise
0.5
–
0.5
–
ns
tADH
ADSP, ADSC hold after CLK rise
0.5
–
0.5
–
ns
tADVH
ADV hold after CLK rise
0.5
–
0.5
–
ns
tWEH
GW, BWE, BWX hold after CLK rise
0.5
–
0.5
–
ns
tDH
Data input hold after CLK rise
0.5
–
0.5
–
ns
tCEH
Chip enable hold after CLK rise
0.5
–
0.5
–
ns
Hold Times
Notes
12. Timing references level is 1.5 V when VDDQ = 3.3 V and is 1.25 V when VDDQ = 2.5 V on all data sheets.
13. Test conditions shown in (a) of Figure 2 on page 12 unless otherwise noted.
14. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a read or write operation can
be initiated.
15. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of Figure 2 on page 12. Transition is measured ±200 mV from steady-state voltage.
16. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data
bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve
high Z prior to low Z under the same system conditions.
17. This parameter is sampled and not 100% tested.
Document Number: 38-05519 Rev. *Q
Page 13 of 24
CY7C1327G
Switching Waveforms
Figure 3. Read Cycle Timing [18]
t CYC
CLK
t
t
CH
t
CL
t
ADH
ADS
ADSP
t ADS
tADH
ADSC
t AS
ADDRESS
tAH
A1
A2
t WES
A3
Burst continued with
new base address
tWEH
GW, BWE,
BW [A:B]
t CES
Deselect
cycle
tCEH
CE
t ADVS tADVH
ADV
ADV
suspends
burst.
OE
t OEHZ
t CLZ
Data Out (Q)
High-Z
Q(A1)
t OEV
t CO
t OELZ
t DOH
Q(A2)
t CHZ
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
t CO
Single READ
BURST READ
DON’T CARE
Burst wraps around
to its initial state
UNDEFINED
Note
18. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
Document Number: 38-05519 Rev. *Q
Page 14 of 24
CY7C1327G
Switching Waveforms (continued)
Figure 4. Write Cycle Timing [19, 20]
t CYC
CLK
tCH
t ADS
tCL
tADH
ADSP
t ADS
ADSC extends burst
tADH
t ADS
tADH
ADSC
t AS
tAH
A1
ADDRESS
A2
A3
Byte write signals are
ignored for first cycle when
ADSP initiates burst
t WES tWEH
BWE,
BW[A :B]
t WES tWEH
GW
t CES
tCEH
CE
t
t
ADVS ADVH
ADV
ADV suspends burst
OE
t DS
Data In (D)
High-Z
t
OEHZ
tDH
D(A1)
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
Data Out (Q)
BURST READ
Single WRITE
BURST WRITE
DON’T CARE
Extended BURST WRITE
UNDEFINED
Notes
19. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
20. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW[A:B] LOW.
Document Number: 38-05519 Rev. *Q
Page 15 of 24
CY7C1327G
Switching Waveforms (continued)
Figure 5. Read/Write Cycle Timing [21, 22, 23]
tCYC
CLK
tCL
tCH
t ADS
tADH
t AS
tAH
ADSP
ADSC
ADDRESS
A1
A2
A3
A4
A5
A6
t WES tWEH
BWE,
BW [A:B]
t CES
tCEH
CE
ADV
OE
t DS
tCO
Data In (D)
t OELZ
High-Z
tCLZ
Data Out (Q)
tDH
High-Z
Q(A1)
Back-to-Back READs
tOEHZ
D(A5)
D(A3)
Q(A2)
Q(A4)
Single WRITE
Q(A4+1)
BURST READ
DON’T CARE
Q(A4+2)
D(A6)
Q(A4+3)
Back-to-Back
WRITEs
UNDEFINED
Notes
21. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
22. The data bus (Q) remains in high Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC.
23. GW is HIGH.
Document Number: 38-05519 Rev. *Q
Page 16 of 24
CY7C1327G
Switching Waveforms (continued)
Figure 6. ZZ Mode Timing [24, 25]
CLK
t
ZZ
I
t
t
ZZ
ZZREC
ZZI
SUPPLY
I
t RZZI
DDZZ
ALL INPUTS
(except ZZ)
Outputs (Q)
DESELECT or READ Only
High-Z
DON’T CARE
Notes
24. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.
25. DQs are in high Z when exiting ZZ sleep mode.
Document Number: 38-05519 Rev. *Q
Page 17 of 24
CY7C1327G
Ordering Information
The table below contains only the parts that are currently available. If you don’t see what you are looking for, please contact your
local sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary
page at http://www.cypress.com/products
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office
closest to you, visit us at http://www.cypress.com/go/datasheet/offices
Speed
(MHz)
Package
Diagram
Ordering Code
Package Type
Operating
Range
133
CY7C1327G-133AXI
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
Industrial
166
CY7C1327G-166AXC
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
Commercial
Ordering Code Definitions
CY
7
C 1327
G - XXX
A
X
X
Temperature range: X = C or I
C = Commercial; I = Industrial
Pb-free
Package Type:
A = 100-pin TQFP
Speed Grade: XXX = 133 MHz or 166 MHz
Process Technology: G 90 nm
1327 = SCD, 256 K × 18 (4 Mb)
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 38-05519 Rev. *Q
Page 18 of 24
CY7C1327G
Package Diagrams
Figure 7. 100-pin TQFP (16 × 22 × 1.6 mm) A100RA Package Outline, 51-85050
ș2
ș1
ș
SYMBOL
DIMENSIONS
MIN. NOM. MAX.
A
A1
1.60
0.05
0.15
NOTE:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. BODY LENGTH DIMENSION DOES NOT
INCLUDE MOLD PROTRUSION/END FLASH.
A2
1.35 1.40 1.45
D
15.80 16.00 16.20
MOLD PROTRUSION/END FLASH SHALL
D1
13.90 14.00 14.10
E
21.80 22.00 22.20
NOT EXCEED 0.0098 in (0.25 mm) PER SIDE.
BODY LENGTH DIMENSIONS ARE MAX PLASTIC
E1
19.90 20.00 20.10
R1
0.08
0.20
R2
0.08
0.20
ș
0°
7°
ș1
0°
ș2
11°
13°
12°
0.20
c
b
0.22 0.30 0.38
L
0.45 0.60 0.75
L1
L2
L3
e
BODY SIZE INCLUDING MOLD MISMATCH.
3. JEDEC SPECIFICATION NO. REF: MS-026.
1.00 REF
0.25 BSC
0.20
0.65 TYP
51-85050 *F
Document Number: 38-05519 Rev. *Q
Page 19 of 24
CY7C1327G
Acronyms
Acronym
Document Conventions
Description
Units of Measure
CE
Chip Enable
CMOS
Complementary Metal Oxide Semiconductor
°C
degree Celsius
EIA
Electronic Industries Alliance
MHz
megahertz
I/O
Input/Output
µA
microampere
JEDEC
Joint Electron Devices Engineering Council
mA
milliampere
LMBU
Logical Multi-Bit Upsets
ms
millisecond
LSBU
Logical Single-Bit Upsets
mm
millimeter
OE
Output Enable
mV
millivolt
SEL
Single Event Latch-Up
nm
nanometer
SRAM
Static Random Access Memory
TQFP
Thin Quad Flat Pack
TTL
Transistor-Transistor Logic
Document Number: 38-05519 Rev. *Q
Symbol
Unit of Measure
ns
nanosecond
ohm
%
percent
pF
picofarad
V
volt
W
watt
Page 20 of 24
CY7C1327G
Errata
This section describes the Ram9 Sync ZZ pin issue. Details include trigger conditions, the devices affected, proposed workaround
and silicon revision applicability. Please contact your local Cypress sales representative if you have further questions.
Part Numbers Affected
Density & Revision
Package Type
Operating Range
4Mb-Ram9 Synchronous SRAMs: CY7C132*G
100-pin TQFP
Commercial/
Industrial
Product Status
All of the devices in the Ram9 4Mb Sync family are qualified and available in production quantities.
Ram9 Sync ZZ Pin Issues Errata Summary
The following table defines the errata applicable to available Ram9 4Mb Sync family devices.
Item
1.
Issues
ZZ Pin
Description
Device
When asserted HIGH, the ZZ pin places
device in a “sleep” condition with data integrity
preserved.The ZZ pin currently does not have
an internal pull-down resistor and hence
cannot be left floating externally by the user
during normal mode of operation.
4M-Ram9 (90nm)
Fix Status
For the 4M Ram9 (90 nm)
devices, there is no plan to fix
this issue.
1. ZZ Pin Issue
■
PROBLEM DEFINITION
The problem occurs only when the device is operated in the normal mode with ZZ pin left floating. The ZZ pin on the SRAM
device does not have an internal pull-down resistor. Switching noise in the system may cause the SRAM to recognize a HIGH
on the ZZ input, which may cause the SRAM to enter sleep mode. This could result in incorrect or undesirable operation of the
SRAM.
■
TRIGGER CONDITIONS
Device operated with ZZ pin left floating.
■
SCOPE OF IMPACT
When the ZZ pin is left floating, the device delivers incorrect data.
■
WORKAROUND
Tie the ZZ pin externally to ground.
■
FIX STATUS
For the 4M Ram9 (90 nm) devices, there is no plan to fix this issue.
Document Number: 38-05519 Rev. *Q
Page 21 of 24
CY7C1327G
Document History Page
Document Title: CY7C1327G, 4-Mbit (256K × 18) Pipelined Sync SRAM
Document Number: 38-05519
Rev.
ECN No.
Submission
Date
Orig. of
Change
Description of Change
**
224367
See ECN
RKF
New data sheet.
*A
278513
See ECN
VBL
Updated Ordering Information (Updated part numbers (Changed TQFP to
Pb-free TQFP, added PB-free BGA packages)).
*B
332895
See ECN
SYT
Updated Features (Removed 225 MHz, 100 MHz frequencies related
information).
Updated Selection Guide (Removed 225 MHz, 100 MHz frequencies related
information).
Updated Pin Configurations (Modified Address Expansion balls in the pinouts
for 100-pin TQFP and 119-ball BGA Packages as per JEDEC standards).
Updated Pin Definitions.
Updated Electrical Characteristics (Removed 225 MHz, 100 MHz frequencies
related information, updated Test Conditions of VOL and VOH parameters).
Updated Thermal Resistance (Replaced values of JA and JC parameters
from TBD to respective Thermal Values for all packages).
Updated Switching Characteristics (Removed 225 MHz, 100 MHz frequencies
related information).
Updated Ordering Information (By shading and unshading MPNs as per
availability, removed comment on the availability of BGA lead-free package).
*C
351194
See ECN
PCI
Updated Ordering Information (Updated part numbers).
*D
366728
See ECN
PCI
Updated Electrical Characteristics (Added test conditions for VDD and VDDQ
parameters, updated Note 10 (Replaced VIH < VDD with VIH < VDD)).
*E
419256
See ECN
RXU
Changed status from Preliminary to Final.
Changed address of Cypress Semiconductor Corporation from “3901 North
First Street” to “198 Champion Court”.
Updated Electrical Characteristics (Changed “Input Load Current except ZZ
and MODE” to “Input Leakage Current except ZZ and MODE” in the description
of IX parameter).
Updated Ordering Information (Updated part numbers, replaced Package
Name column with Package Diagram in the Ordering Information table).
Updated Package Diagrams (spec 51-85050 (changed revision from *A to *B)).
*F
480124
See ECN
VKN
Updated Maximum Ratings (Added the Maximum Rating for Supply Voltage
on VDDQ Relative to GND).
Updated Ordering Information (Updated part numbers).
*G
2756340
08/26/2009
*H
3044512
10/01/2010
NJY
Added Ordering Code Definitions.
Updated Package Diagrams.
Added Acronyms and Units of Measure.
Minor edits.
Updated to new template.
*I
3363203
09/05/2011
PRIT
Updated Package Diagrams.
Updated in new template.
Document Number: 38-05519 Rev. *Q
VKN/AESA Added Neutron Soft Error Immunity.
Updated Ordering Information (By including parts that are available, and
modified the disclaimer for the Ordering information).
Page 22 of 24
CY7C1327G
Document History Page (continued)
Document Title: CY7C1327G, 4-Mbit (256K × 18) Pipelined Sync SRAM
Document Number: 38-05519
Rev.
ECN No.
Submission
Date
Orig. of
Change
Description of Change
*J
3612268
05/09/2012
PRIT
Updated Features (Removed 250 MHz, 200 MHz frequencies related
information, removed 119-ball BGA package related information).
Updated Functional Description (Removed the Note “For best practices
recommendations, refer to the Cypress application note System Design
Guidelines on www.cypress.com.” and its reference).
Updated Selection Guide (Removed 250 MHz, 200 MHz frequencies related
information).
Updated Pin Configurations (Removed 119-ball BGA package related
information).
Updated Electrical Characteristics (Removed 250 MHz, 200 MHz frequencies
related information).
Updated Capacitance (Removed 119-ball BGA package related information).
Updated Thermal Resistance (Removed 119-ball BGA package related
information).
Updated Switching Characteristics (Removed 250 MHz, 200 MHz frequencies
related information).
*K
3749841
09/20/2012
PRIT
No technical updates.
Completing Sunset Review.
*L
3984870
05/02/2013
PRIT
Added Errata.
*M
4039228
06/25/2013
PRIT
Added Errata Footnotes (Note 1, 2).
Updated Pin Configurations:
Added Note 1 and referred the same note in Figure 1.
Updated Pin Definitions:
Added Note 2 and referred the same note in ZZ pin.
Updated to new template.
*N
4077099
07/25/2013
PRIT
Updated Truth Table.
*O
4150660
10/08/2013
PRIT
Updated Errata.
*P
4574263
11/19/2014
PRIT
Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
Updated Package Diagrams:
spec 51-85050 – Changed revision from *D to *E.
*Q
5510101
11/04/2016
PRIT
Updated Package Diagrams:
spec 51-85050 – Changed revision from *E to *F.
Updated to new template.
Completing Sunset Review.
Document Number: 38-05519 Rev. *Q
Page 23 of 24
CY7C1327G
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC®Solutions
Products
ARM® Cortex® Microcontrollers
Automotive
cypress.com/arm
cypress.com/automotive
Clocks & Buffers
cypress.com/clocks
Interface
cypress.com/interface
Internet of Things
Lighting & Power Control
cypress.com/iot
cypress.com/powerpsoc
Memory
PSoC
Touch Sensing
USB Controllers
Wireless/RF
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Cypress Developer Community
Forums | Projects | Video | Blogs | Training | Components
Technical Support
cypress.com/support
cypress.com/memory
cypress.com/psoc
cypress.com/touch
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2004-2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 38-05519 Rev. *Q
Revised November 4, 2016
i486 is a trademark, and Intel and Pentium are registered trademarks, of Intel Corporation. PowerPC is a registered trademark of IBM Corporation.
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