CY7C1338F-100BGI

CY7C1338F 4-Mb (128K x 32) Flow-Through Sync SRAM Features • • • • 128K X 32 common I/O 3.3V –5% and +10% core power supply (VDD) 2.5V or 3.3V I/O supply (VDDQ) Fast clock-to-output times — 6.5 ns (133-MHz version) — 7.5 ns (117-MHz version) — 8.0 ns (100-MHz version) — 11.0 ns (66-MHz version) Provide high-performance 2-1-1-1 access rate User-selectable burst counter supporting Intel Pentium interleaved or linear burst sequences Separate processor and controller address strobes Synchronous self-timed write Asynchronous output enable Offered in JEDEC-standard 100-pin TQFP and 119-ball BGA packages “ZZ” Sleep Mode option 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BW[A:D], and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin. The CY7C1338F allows either interleaved or linear burst sequences, selected by the MODE input pin. A HIGH selects an interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses can be initiated with the Processor Address Strobe (ADSP) or the cache Controller Address Strobe (ADSC) inputs. Address advancement is controlled by the Address Advancement (ADV) input. Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor (ADSP) or Address Strobe Controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin (ADV). The CY7C1338F operates from a +3.3V core power supply while all outputs may operate with either a +2.5 or +3.3V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible. • • • • • • • Functional Description[1] The CY7C1338F is a 131,072 x 32 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is Logic Block Diagram A0, A1, A ADDRESS REGISTER A[1:0] MODE ADV CLK BURST Q1 COUNTER AND LOGIC Q0 CLR ADSC ADSP DQD BYTE BWD WRITE REGISTER DQD BYTE WRITE REGISTER BWC DQC BYTE WRITE REGISTER DQC BYTE WRITE REGISTER DQB BYTE BWB DQB BYTE WRITE REGISTER DQA BYTE BWA BWE GW CE1 CE2 CE3 OE DQA BYTE WRITE REGISTER WRITE REGISTER WRITE REGISTER MEMORY ARRAY SENSE AMPS OUTPUT BUFFERS DQs ENABLE REGISTER INPUT REGISTERS ZZ SLEEP CONTROL Note: 1. For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05218 Rev. *A • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised February 2, 2004 CY7C1338F Selection Guide Maximum Access Time Maximum Operating Current Maximum Standby Current 133 MHz 6.5 225 40 117 MHz 7.5 220 40 100 MHz 8.0 205 40 66 MHz 11.0 195 40 Unit ns mA mA Shaded areas contain advance information. Please contact your local Cypress sales representative for availablity of these parts. Pin Configurations 100-Pin TQFP BWD BWC BWB BWA CE3 CE1 VDD VSS OE ADSC ADSP ADV 86 85 84 83 CE2 CLK GW BWE A A 82 A 99 98 97 96 95 94 93 92 91 90 89 88 87 NC DQC DQC VDDQ VSSQ DQC DQC BYTE C DQC DQC VSSQ VDDQ DQC DQC NC VDD NC VSS DQD DQD VDDQ VSSQ DQD DQD DQD DQD VSSQ VDDQ DQD DQD NC BYTE D 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 100 81 A CY7C1338F 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 44 45 46 47 48 49 50 NC DQB DQB VDDQ VSSQ DQB DQB DQB DQB VSSQ VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSSQ DQA DQA DQA DQA VSSQ VDDQ DQA DQA NC BYTE B BYTE A 38 39 40 41 VDD 42 NC NC MODE A VSS NC NC A A A1 A0 A A A 43 A A A A Document #: 38-05218 Rev. *A A Page 2 of 17 CY7C1338F Pin Configurations (continued) 119-Ball BGA 1 A B C D E F G H J K L M N P R T U VDDQ NC NC DQC DQC VDDQ DQC DQC VDDQ DQD DQD VDDQ DQD DQD NC NC VDDQ 2 A CE2 A NC DQC DQC DQC DQC VDD DQD DQD DQD DQD NC A NC NC 3 A A A VSS VSS VSS BWC VSS NC VSS BWD VSS VSS VSS MODE A NC 4 ADSP ADSC VDD NC CE1 OE ADV GW VDD CLK NC BWE A1 A0 VDD A NC 5 A A A VSS VSS VSS BWB VSS NC VSS BWA VSS VSS VSS NC A NC 6 A NC A NC DQB DQB DQB DQB VDD DQA DQA DQA DQA NC A NC NC 7 VDDQ NC NC DQB DQB VDDQ DQB DQB VDDQ DQA DQA VDDQ DQA DQA NC ZZ VDDQ Pin Descriptions Name A0, A1, A TQFP BGA I/O Description InputAddress Inputs used to select one of the 128K address locations. 37,36,32, P4,N4,A2, 33,34,35, A3,A5,A6, Synchronous Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW, 44,45,46, B3,B5,C2, and CE1, CE2, and CE3 are sampled active. A[1:0] feed the 2-bit counter. 47,48,49, C3,C5,C6, 50,81,82, R2,R6,T3, T4,T5 99,100 93,94,95, L5,G5,G3, InputByte Write Select Inputs, active LOW. Qualified with BWE to conduct 96 L3 Synchronous byte writes to the SRAM. Sampled on the rising edge of CLK. 88 H4 InputGlobal Write Enable Input, active LOW. When asserted LOW on the Synchronous rising edge of CLK, a global write is conducted (ALL bytes are written, regardless of the values on BW[A:D] and BWE). InputByte Write Enable Input, active LOW. Sampled on the rising edge of Synchronous CLK. This signal must be asserted LOW to conduct a byte write. Input-Clock Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst counter when ADV is asserted LOW, during a burst operation. InputChip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Synchronous Used in conjunction with CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. InputChip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Synchronous Used in conjunction with CE1 and CE3 to select/deselect the device. InputChip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Synchronous Used in conjunction with CE1 and CE2 to select/deselect the device. InputOutput Enable, asynchronous input, active LOW. Controls the direction Asynchronous of the I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE is masked during the first clock of a read cycle when emerging from a deselected state. Page 3 of 17 BWA,BWB BWC,BWD GW BWE CLK 87 89 M4 K4 CE1 CE2 CE3 OE 98 E4 97 92 86 B2 F4 Document #: 38-05218 Rev. *A CY7C1338F Pin Descriptions (continued) Name ADV ADSP TQFP 83 84 BGA G4 A4 I/O Description InputAdvance Input signal, sampled on the rising edge of CLK. When Synchronous asserted, it automatically increments the address in a burst cycle. InputAddress Strobe from Processor, sampled on the rising edge of CLK, Synchronous active LOW. When asserted LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH InputAddress Strobe from Controller, sampled on the rising edge of CLK, Synchronous active LOW. When asserted LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. InputZZ “sleep” Input, active HIGH. When asserted HIGH places the device Asynchronous in a non-time-critical “sleep” condition with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin has an internal pull-down. ADSC 85 B4 ZZ 64 T7 DQs 52,53,56, 57,58,59, 62,63,68, 69,72,73, 74,75,78, 79,2,3,6, 7,8,9,12, 13,18,19, 22,23,24, 25,28,29 15,41,65, 91 I/OBidirectional Data I/O lines. As inputs, they feed into an on-chip data K6,K7,L6, L7,M6,N6, Synchronous register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the addresses N7,P7,D7, presented during the previous clock rise of the read cycle. The direction of E6,E7,F6, the pins is controlled by OE. When OE is asserted LOW, the pins behave G6,G7,H6, H7,D1,E1, as outputs. When HIGH, DQs are placed in a three-state condition. E2,F2,G1, G2,H1,H2, K1,K2,L1, L2,M2,N1 N2,P1 C4,J2,J4, R4,J6 Power Supply Ground Power supply inputs to the core of the device. Ground for the core of the device. VDD VSS 17,40,67, D3,D5,E3, 90 E5,F3,F5, H3,H5,K3, K5,M3,M5, N3,N5,P3, P5 4,11,20, A1,A7,F1, 27,54,61, F7,J1,J7, 70,77 M1,M7,U1, U7 5,10,21,55 ,60,71,76 31 – R3 VDDQ I/O Power Power supply for the I/O circuitry. Supply VSSQ MODE I/O Ground Ground for the I/O circuitry. InputStatic Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD or left floating selects interleaved burst sequence. This is a strap pin and should remain static during device operation. Mode Pin has an internal pull-up. No Connects. Not Internally connected to the die. NC 14,16,38, B1,B6,B7, 39,42,43, C1,C7,D4, 66,51,80, J3,J5,L4, 1,30 R1,R5,R7, T1,T2,T6, U2,U3,U4, U5,U6,P6, D6,D2,P2 Document #: 38-05218 Rev. *A Page 4 of 17 CY7C1338F Functional Overview All synchronous inputs pass through input registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (t C0) is 6.5 ns (133-MHz device). The CY7C1338F supports secondary cache in systems utilizing either a linear or interleaved burst sequence. The interleaved burst order supports Pentium® and i486 processors. The linear burst sequence is suited for processors that utilize a linear burst sequence. The burst order is user-selectable, and is determined by sampling the MODE input. Accesses can be initiated with either the Processor Address Strobe (ADSP) or the Controller Address Strobe (ADSC). Address advancement through the burst sequence is controlled by the ADV input. A two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. Byte write operations are qualified with the Byte Write Enable (BWE) and Byte Write Select (BW[A:D]) inputs. A Global Write Enable (GW) overrides all byte write inputs and writes data to all four bytes. All writes are simplified with on-chip synchronous self-timed write circuitry. Three synchronous Chip Selects (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output three-state control. ADSP is ignored if CE1 is HIGH. Single Read Accesses A single read access is initiated when the following conditions are satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted active, and (2) ADSP or ADSC is asserted LOW (if the access is initiated by ADSC, the write inputs must be deasserted during this first cycle). The address presented to the address inputs is latched into the address register and the burst counter/control logic and presented to the memory core. If the OE input is asserted LOW, the requested data will be available at the data outputs a maximum to tCDV after clock rise. ADSP is ignored if CE1 is HIGH. Single Write Accesses Initiated by ADSP This access is initiated when the following conditions are satisfied at clock rise: (1) CE1, CE2, CE3 are all asserted active, and (2) ADSP is asserted LOW. The addresses presented are loaded into the address register and the burst inputs (GW, BWE, and BW[A:D] )are ignored during this first clock cycle. If the write inputs are asserted active (see Write Cycle Descriptions table for appropriate states that indicate a write) on the next clock rise,the appropriate data will be latched and written into the device. Byte writes are allowed. During byte writes, BWA controls DQA and BWB controls DQB. BWC controls DQC, and BWD controls DQD. All I/Os are three-stated during a byte write.Since this is a common I/O device, the asynchronous OE input signal must be deasserted and the I/Os must be three-stated prior to the presentation of data to DQs. As a safety precaution, the data lines are three-stated once a write cycle is detected, regardless of the state of OE. Single Write Accesses Initiated by ADSC This write access is initiated when the following conditions are satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted active, (2) ADSC is asserted LOW, (3) ADSP is deasserted HIGH, and (4) the write input signals (GW, BWE, and BW[A:D]) indicate a write access. ADSC is ignored if ADSP is active LOW. The addresses presented are loaded into the address register and the burst counter/control logic and delivered to the memory core. The information presented to DQ[A:D] will be written into the specified address location. Byte writes are allowed. During byte writes, BWA controls DQA, BWB controls DQB, BWC controls DQC, and BWD controls DQD. All I/Os are three-stated when a write is detected, even a byte write. Since this is a common I/O device, the asynchronous OE input signal must be deasserted and the I/Os must be three-stated prior to the presentation of data to DQs. As a safety precaution, the data lines are three-stated once a write cycle is detected, regardless of the state of OE. Burst Sequences The CY7C1338F provides an on-chip two-bit wraparound burst counter inside the SRAM. The burst counter is fed by A[1:0], and can follow either a linear or interleaved burst order. The burst order is determined by the state of the MODE input. A LOW on MODE will select a linear burst sequence. A HIGH on MODE will select an interleaved burst order. Leaving MODE unconnected will cause the device to default to a interleaved burst sequence. Sleep Mode The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the “sleep” mode. CEs, ADSP, and ADSC must remain inactive for the duration of tZZREC after the ZZ input returns LOW. Interleaved Burst Address Table (MODE = Floating or VDD) First Address A1, A0 00 01 10 11 Second Address A1, A0 01 00 11 10 Third Address A1, A0 10 11 00 01 Fourth Address A1, A0 11 10 01 00 Linear Burst Address Table (MODE = GND) First Address A1, A0 00 01 10 11 Second Address A1, A0 01 10 11 00 Third Address A1, A0 10 11 00 01 Fourth Address A1, A0 11 00 01 10 Page 5 of 17 Document #: 38-05218 Rev. *A CY7C1338F ZZ Mode Electrical Characteristics Parameter IDDZZ tZZS tZZREC tZZI tRZZI Description Snooze mode standby current Device operation to ZZ ZZ recovery time ZZ active to snooze current ZZ Inactive to exit snooze current Test Conditions ZZ > VDD – 0.2V ZZ > VDD – 0.2V ZZ < 0.2V This parameter is sampled This parameter is sampled 0 2tCYC 2tCYC Min. Max. 40 2tCYC Unit mA ns ns ns ns Truth Table[2, 3, 4, 5, 6] Cycle Description Deselected Cycle, Power-down Deselected Cycle, Power-down Deselected Cycle, Power-down Deselected Cycle, Power-down Deselected Cycle, Power-down Snooze Mode, Power-down Read Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Begin Burst Read Cycle, Begin Burst Read Cycle, Begin Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Continue Burst Write Cycle, Continue Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Write Cycle, Suspend Burst Write Cycle, Suspend Burst Address Used None None None None None None External External External External External Next Next Next Next Next Next Current Current Current Current Current Current CE1 CE2 CE3 H L L L X X L L L L L X X H H X H X X H H X H X L X L X X H H H H H X X X X X X X X X X X X X X H X X X L L L L L X X X X X X X X X X X X ZZ ADSP ADSC ADV WRITE L L L L L H L L L L L L L L L L L L L L L L L X L L H H X L L H H H H H X X H X H H X X H X L X X L L X X X L L L H H H H H H H H H H H H X X X X X X X X X X X L L L L L L H H H H H H X X X X X X X X L H H H H H H L L H H H H L L OE X X X X X X L H X L H L H L H X X L H L H X X CLK DQ L-H three-state L-H three-state L-H three-state L-H three-state L-H three-state X three-state L-H Q L-H three-state L-H D L-H Q L-H three-state L-H Q L-H three-state L-H Q L-H three-state L-H D L-H D L-H Q L-H three-state L-H Q L-H three-state L-H D L-H D Notes: 2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. 3. WRITE = L when any one or more Byte Write enable signals (BWA, BWB, BWC, BWD) and BWE = L or GW= L. WRITE = H when all Byte write enable signals ( BWA, BWB, BWC, BWD), BWE, GW = H. 4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock. 5. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW[A:D]. Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state. OE is a don't care for the remainder of the write cycle. 6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are three-state when OE is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW). 7. Table only lists a partial listing of the byte write combinations. Any combination of BW[A:D] is valid. Appropriate write will be done based on which byte write is active. Document #: 38-05218 Rev. *A Page 6 of 17 CY7C1338F Partial Truth Table for Read/Write[2, 7] Function Read Read Write Byte A Write Byte B Write Bytes B, A Write Byte C Write Bytes C, A Write Bytes C, B Write Bytes C, B, A Write Byte D Write Bytes D, A Write Bytes D, B Write Bytes D, B, A Write Bytes D, B Write Bytes D, B, A Write Bytes D, C, A Write All Bytes Write All Bytes GW H H H H H H H H H H H H H H H H H L BWE H L L L L L L L L L L L L L L L L X BWD X H H H H H H H H L L L L L L L L X BWC X H H H H L L L L H H H H L L L L X BWB X H H L L H H L L H H L L H H L L X BWA X H L H L H L H L H L H L H L H L X Document #: 38-05218 Rev. *A Page 7 of 17 CY7C1338F Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage on VDD Relative to GND........ –0.5V to +4.6V DC Voltage Applied to Outputs in three-state ....................................... –0.5V to VDDQ + 0.5V DC Input Voltage....................................–0.5V to VDD + 0.5V Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage........................................... >2001V (per MIL-STD-883, Method 3015) Latch-up Current..................................................... >200 mA Operating Range Range Commercial Industrial Ambient Temperature] 0°C to +70°C –40°C to +85°C VDD VDDQ 3.3V −5%/+10% 2.5V –5% to VDD Electrical Characteristics Over the Operating Range [8, 9] CY7C1345F Parameter VDD VDDQ VOH VOL VIH VIL IX Description Power Supply Voltage I/O Supply Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[8] Input Load Current (except ZZ and MODE) Input Current of MODE Input Current of ZZ IOZ IOS IDD Output Leakage Current Output Short Circuit Current VDD Operating Supply Current VDDQ = 3.3V, VDD = Min., IOH = –4.0 mA VDDQ = 2.5V, VDD = Min., IOH = –1.0 mA VDDQ = 3.3V, VDD = Min., IOL = 8.0 mA VDDQ = 2.5V, VDD = Min., IOL = 1.0 mA VDDQ = 3.3V VDDQ = 2.5V VDDQ = 3.3V VDDQ = 2.5V GND ≤ VI ≤ VDDQ Input = VSS Input = VDD Input = VSS Input = VDD GND ≤ VI ≤ VDD, Output Disabled VDD = Max., VOUT = GND VDD = Max., IOUT = 0 mA, f = fMAX= 1/tCYC 7.5-ns cycle, 133 MHz 8.0-ns cycle, 117 MHz 10-ns cycle, 100 MHz 15-ns cycle, 66 MHz ISB1 Automatic CE Power-Down Current—TTL Inputs Max. VDD, Device Deselected, 7.5-ns cycle, 133 VIN ≥ VIH or VIN ≤ VIL, f = fMAX, MHz inputs switching 8.0-ns cycle, 117 MHz 10-ns cycle, 100 MHz 15-ns cycle, 66 MHz ISB2 Automatic CE Power-Down Current—CMOS Inputs Max. VDD, Device Deselected, All speeds VIN ≥ VDD – 0.3V or VIN ≤ 0.3V, f = 0, inputs static –5 –5 30 5 –300 225 220 205 195 90 85 80 60 40 2.0 1.7 –0.3 –0.3 −5 –30 5 Test Conditions Min. 3.135 2.375 2.4 2.0 0.4 0.4 VDD + 0.3V VDD + 0.3V 0.8 0.7 5 Max. 3.6 VDD Unit V V V V V V V V V V µA µA µA µA µA µA µA mA mA mA mA mA mA mA mA mA Shaded areas contain advance information. Notes: 8. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC) > -2V (Pulse width less than tCYC/2). 9. TPower-up: Assumes a linear ramp from 0v to VDD(min.) within 200ms. During this time VIH < VDD and VDDQ < VDD. Document #: 38-05218 Rev. *A Page 8 of 17 CY7C1338F Electrical Characteristics Over the Operating Range (continued)[8, 9] CY7C1345F Parameter ISB3 Description Automatic CE Power-Down Current—CMOS Inputs Test Conditions Max. VDD, Device Deselected, VIN ≥ VDDQ – 0.3V or VIN ≤ 0.3V, f = fMAX, inputs switching 7.5-ns cycle, 133 MHz 8.0-ns cycle, 117 MHz 10-ns cycle, 100 MHz 15-ns cycle, 66 MHz ISB4 Automatic CE Power-Down Current—TTL Inputs Max. VDD, Device Deselected, VIN ≥ VDD – 0.3V or VIN ≤ 0.3V, f = 0, inputs static All speeds Min. Max. 75 70 65 45 45 Unit mA mA mA mA mA Thermal Resistance[10] Parameter ΘJA ΘJC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedence, per EIA / JESD51. TQFP Package 41.83 9.99 BGA Package 47.63 11.71 Unit °C/W °C/W Capacitance[10] Parameter CIN CCLK CI/O Description Input Capacitance Clock Input Capacitance Input/Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VDD = 3.3V. VDDQ = 3.3V TQFP Package 5 5 5 BGA Package 5 5 7 Unit pF pF pF AC Test Loads and Waveforms 3.3V I/O Test Load OUTPUT Z0 = 50Ω 3.3V OUTPUT RL = 50Ω R = 317Ω VDD 5 pF GND R = 351Ω 10% ALL INPUT PULSES 90% 90% 10% ≤ 1ns VL = 1.5V ≤ 1ns 2.5V I/O Test Load OUTPUT Z0 = 50Ω (a) 2.5V INCLUDING JIG AND SCOPE (b) R = 1667Ω VDD (c) ALL INPUT PULSES 10% 90% 90% 10% ≤ 1ns OUTPUT RL = 50Ω VL = 1.25V 5 pF GND R =1538Ω ≤ 1ns (a) INCLUDING JIG AND SCOPE (b) (c) Note: 10. Tested initially and after any design or process change that may affect these parameters. Document #: 38-05218 Rev. *A Page 9 of 17 CY7C1338F Switching Characteristics Over the Operating Range [15, 16] 133 MHz Parameter tPOWER Clock tCYC tCH tCL Output Times tCDV tDOH tCLZ tCHZ tOEV tOELZ tOEHZ Setup Times tAS tADS tADVS tWES tDS tCES Hold Times tAH tADH tWEH tADVH tDH tCEH Address Hold After CLK Rise ADSP, ADSC Hold After CLK Rise GW,BWE, BW[A:D] Hold After CLK Rise ADV Hold After CLK Rise Data Input Hold After CLK Rise Chip Enable Hold After CLK Rise 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 ns ns ns ns ns ns Address Set-up Before CLK Rise ADSP, ADSC Set-up Before CLK Rise ADV Set-up Before CLK Rise GW, BWE, BW[A:D] Set-up Before CLK Rise Data Input Set-up Before CLK Rise Chip Enable Set-up 1.5 1.5 1.5 1.5 1.5 1.5 2.0 2.0 2.0 2.0 1.5 2.0 2.0 2.0 2.0 2.0 1.5 2.0 2.0 2.0 2.0 2.0 1.5 2.0 ns ns ns ns ns ns Data Output Valid After CLK Rise Data Output Hold After CLK Rise Clock to Low-Z[12, 13, 14] Clock to High-Z[12, 13, 14] OE LOW to Output Valid OE LOW to Output Low-Z[12, 13, 14] OE HIGH to Output High-Z[12, 13, 14] 0 3.5 2.0 0 3.5 3.5 0 3.5 6.5 2.0 0 3.5 3.5 0 3.5 7.5 2.0 0 3.5 3.5 0 6.0 8.0 2.0 0 5.0 6.0 11.0 ns ns ns ns ns ns ns Clock Cycle Time Clock HIGH Clock LOW 7.5 2.5 2.5 8.5 3.0 3.0 10 4.0 4.0 15 5.0 5.0 ns ns ns Description VDD(Typical) to the first Access [11] 117 MHz 1 100 MHz 1 66 MHz Min. 1 Max. Unit ms Min. Max. Min. Max. Min. Max. 1 Shaded areas contain advance information. Notes: 11. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a read or write operation can be initiated. 12. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage. 13. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z prior to Low-Z under the same system conditions. 14. This parameter is sampled and not 100% tested. 15. Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V. 16. Test conditions shown in (a) of AC Test Loads unless otherwise noted. Document #: 38-05218 Rev. *A Page 10 of 17 CY7C1338F Timing Diagrams Read Cycle Timing[17] tCYC CLK t CH t CL tADS tADH ADSP tADS tADH ADSC tAS tAH ADDRESS A1 t WES t WEH A2 GW, BWE,BW [A:D] tCES t CEH Deselect Cycle CE t ADVS t ADVH ADV ADV suspends burst. OE t OEV t CLZ t OEHZ t OELZ tCDV tDOH t CHZ Data Out (Q) High-Z Q(A1) t CDV Q(A2) Q(A2 + 1) Q(A2 + 2) Q(A2 + 3) Q(A2) Q(A2 + 1) Q(A2 + 2) Burst wraps around to its initial state Single READ DON’T CARE BURST READ UNDEFINED Notes: 17. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH. Document #: 38-05218 Rev. *A Page 11 of 17 CY7C1338F Timing Diagrams (continued) Write Cycle Timing[17, 18] t CYC CLK t CH t CL tADS tADH ADSP tADS tADH ADSC extends burst tADS tADH ADSC tAS tAH ADDRESS A1 A2 Byte write signals are ignored for first cycle when ADSP initiates burst A3 tWES tWEH BWE, BW[A:D] t t WES WEH GW tCES tCEH CE tADVS tADVH ADV ADV suspends burst OE t DS t DH D(A2) D(A2 + 1) D(A2 + 1) D(A2 + 2) D(A2 + 3) D(A3) D(A3 + 1) D(A3 + 2) Data in (D) High-Z t OEHZ D(A1) Data Out (Q) BURST READ Single WRITE BURST WRITE Extended BURST WRITE DON’T CARE UNDEFINED Note: 18. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW[A:D] LOW. Document #: 38-05218 Rev. *A Page 12 of 17 CY7C1338F Timing Diagrams (continued) Read/Write Timing[17, 19, 20] tCYC CLK t CH tADS tADH t CL ADSP ADSC tAS tAH ADDRESS A1 A2 A3 t t WES WEH A4 A5 A6 BWE, BW[A:D] tCES tCEH CE ADV OE tDS tDH tOELZ Data In (D) Data Out (Q) High-Z t OEHZ D(A3) tCDV D(A5) D(A6) Q(A1) Q(A2) Single WRITE DON’T CARE Q(A4) Q(A4+1) Q(A4+2) Q(A4+3) Back-to-Back WRITEs Back-to-Back READs BURST READ UNDEFINED Notes: 19. The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC. 20. GW is HIGH. Document #: 38-05218 Rev. *A Page 13 of 17 CY7C1338F Timing Diagrams (continued) ZZ Mode Timing [21, 22] CLK t ZZ t ZZREC ZZ t ZZI I SUPPLY I DDZZ t RZZI DESELECT or READ Only ALL INPUTS (except ZZ) Outputs (Q) High-Z DON’T CARE Ordering Information Speed (MHz) 133 Ordering Code CY7C1338F-133AC CY7C1338F-133BGC CY7C1338F-133AI CY7C1338F-133BGI 117 CY7C1338F-117AC CY7C1338F-117BGC CY7C1338F-117AI CY7C1338F-117BGI 100 CY7C1338F-100AC CY7C1338F-100BGC CY7C1338F-100AI CY7C1338F-100BGI 66 CY7C1338F-66AC CY7C1338F-66BGC CY7C1338F-66AI CY7C1338F-66BGI Package Name A101 BG119 A101 BG119 A101 BG119 A101 BG119 A101 BG119 A101 BG119 A101 BG119 A101 BG119 Package Type 100-Lead Thin Quad Flat Pack ( 14 x 20 x 1.4mm ) 119-Ball PBGA ( 14 x 22 x 2.4mm ) 100-Lead Thin Quad Flat Pack ( 14 x 20 x 1.4mm ) 119-Ball PBGA ( 14 x 22 x 2.4mm ) 100-Lead Thin Quad Flat Pack ( 14 x 20 x 1.4mm ) 119-Ball PBGA ( 14 x 22 x 2.4mm ) 100-Lead Thin Quad Flat Pack ( 14 x 20 x 1.4mm ) 119-Ball PBGA ( 14 x 22 x 2.4mm ) 100-Lead Thin Quad Flat Pack ( 14 x 20 x 1.4mm ) 119-Ball PBGA ( 14 x 22 x 2.4mm ) 100-Lead Thin Quad Flat Pack ( 14 x 20 x 1.4mm ) 119-Ball PBGA ( 14 x 22 x 2.4mm ) 100-Lead Thin Quad Flat Pack ( 14 x 20 x 1.4mm ) 119-Ball PBGA ( 14 x 22 x 2.4mm ) 100-Lead Thin Quad Flat Pack ( 14 x 20 x 1.4mm ) 119-Ball PBGA ( 14 x 22 x 2.4mm ) Industrial Commercial Industrial Commercial Industrial Commercial Industrial Operating Range Commercial Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts. Notes: 21. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device. 22. DQs are in high-Z when exiting ZZ sleep mode. Document #: 38-05218 Rev. *A Page 14 of 17 CY7C1338F Package Diagrams 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101 16.00±0.20 14.00±0.10 100 1 81 80 DIMENSIONS ARE IN MILLIMETERS. 1.40±0.05 0.30±0.08 22.00±0.20 20.00±0.10 0.65 TYP. 30 31 50 51 12°±1° (8X) SEE DETAIL A 0.20 MAX. 1.60 MAX. STAND-OFF 0.05 MIN. 0.15 MAX. 0.10 R 0.08 MIN. 0.20 MAX. 0° MIN. 0.25 GAUGE PLANE R 0.08 MIN. 0.20 MAX. SEATING PLANE 0°-7° 0.60±0.15 0.20 MIN. 1.00 REF. DETAIL A 51-85050-*A Document #: 38-05218 Rev. *A Page 15 of 17 CY7C1338F Package Diagrams (continued) 119-Lead PBGA (14 x 22 x 2.4 mm) BG119 51-85115-*B Intel and Pentium are registered trademarks of Intel Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05218 Rev. *A Page 16 of 17 CY7C1338F Document History Page Document Title: CY7C1338B 4-Mb (128K x 32) Flow-Through Sync SRAM Document Number: 38-05218 REV. ** *A ECN NO. 119832 200663 Issue Date 12/11/02 12/19/03 Orig. of Change HGK SWI New Data Sheet Final Data Sheet Description of Change Document #: 38-05218 Rev. *A Page 17 of 17