CY7C1342-35JI

CY7C135 CY7C1342 4K x 8 Dual-Port Static RAM and 4K x 8 Dual-Port SRAM with Semaphores Features • True Dual-Ported memory cells which allow simultaneous reads of the same memory location • 4K x 8 organization • 0.65-micron CMOS for optimum speed/power • High-speed access: 15 ns • Low operating power: ICC = 160 mA (max.) • Fully asynchronous operation • Automatic power-down • Semaphores included on the 7C1342 to permit software handshaking between ports • Available in 52-pin PLCC • Pb-Free packages available Functional Description The CY7C135 and CY7C1342 are high-speed CMOS 4K x 8 dual-port static RAMs. The CY7C1342 includes semaphores that provide a means to allocate portions of the dual-port RAM or any shared resource. Two ports are provided permitting independent, asynchronous access for reads and writes to any location in memory. Application areas include interprocessor/multiprocessor designs, communications status buffering, and dual-port video/graphics memory. Each port has independent control pins: chip enable (CE), read or write enable (R/W), and output enable (OE). The CY7C135 is suited for those systems that do not require on-chip arbitration or are intolerant of wait states. Therefore, the user must be aware that simultaneous access to a location is possible. Semaphores are offered on the CY7C1342 to assist in arbitrating between ports. The semaphore logic is comprised of eight shared latches. Only one side can control the latch (semaphore) at any time. Control of a semaphore indicates that a shared resource is in use. An automatic power-down feature is controlled independently on each port by a chip enable (CE) pin or SEM pin (CY7C1342 only). The CY7C135 and CY7C1342 are available in 52-pin PLCC. Logic Block Diagram R/WL CEL OEL R/WR CER OER I/O7L I/O0L I/O CONTROL I/O CONTROL I/O7R I/O0R A11L A0L ADDRESS DECODER MEMORY ARRAY ADDRESS DECODER A11R A0R CEL OEL R/WL SEMAPHORE ARBITRATION (7C1342 only) CER OER R/WR (7C1342 only) SEMR (7C1342 only) SEML Cypress Semiconductor Corporation Document #: 38-06038 Rev. *C • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised September 6, 2005 CY7C135 CY7C1342 Selection Guide Maximum Access Time Maximum Operating Current Maximum Standby Current for ISB1 7C135-15 7C1342-15 15 220 60 7C135-20 7C1342-20 20 190 50 7C135-25 7C1342-25 25 180 40 7C135-35 7C1342-35 35 160 30 7C135-55 7C1342-55 55 160 30 Unit ns mA mA Commercial Commercial Pin Configurations PLCC Top View CER R/W R N/C A11R A10R OER A0R A1R A2R A3R A4R A5R A6R A7R A8R A9R NC I/O7R SEMR A11R A10R OER A0R A1R A2R A3R A4R A5R A6R A7R A8R A9R NC I/O7R A 11L N/C R/W L CEL VCC A0L OEL A 10L A1L A2L A3L A4L A5L A6L A7L A8L A9L I/O0L I/O1L I/O2L I/O3L 8 9 10 11 12 13 14 15 16 17 18 19 20 A1L A2L A3L A4L A5L A6L A7L A8L A9L I/O0L I/O1L I/O2L I/O3L 8 9 10 11 12 13 14 15 16 17 18 19 20 7 6 5 4 3 2 1 52 51 50 49 48 47 46 45 44 43 42 41 7C135 40 39 38 37 36 35 34 21 22 23 24 25 26 27 28 29 30 31 32 33 NC GND I/O0R I/O1R I/O2R I/O3R I/O4R I/O5R I/O6R I/O4L I/O5L I/O6L I/O7L A0L OEL A 10L A 11L PLCC Top View SEM L R/W L CEL VCC CER R/W R 7 6 5 4 3 2 1 52 51 50 49 48 47 46 45 44 43 42 41 7C1342 40 39 38 37 36 35 34 21 22 23 24 25 26 27 28 29 30 31 32 33 NC GND I/O0R I/O1R I/O2R I/O3R I/O4R I/O5R I/O6R Pin Definitions Left Port A0L–11L CEL OEL R/WL Right Port A0R–11R CER OER R/WR Address Lines Chip Enable Output Enable Read/Write Enable Description SEMR Semaphore Enable. When asserted LOW, allows access to eight semaphores. The three SEML (CY7C1342 only) (CY7C1342 only) least significant bits of the address lines will determine which semaphore to write or read. The I/O0 pin is used when writing to a semaphore. Semaphores are requested by writing a 0 into the respective location. Document #: 38-06038 Rev. *C Page 2 of 12 I/O4L I/O5L I/O6L I/O7L CY7C135 CY7C1342 Maximum Ratings[1] Storage Temperature ..................................–65°C to+150°C Ambient Temperature with Power Applied..............................................–55°C to+125°C Supply Voltage to Ground Potential (Pin 48 to Pin 24) ............................................ –0.5V to+7.0V DC Voltage Applied to Outputs in High Z State ................................................ –0.5V to+7.0V DC Input Voltage[2] ......................................... –3.0V to +7.0V Static Discharge Voltage........................................... > 2001V (per MIL-STD-883, Method 3015) Latch-Up Current .................................................... > 200 mA Operating Range Range Commercial Industrial Ambient Temperature 0°C to +70°C –40°C to +85°C VCC 5V ± 10% 5V ± 10% Electrical Characteristics Over the Operating Range 7C135-15 7C1342-15 Parameter VOH VOL VIH VIL IIX IOZ ICC ISB1 ISB2 ISB3 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current Output Leakage Current Operating Current Standby Current (Both Ports TTL Levels) Standby Current (One Port TTL Level) GND ≤ VI ≤ VCC Outputs Disabled, GND ≤ VO ≤ VCC VCC = Max., IOUT = 0 mA CEL and CER ≥ VIH, f = fMAX[3] CEL and CER ≥ VIH, f = fMAX[3] Com’l Ind. Com’l Ind. Com’l Ind. Com’l Ind. Com’l Ind. 125 115 15 15 130 120 60 50 –10 –10 Test Conditions VCC = Min., IOH = –4.0 mA VCC = Min., IOL = 4.0 mA 2.2 0.8 +10 +10 220 –10 –10 2.4 0.4 2.2 0.8 +10 +10 190 –10 –10 7C135-20 7C1342-20 2.4 0.4 2.2 0.8 +10 +10 180 190 40 50 110 120 15 30 100 115 mA mA mA mA 7C135-25 7C1342-25 2.4 0.4 V V V V µA µA mA Min. Max. Min. Max. Min. Max. Unit Standby Current Both Ports CE and CER ≥ (Both Ports CMOS Levels) VCC – 0.2V, VIN ≥ VCC – 0.2V or VIN ≤ 0.2V, f = 0[3] Standby Current (One Port CMOS Level) One Port CEL or CER ≥ VCC – 0.2V, VIN ≥VCC – 0.2V or VIN ≤ 0.2V, Active Port Outputs, f = fMAX[3] ISB4 Notes: 1. The Voltage on any input or I/O pin cannot exceed the power pin during power-up. 2. Pulse width < 20 ns. 3. fMAX = 1/tRC = All inputs cycling at f = 1/tRC (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level standby ISB3. Document #: 38-06038 Rev. *C Page 3 of 12 CY7C135 CY7C1342 Electrical Characteristics Over the Operating Range (continued) 7C135-35 7C1342-35 Parameter VOH VOL VIH VIL IIX IOZ ICC ISB1 ISB2 ISB3 Input LOW Voltage Input Load Current Output Leakage Current Operating Current Standby Current (Both Ports TTL Levels) Standby Current (One Port TTL Level) GND ≤ VI ≤ VCC Outputs Disabled, GND ≤ VO ≤ VCC VCC = Max., IOUT = 0 mA VCC = Max., IOUT = 0 mA CEL and CER ≥ VIH, f = fMAX[3] Com’l Ind. Com’l Ind. CEL and CER ≥ VIH, f = fMAX[3] Com’l Ind. Com’l Ind. Com’l Ind. –10 –10 Description Output HIGH Voltage Output LOW Voltage Test Conditions VCC = Min., IOH = –4.0 mA VCC = Min., IOL = 4.0 mA 2.2 0.8 +10 +10 160 180 30 40 100 110 15 30 90 100 –10 –10 Min. 2.4 0.4 2.2 0.8 +10 +10 160 180 30 40 100 110 15 30 90 100 mA mA mA mA Max. 7C135-55 7C1342-55 Min. 2.4 0.4 Max. Unit V V V V µA µA mA Standby Current Both Ports CE and CER ≥ VCC – 0.2V, (Both Ports CMOS Levels) VIN ≥ VCC – 0.2V or VIN ≤ 0.2V, f = 0[3] Standby Current (One Port CMOS Level) One Port CEL or CER ≥ VCC – 0.2V, VIN ≥ VCC – 0.2V or VIN ≤ 0.2V, Active Port Outputs, f = fMAX[3] ISB4 Capacitance[4] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V Max. 10 10 Unit pF pF AC Test Loads and Waveforms 5V R1 = 893Ω OUTPUT C = 30 pF R1 = 347Ω OUTPUT C = 30 pF VTH = 1.4V (a) Normal Load (Load 1) (b) Thévenin Equivalent (Load 1) RTH = 250Ω RTH = 250Ω OUTPUT C = 5 pF VX (c) Three-State Delay (Load 3) ALL INPUT PULSES 3.0V GND 10% 90% 90% 10% ≤ 3 ns ≤ 3 ns Note: 4. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-06038 Rev. *C Page 4 of 12 CY7C135 CY7C1342 Switching Characteristics Over the Operating Range[5] 7C135-15 7C1342-15 Parameter READ CYCLE tRC tAA tOHA tACE tDOE tLZOE[6,7,8] tHZOE[6,7,8] tLZCE[6,7,8] tHZCE[6,7,8] tPU[8] tPD[8] tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE[7,8] tLZWE[7,8] tWDD[9] tDDD[9] Read Cycle Time Address to Data Valid Output Hold From Address Change CE LOW to Data Valid OE LOW to Data Valid OE Low to Low Z OE HIGH to High Z CE LOW to Low Z CE HIGH to High Z CE LOW to Power Up CE HIGH to Power Down Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start Write Pulse Width Data Set-Up to Write End Data Hold from Write End R/W LOW to High Z R/W HIGH to Low Z Write Pulse to Data Delay Write Data Valid to Read Data Valid SEM Flag Update Pulse (OE or SEM) SEM Flag Write to Read Time SEM Flag Contention Window 10 5 5 3 30 25 15 12 12 2 0 12 10 0 10 3 40 30 0 15 20 15 15 2 0 15 13 0 13 3 50 30 3 10 0 20 25 20 20 2 0 20 15 0 15 3 60 35 3 10 3 13 0 25 35 30 30 2 0 25 15 0 20 3 70 40 3 15 10 3 13 3 15 0 35 55 50 50 2 0 50 25 0 25 15 15 3 20 13 3 15 3 20 0 55 20 20 3 25 15 3 20 3 25 25 25 3 35 20 3 25 35 35 3 55 25 55 55 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description Min. Max. 7C135-20 7C1342-20 Min. Max. 7C135-25 7C1342-25 Min. Max. 7C135-35 7C1342-35 Min. Max. 7C135-55 7C1342-55 Min. Max. Unit WRITE CYCLE SEMAPHORE TIMING[10] tSOP tSWRD tSPS 10 5 5 10 5 5 15 5 5 15 5 5 ns ns ns Notes: 5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 6. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE. 7. Test conditions used are Load 3. 8. This parameter is guaranteed but not tested. 9. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Port-to-Port Delay waveform. 10. Semaphore timing applies only to CY7C1342. Document #: 38-06038 Rev. *C Page 5 of 12 CY7C135 CY7C1342 Switching Waveforms Read Cycle No. 1[11,12] Either Port Address Access tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID Read Cycle No. 2[11,13] Either Port CE/OE Access SEM [10] or CE OE tLZOE tLZCE tACE tDOE tHZOE tHZCE DATA OUT tPU ICC ISB DATA VALID tPD Read Timing with Port-to-Port[14] twc ADDRESSR R/WR MATCH t PWE t SD t HD DATAINR VALID ADDRESSL MATCH tDDD DATAOUTL tWDD Notes: 11. R/W is HIGH for read cycle. 12. Device is continuously selected, CE = VIL and OE = VIL. 13. Address valid prior to or coincident with CE transition LOW. 14. CEL = CER =LOW; R/WL = HIGH VALID Document #: 38-06038 Rev. *C Page 6 of 12 CY7C135 CY7C1342 Switching Waveforms (continued) Write Cycle No. 1: OE Three-States Data I/Os (Either Port)[15, 16, 17] tWC ADDRESS SEM OR CE [10] tSCE tAW tHA tPWE R/W tSA DATAIN tSD DATA VALID tHD OE tHZOE DATAOUT HIGH IMPEDANCE t LZOE Write Cycle No. 2:R/W Three-States Data I/Os (Either Port)[16, 18] tWC ADDRESS tSCE SEM OR CE R/W [10] tHA tSA tAW tPWE tSD DATAIN tHZWE DATAOUT DATA VALID tLZWE HIGH IMPEDANCE tHD Notes: 15. The internal write time of the memory is defined by the overlap of CE or SEM LOW and R/W LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 16. R/W must be HIGH during all address transactions. 17. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or (tHZWE + tSD) to allow the I/O drivers to turn off and data to be placed on the bus for the required tSD. If OE is HIGH during a R/W controlled write cycle (as in this example), this requirement does not apply and the write pulse can be as short as the specified tPWE. 18. Data I/O pins enter high-impedance when OE is held LOW during write. Document #: 38-06038 Rev. *C Page 7 of 12 CY7C135 CY7C1342 Switching Waveforms (continued) Semaphore Read After Write Timing, Either Side (CY7C1342 only)[19] tAA A0–A2 VALID ADDRESS tAW SEM tSCE tHA tSOP VALID ADDRESS tACE tOHA tSD I/O0 DATAINVALID tSA R/W tSWRD OE WRITE CYCLE tSOP READ CYCLE tDOE tPWE tHD DATAOUT VALID Timing Diagram of Semaphore Contention (CY7C1342 only)[20, 21, 22] A0L–A2L MATCH R/WL SEML tSPS A0R–A2R MATCH R/WR SEMR Notes: 19. CE = HIGH for the duration of the above timing (both write and read cycle). 20. I/O0R = I/O0L = LOW (request semaphore); CER = CEL = HIGH. 21. Semaphores are reset (available to both ports) at cycle start. 22. If tSPS is violated, it is guaranteed that only one side will gain access to the semaphore. Document #: 38-06038 Rev. *C Page 8 of 12 CY7C135 CY7C1342 Architecture The CY7C135 consists of an array of 4K words of 8 bits each of dual-port RAM cells, I/O and address lines, and control signals (CE, OE, R/W). Two semaphore control pins exist for the CY7C1342 (SEML/R). zero (the left port in this case). If the left port now relinquishes control by writing a one to the semaphore, the semaphore will be set to one for both sides. However, if the right port had requested the semaphore (written a zero) while the left port had control, the right port would immediately own the semaphore. Table 2 shows sample semaphore operations. When reading a semaphore, all eight data lines output the semaphore value. The read value is latched in an output register to prevent the semaphore from changing state during a write from the other port. If both ports request a semaphore control by writing a 0 to a semaphore within tSPS of each other, it is guaranteed that only one side will gain access to the semaphore. Initialization of the semaphore is not automatic and must be reset during initialization program at power-up. All semaphores on both sides should have a one written into them at initialization from both sides to assure that they will be free when needed. Table 1. Non-Contending Read/Write Inputs CE H H X H L L L R/W X H X L H L X OE X L H X L X X SEM H L X L H H L I/O0-7 I/O0-7 Left Right 1 0 0 1 1 0 1 1 1 0 1 1 1 1 0 0 1 1 0 1 1 1 Outputs I/O0 – I/O7 High Z Data Out High Z Data In Data Out Data In Operation Power-Down Read Semaphore I/O Lines Disabled Write to Semaphore Read Write Illegal Condition Functional Description Write Operation Data must be set up for a duration of tSD before the rising edge of R/W in order to guarantee a valid write. Since there is no on-chip arbitration, the user must be sure that a specific location will not be accessed simultaneously by both ports or erroneous data could result. A write operation is controlled by either the OE pin (see Write Cycle No. 1 timing diagram) or the R/W pin (see Write Cycle No. 2 timing diagram). Data can be written tHZOE after the OE is deasserted or tHZWE after the falling edge of R/W. Required inputs for write operations are summarized in Table 1. If a location is being written to by one port and the opposite port attempts to read the same location, a port-to-port flowthrough delay is met before the data is valid on the output. Data will be valid on the port wishing to read the location tDDD after the data is presented on the writing port. Read Operation When reading the device, the user must assert both the OE and CE pins. Data will be available tACE after CE or tDOE after OE are asserted. If the user of the CY7C1342 wishes to access a semaphore, the SEM pin must be asserted instead of the CE pin. Required inputs for read operations are summarized in Table 1. Semaphore Operation The CY7C1342 provides eight semaphore latches which are separate from the dual port memory locations. Semaphores are used to reserve resources which are shared between the two ports. The state of the semaphore indicates that a resource is in use. For example, if the left port wants to request a given resource, it sets a latch by writing a zero to a semaphore location. The left port then verifies its success in setting the latch by reading it. After writing to the semaphore, SEM or OE must be deasserted for tSOP before attempting to read the semaphore. The semaphore value will be available tSWRD + tDOE after the rising edge of the semaphore write. If the left port was successful (reads a zero), it assumes control over the shared resource, otherwise (reads a one) it assumes the right port has control and continues to poll the semaphore. When the right side has relinquished control of the semaphore (by writing a one), the left side will succeed in gaining control of the semaphore. If the left side no longer requires the semaphore, a one is written to cancel its request. Semaphores are accessed by asserting SEM LOW. The SEM pin functions as a chip enable for the semaphore latches. CE must remain HIGH during SEM LOW. A0–2 represents the semaphore address. OE and R/W are used in the same manner as a normal memory access. When writing or reading a semaphore, the other address pins have no effect. When writing to the semaphore, only I/O0 is used. If a 0 is written to the left port of an unused semaphore, a one will appear at the same semaphore address on the right port. That semaphore can now only be modified by the side showing a Document #: 38-06038 Rev. *C Table 2. Semaphore Operation Example Function No Action Left port writes semaphore Right port writes 0 to semaphore Left port writes 1 to semaphore Left port writes 0 to semaphore Right port writes 1 to semaphore Left port writes 1 to semaphore Right port writes 0 to semaphore Right port writes 1 to semaphore Left port writes 0 to semaphore Left port writes 1 to semaphore Status Semaphore free Left port obtains semaphore Right side is denied access Right port is granted access to Semaphore No change. Left port is denied access Left port obtains semaphore No port accessing semaphore address Right port obtains semaphore No port accessing semaphore Left port obtains semaphore No port accessing semaphore Page 9 of 12 CY7C135 CY7C1342 Typical DC and AC Characteristics OUTPUT SOURCE CURRENT (mA) NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.4 NORMALIZED ICC, ISB 1.2 1.0 0.8 0.6 0.4 0.2 0.0 4.0 ICC 4.5 5.0 5.5 6.0 SUPPLY VOLTAGE (V) ISB NORMALIZED ICC, ISB 1.2 1.0 0.8 0.6 0.4 0.2 0.6 –55 25 125 AMBIENT TEMPERATURE (°C) ISB3 VCC = 5.0V VIN = 5.0V NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE ICC OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE 140 120 100 80 60 40 20 0 0 1.0 2.0 3.0 4.0 5.0 OUTPUT VOLTAGE (V) VCC = 5.0V TA = 25°C 1.10 NORMALIZED tAA NORMALIZED tAA TA = 25°C 1.2 1.1 OUTPUT SINK CURRENT (mA) NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE NORMALIZED ACCESS TIME vs. AMBIENT TEMPERATURE OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE 100 90 80 70 60 50 0.0 1.0 VCC = 5.0V TA = 25°C 2.0 3.0 4.0 5.0 1.05 1.0 VCC = 5.0V 0.9 0.8 –55 1.00 0.95 4.0 4.5 5.0 5.5 6.0 25 125 SUPPLY VOLTAGE (V) AMBIENT TEMPERATURE (°C) OUTPUT VOLTAGE (V) TYPICAL POWER-ON CURRENT vs. SUPPLY VOLTAGE 1.0 NORMALIZED tPC 20.0 TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING 1.25 NORMALIZED ICC NORMALIZED ICC vs. CYCLE TIME VCC = 5.0V TA = 25°C VIN = 5.0V 0.75 0.50 DELTA tAA (ns) 15.0 10.0 VCC = 4.5V TA = 25°C 0 200 400 600 800 1000 1.0 0.75 0.25 0.0 5.0 0 0 1.0 2.0 3.0 4.0 5.0 SUPPLY VOLTAGE (V) 0.50 10 20 30 40 50 CAPACITANCE (pF) CYCLE FREQUENCY (MHz) Document #: 38-06038 Rev. *C Page 10 of 12 CY7C135 CY7C1342 Ordering Information 4K x8 Dual-Port SRAM Speed (ns) 15 20 25 Ordering Code CY7C135–15JC CY7C135-15JXC CY7C135–20JC CY7C135–25JC CY7C135-25JXC CY7C135–25JI 35 55 CY7C135–35JC CY7C135–35JI CY7C135–55JC CY7C135–55JI 4K x8 Dual-Port SRAM with Semaphores Speed (ns) 15 20 25 35 55 Ordering Code CY7C1342–15JC CY7C1342–20JC CY7C1342–25JC CY7C1342–25JI CY7C1342–35JC CY7C1342–35JI CY7C1342–55JC CY7C1342–55JI Package Type J69 J69 J69 J69 J69 J69 J69 J69 Package Type 52-Lead Plastic Leaded Chip Carrier 52-Lead Plastic Leaded Chip Carrier 52-Lead Plastic Leaded Chip Carrier 52-Lead Plastic Leaded Chip Carrier 52-Lead Plastic Leaded Chip Carrier 52-Lead Plastic Leaded Chip Carrier 52-Lead Plastic Leaded Chip Carrier 52-Lead Plastic Leaded Chip Carrier Operating Range Commercial Commercial Commercial Industrial Commercial Industrial Commercial Industrial Package Name J69 J69 J69 J69 J69 J69 J69 J69 J69 J69 Package Type 52-Lead Plastic Leaded Chip Carrier 52-Lead Pb-Free Plastic Leaded Chip Carrier 52-Lead Plastic Leaded Chip Carrier 52-Lead Plastic Leaded Chip Carrier 52-Lead Pb-Free Plastic Leaded Chip Carrier 52-Lead Plastic Leaded Chip Carrier 52-Lead Plastic Leaded Chip Carrier 52-Lead Plastic Leaded Chip Carrier 52-Lead Plastic Leaded Chip Carrier 52-Lead Plastic Leaded Chip Carrier Industrial Commercial Industrial Commercial Industrial Commercial Commercial Operating Range Commercial Package Diagrams 52-Lead Plastic Leaded Chip Carrier J69 52-Lead Pb-Free Plastic Leaded Chip Carrier J69 51-85004-*A All products and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-06038 Rev. *C Page 11 of 12 © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY7C135 CY7C1342 Document History Page Document Title: CY7C135/CY7C1342 4K x 8 Dual Port Static RAM and 4K x 8 Dual Port Static RAM w/Semaphores Document Number: 38-06038 REV. ** *A *B *C ECN NO. 110181 122288 236763 393413 Issue Date 10/21/01 12/27/02 SEE ECN See ECN Orig. of Change SZV RBI YDT YIM Description of Change Change from Spec number: 38-00541 to 38-06038 Power up requirements added to Maximum Ratings Information Removed cross information from features section Added Pb-Free Logo Added Pb-Free parts to ordering information: CY7C135-15JXC, CY7C135-25JXC Document #: 38-06038 Rev. *C Page 12 of 12