CY7C1345F-100BGC

CY7C1345F 4-Mb (128K x 36) Flow-Through Sync SRAM Functional Description[1] Features • 128K × 36 common I/O • 3.3V –5% and +10% core power supply (VDD) • 2.5V or 3.3V I/O supply (VDDQ) • Fast clock-to-output times — 6.5 ns (133-MHz version) — 7.5 ns (117-MHz version) — 8.0 ns (100-MHz version) — 11.0 ns (66-MHz version) • Provide high-performance 2-1-1-1 access rate • User-selectable burst counter supporting Intel Pentium interleaved or linear burst sequences • Separate processor and controller address strobes • Synchronous self-timed write • Asynchronous output enable • Offered in JEDEC-standard 100-pin TQFP and 119-ball BGA packages • “ZZ” Sleep Mode option The CY7C1345F is a 131,072 x 36 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BW[A:D], and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin. The CY7C1345F allows either interleaved or linear burst sequences, selected by the MODE input pin. A HIGH selects an interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses can be initiated with the Processor Address Strobe (ADSP) or the cache Controller Address Strobe (ADSC) inputs. Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor (ADSP) or Address Strobe Controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin (ADV). The CY7C1345F operates from a +3.3V core power supply while all outputs may operate with either a +2.5 or +3.3V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible. Logic Block Diagram ADDRESS REGISTER A0, A1, A A[1:0] MODE BURST Q1 COUNTER AND LOGIC Q0 CLR ADV CLK ADSC ADSP DQD, DQPD DQD, DQPD BWD BYTE BYTE WRITE REGISTER WRITE REGISTER DQC, DQPC DQC, DQPC BWC BYTE BYTE WRITE REGISTER WRITE REGISTER DQB, DQPB BWB DQB, DQPB BYTE BYTE WRITE REGISTER MEMORY ARRAY SENSE AMPS OUTPUT BUFFERS DQs DQPA DQPB DQPC DQPD WRITE REGISTER DQA, DQPA BWA BWE DQA, DQPA BYTE BYTE WRITE REGISTER WRITE REGISTER INPUT REGISTERS GW ENABLE REGISTER CE1 CE2 CE3 OE ZZ SLEEP CONTROL Note: 1. For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05214 Rev. *C • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised September 24, [+] Feedback CY7C1345F Selection Guide 133 MHz 6.5 225 40 Maximum Access Time Maximum Operating Current Maximum Standby Current 117 MHz 7.5 220 40 100 MHz 8.0 205 40 66 MHz 11.0 195 40 Unit ns mA mA Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts. Pin Configurations A A 35 36 37 38 39 40 41 42 45 46 47 48 49 50 A A1 A0 NC NC VSS VDD NC NC A A A A A A A 44 34 Document #: 38-05214 Rev. *C 43 81 82 83 84 BWE GW OE ADSC ADSP ADV 85 86 87 CLK 89 88 VDD VSS 91 90 BWA CE3 93 92 BWC 96 BWB BWD 97 94 CE2 98 95 A CE1 99 A 31 VSSQ VDDQ DQD DQD DQPD 33 VSS DQD DQD VDDQ VSSQ DQD DQD DQD DQD CY7C1345F A BYTE D DQC DQC VSSQ VDDQ DQC DQC NC VDD NC A BYTE C 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 32 VDDQ VSSQ DQC DQC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 MODE A DQPC DQC DQC 100 100-Pin TQFP DQPB DQB DQB VDDQ VSSQ DQB DQB DQB DQB VSSQ VDDQ DQB DQB VSS NC BYTE B VDD ZZ DQA DQA VDDQ VSSQ DQA DQA DQA DQA BYTE A VSSQ VDDQ DQA DQA DQPA Page 2 of 17 [+] Feedback CY7C1345F Pin Configurations (continued) 119-Ball BGA 1 2 3 4 5 6 7 A VDDQ A A ADSP A A VDDQ B C NC NC CE2 A A A ADSC VDD A A CE3 A NC NC D DQC DQPC VSS NC VSS DQPB DQB E F DQC VDDQ DQC DQC VSS VSS CE1 OE VSS VSS DQB DQB DQB VDDQ G H J DQC DQC VDDQ DQC DQC VDD BWC VSS NC ADV GW VDD BWB VSS NC DQB DQB VDD DQB DQB VDDQ K DQD DQD VSS CLK VSS DQA DQA L DQD DQD BWD NC BWA DQA DQA M N VDDQ DQD DQD DQD VSS VSS BWE A1 VSS VSS DQA DQA VDDQ DQA P DQD DQPD VSS A0 VSS DQPA DQA R T NC NC A MODE A VDD NC A A A NC NC NC U VDDQ NC NC NC NC NC VDDQ ZZ Pin Descriptions Name TQFP BGA I/O Description InputAddress Inputs used to select one of the 128K address P4,N4,A2,A3, A5,A6,B3,B5, Synchronous locations. Sampled at the rising edge of the CLK if ADSP or ADSC C2,C3,C5,C6, is active LOW, and CE1, CE2, and CE3 are sampled active. A[1:0] feed R2,R6,T3,T4, the 2-bit counter. T5 A0, A1, A 37,36,32, 33,34,35, 44,45,46, 47,48,49, 50,81,82, 99,100 BWA,BWB BWC,BWD GW 93,94, 95,96 L5,G5, G3,L3 InputByte Write Select Inputs, active LOW. Qualified with BWE to Synchronous conduct byte writes to the SRAM. Sampled on the rising edge of CLK. 88 H4 InputGlobal Write Enable Input, active LOW. When asserted LOW on Synchronous the rising edge of CLK, a global write is conducted (ALL bytes are written, regardless of the values on BW[A:D] and BWE). BWE 87 M4 InputByte Write Enable Input, active LOW. Sampled on the rising edge Synchronous of CLK. This signal must be asserted LOW to conduct a byte write. CLK 89 K4 CE1 98 E4 InputChip Enable 1 Input, active LOW. Sampled on the rising edge of Synchronous CLK. Used in conjunction with CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE2 97 B2 InputChip Enable 2 Input, active HIGH. Sampled on the rising edge of Synchronous CLK. Used in conjunction with CE1 and CE3 to select/deselect the device. CE3 92 B6 InputChip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Synchronous Used in conjunction with CE1 and CE2 to select/deselect the device. Document #: 38-05214 Rev. *C Input-Clock Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst counter when ADV is asserted LOW, during a burst operation. Page 3 of 17 [+] Feedback CY7C1345F Pin Descriptions (continued) Name TQFP BGA OE 86 F4 InputOutput Enable, asynchronous input, active LOW. Controls the Asynchronous direction of the I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE is masked during the first clock of a read cycle when emerging from a deselected state. ADV 83 G4 InputAdvance Input signal, sampled on the rising edge of CLK. When Synchronous asserted, it automatically increments the address in a burst cycle. ADSP 84 A4 ADSC 85 B4 ZZ 64 T7 InputAddress Strobe from Processor, sampled on the rising edge of Synchronous CLK, active LOW. When asserted LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH InputAddress Strobe from Controller, sampled on the rising edge of Synchronous CLK, active LOW. When asserted LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. InputZZ “sleep” Input, active HIGH. When asserted HIGH places the Asynchronous device in a non-time-critical “sleep” condition with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin has an internal pull-down. DQs DQPA, DQPB DQPC, DQPD 52,53,56, 57,58,59, 62,63,68, 69,72,73, 74,75,78, 79,2,3,6, 7,8,9,12, 13,18,19, 22,23,24, 25,28,29, 51,80,1,30 I/O Description I/OBidirectional Data I/O lines. As inputs, they feed into an on-chip K6,K7,L6, Synchronous data register that is triggered by the rising edge of CLK. As outputs, L7,M6,N6, they deliver the data contained in the memory location specified by N7,P7,D7, the addresses presented during the previous clock rise of the read E6,E7,F6, cycle. The direction of the pins is controlled by OE. When OE is G6,G7,H6, H7,D1,E1, asserted LOW, the pins behave as outputs. When HIGH, DQs and E2,F2,G1, DQP[A:D] are placed in a three-state condition. G2,H1,H2, K1,K2,L1, L2,M2,N1 N2,P1,P6,D6, D2,P2 VDD 15,41, 65, 91 C4,J2,J4, R4,J6 VSS 17,40, 67,90 D3,D5,E3,E5, F3,F5,H3,H5, K3,K5,M3,M5, N3,N5,P3,P5 Ground Ground for the core of the device. VDDQ 4,11,20, 27,54,61, 70,77 A1,A7,F1,F7, J1,J7,M1,M7, U1,U7 I/O Power Supply Power supply for the I/O circuitry. VSSQ 5,10,21, 26,55,60, 71,76 – I/O Ground Ground for the I/O circuitry. 31 R3 InputStatic 14,16,38, 39,42,43, 66, B1,B7,C1,C7, D4,J3,J5,L4, R1,R5,R7,T1, T2,T6,U2,U3, U4,U5,U6 MODE NC Document #: 38-05214 Rev. *C Power Supply Power supply inputs to the core of the device. Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD or left floating selects interleaved burst sequence. This is a strap pin and should remain static during device operation. Mode Pin has an internal pull-up. No Connects. Not Internally connected to the die. Page 4 of 17 [+] Feedback CY7C1345F Functional Overview All synchronous inputs pass through input registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (t C0) is 6.5 ns (133-MHz device). The CY7C1345F supports secondary cache in systems utilizing either a linear or interleaved burst sequence. The interleaved burst order supports Pentium® and i486 processors. The linear burst sequence is suited for processors that utilize a linear burst sequence. The burst order is user-selectable, and is determined by sampling the MODE input. Accesses can be initiated with either the Processor Address Strobe (ADSP) or the Controller Address Strobe (ADSC). Address advancement through the burst sequence is controlled by the ADV input. A two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. Byte write operations are qualified with the Byte Write Enable (BWE) and Byte Write Select (BW[A:D]) inputs. A Global Write Enable (GW) overrides all byte write inputs and writes data to all four bytes. All writes are simplified with on-chip synchronous self-timed write circuitry. Three synchronous Chip Selects (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output three-state control. ADSP is ignored if CE1 is HIGH. Single Read Accesses A single read access is initiated when the following conditions are satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted active, and (2) ADSP or ADSC is asserted LOW (if the access is initiated by ADSC, the write inputs must be deasserted during this first cycle). The address presented to the address inputs is latched into the address register and the burst counter/control logic and presented to the memory core. If the OE input is asserted LOW, the requested data will be available at the data outputs a maximum to tCDV after clock rise. ADSP is ignored if CE1 is HIGH. Single Write Accesses Initiated by ADSP This access is initiated when the following conditions are satisfied at clock rise: (1) CE1, CE2, CE3 are all asserted active, and (2) ADSP is asserted LOW. The addresses presented are loaded into the address register and the burst inputs (GW, BWE, and BW[A:D] )are ignored during this first clock cycle. If the write inputs are asserted active ( see Write Cycle Descriptions table for appropriate states that indicate a write) on the next clock rise,the appropriate data will be latched and written into the device.Byte writes are allowed. During byte writes, BWA controls DQA and BWB controls DQB, BWC controls DQC, and BWD controls DQD.All I/Os are three-stated during a byte write.Since this is a common I/O device, the asynchronous OE input signal must be deasserted and the I/Os must be three-stated prior to the presentation of data to DQs. As a safety precaution, the data lines are three-stated once a write cycle is detected, regardless of the state of OE. Single Write Accesses Initiated by ADSC This write access is initiated when the following conditions are satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted active, (2) ADSC is asserted LOW, (3) ADSP is deasserted Document #: 38-05214 Rev. *C HIGH, and (4) the write input signals (GW, BWE, and BW[A:D]) indicate a write access. ADSC is ignored if ADSP is active LOW. The addresses presented are loaded into the address register and the burst counter/control logic and delivered to the memory core. The information presented to DQ[D:A] will be written into the specified address location. Byte writes are allowed. During byte writes, BWA controls DQA, BWB controls DQB, BWC controls DQC, and BWD controls DQD. All I/Os are three-stated when a write is detected, even a byte write. Since this is a common I/O device, the asynchronous OE input signal must be deasserted and the I/Os must be three-stated prior to the presentation of data to DQs. As a safety precaution, the data lines are three-stated once a write cycle is detected, regardless of the state of OE. Burst Sequences The CY7C1345F provides an on-chip two-bit wraparound burst counter inside the SRAM. The burst counter is fed by A[1:0], and can follow either a linear or interleaved burst order. The burst order is determined by the state of the MODE input. A LOW on MODE will select a linear burst sequence. A HIGH on MODE will select an interleaved burst order. Leaving MODE unconnected will cause the device to default to a interleaved burst sequence. Interleaved Burst Address Table (MODE = Floating or VDD) First Address A1, A0 Second Address A1, A0 Third Address A1, A0 Fourth Address A1, A0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 Linear Burst Address Table (MODE = GND) First Address A1, A0 Second Address A1, A0 Third Address A1, A0 Fourth Address A1, A0 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 Sleep Mode The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the “sleep” mode. CEs, ADSP, and ADSC must remain inactive for the duration of tZZREC after the ZZ input returns LOW. Page 5 of 17 [+] Feedback CY7C1345F ZZ Mode Electrical Characteristics Parameter Description Test Conditions Min. IDDZZ Snooze mode standby current ZZ > VDD – 0.2V tZZS Device operation to ZZ ZZ > VDD – 0.2V tZZREC ZZ recovery time ZZ < 0.2V tZZI ZZ Active to snooze current This parameter is sampled tRZZI ZZ Inactive to exit snooze current This parameter is sampled Max. Unit 40 mA 2tCYC ns 2tCYC ns 2tCYC ns 0 ns Truth Table[2, 3, 4, 5, 6] Cycle Description Address Used ZZ ADSP ADSC Deselected Cycle, Power-down None CE1 CE2 CE3 H X X L X L ADV WRITE X X OE X CLK L-H three-state Deselected Cycle, Power-down None L L X L L X X X X L-H three-state Deselected Cycle, Power-down None L X H L L X X X X L-H three-state Deselected Cycle, Power-down None L L X L H L X X X L-H three-state Deselected Cycle, Power-down None X X X L H L X X X L-H three-state Snooze Mode, Power-down None X X X H X X X X X Read Cycle, Begin Burst External L H L L L X X X L L-H Q Read Cycle, Begin Burst External L H L L L X X X H L-H three-state X DQ three-state Write Cycle, Begin Burst External L H L L H L X L X L-H D Read Cycle, Begin Burst External L H L L H L X H L L-H Q Read Cycle, Begin Burst External L H L L H L X H H L-H three-state Next X X X L H H L H L L-H Q Read Cycle, Continue Burst Read Cycle, Continue Burst Next X X X L H H L H H L-H three-state Read Cycle, Continue Burst Next H X X L X H L H L L-H Q Read Cycle, Continue Burst Next H X X L X H L H H L-H three-state Write Cycle, Continue Burst Next X X X L H H L L X L-H D Write Cycle, Continue Burst Next H X X L X H L L X L-H D Read Cycle, Suspend Burst Current X X X L H H H H L L-H Q Read Cycle, Suspend Burst Current X X X L H H H H H L-H three-state Read Cycle, Suspend Burst Current H X X L X H H H L L-H Q Read Cycle, Suspend Burst Current H X X L X H H H H L-H three-state Write Cycle, Suspend Burst Current X X X L H H H L X L-H D Write Cycle, Suspend Burst Current H X X L X H H L X L-H D Notes: 2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. 3. WRITE = L when any one or more Byte Write enable signals (BWA, BWB, BWC, BWD) and BWE = L or GW= L. WRITE = H when all Byte write enable signals (BWA, BWB, BWC, BWD), BWE, GW = H. 4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock. 5. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW[A: D]. Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state. OE is a don't care for the remainder of the write cycle. 6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are three-state when OE is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW). Document #: 38-05214 Rev. *C Page 6 of 17 [+] Feedback CY7C1345F Partial Truth Table for Read/Write[2, 7] Function BWE H BWD Read GW H BWC BWB BWA X X X X Read H L H H H H Write Byte (A, DQPA) H L H H H L Write Byte (B, DQPB) H L H H L H Write Bytes (B, A, DQPA, DQPB) H L H H L L Write Byte (C, DQPC) H L H L H H Write Bytes (C, A, DQPC, DQPA) H L H L H L Write Bytes (C, B, DQPC, DQPB) H L H L L H Write Bytes (C, B, A, DQPC, DQPB, DQPA) H L H L L L Write Byte (D, DQPD) H L L H H H Write Bytes (D, A, DQPD, DQPA) H L L H H L Write Bytes (D, B, DQPD, DQPA) H L L H L H Write Bytes (D, B, A, DQPD, DQPB, DQPA) H L L H L L Write Bytes (D, B, DQPD, DQPB) H L L L H H Write Bytes (D, B, A, DQPD, DQPC, DQPA) H L L L H L Write Bytes (D, C, A, DQPD, DQPB, DQPA) H L L L L H Write All Bytes H L L L L L Write All Bytes L X X X X X Note: 7. Table only lists a partial listing of the byte write combinations. Any combination of BW[A:D] is valid. Appropriate write will be done based on which byte write is active. Document #: 38-05214 Rev. *C Page 7 of 17 [+] Feedback CY7C1345F Maximum Ratings Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage........................................... >2001V (per MIL-STD-883, Method 3015) (Above which the useful life may be impaired. For user guidelines, not tested.) Latch-up Current..................................................... >200 mA Storage Temperature ................................. –65°C to +150°C Operating Range Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage on VDD Relative to GND........ –0.5V to +4.6V Range DC Voltage Applied to Outputs in three-state ....................................... –0.5V to VDDQ + 0.5V Commercial Industrial DC Input Voltage....................................–0.5V to VDD + 0.5V Electrical Characteristics Over the Operating Range Ambient Temperature] VDD VDDQ 3.3V −5%/+10% 2.5V –5% to VDD –40°C to +85°C 0°C to +70°C [8, 9] CY7C1345F Parameter Description Test Conditions Min. Max. Unit 3.135 3.6 V 2.375 VDD VDD Power Supply Voltage VDDQ I/O Supply Voltage VOH Output HIGH Voltage VOL Output LOW Voltage VIH Input HIGH Voltage VIL Input LOW Voltage[8] IX Input Load Current (except ZZ and MODE) GND ≤ VI ≤ VDDQ Input Current of MODE Input = VSS –30 VDDQ = 3.3V, VDD = Min., IOH = –4.0 mA 2.4 VDDQ = 2.5V, VDD = Min., IOH = –1.0 mA 2.0 VDDQ = 3.3V, VDD = Min., IOL = 8.0 mA 0.4 V VDD + 0.3V V VDDQ = 2.5V 1.7 VDD + 0.3V V VDDQ = 3.3V –0.3 0.8 V VDDQ = 2.5V –0.3 0.7 V −5 5 µA Input = VDD IOZ Output Leakage Current GND ≤ VI ≤ VDD, Output Disabled IOS Output Short Circuit Current VDD = Max., VOUT = GND IDD VDD Operating Supply Current VDD = Max., IOUT = 0 mA, f = fMAX= 1/tCYC 7.5-ns cycle, 133 MHz Automatic CE Power-down Current—CMOS Inputs 30 µA 5 µA –300 µA 225 mA 8.0-ns cycle, 117 MHz 220 mA 10-ns cycle, 100 MHz 205 mA 15-ns cycle, 66 MHz 195 mA 7.5-ns cycle, 133 MHz 90 mA 8.0-ns cycle, 117 MHz 85 mA 10-ns cycle, 100 MHz 80 mA 60 mA 40 mA 15-ns cycle, 66 MHz ISB2 –5 µA µA –5 Input = VDD Max. VDD, Device Deselected, VIN ≥ VIH or VIN ≤ VIL, f = fMAX, inputs switching µA 5 Input = VSS Automatic CE Power-down Current—TTL Inputs V 2.0 VDDQ = 3.3V Input Current of ZZ ISB1 V 0.4 VDDQ = 2.5V, VDD = Min., IOL = 1.0 mA V V All speeds Max. VDD, Device Deselected, VIN ≥ VDD – 0.3V or VIN ≤ 0.3V, f = 0, inputs static Shaded areas contain advance information. Notes: 8. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC) > -2V (Pulse width less than tCYC/2). 9. TPower-up: Assumes a linear ramp from 0v to VDD(min.) within 200ms. During this time VIH < VDD and VDDQ < VDD. Document #: 38-05214 Rev. *C Page 8 of 17 [+] Feedback CY7C1345F Electrical Characteristics Over the Operating Range (continued) [8, 9] CY7C1345F Parameter Description Test Conditions Automatic CE Power-down Current—CMOS Inputs ISB3 Min. Max. VDD, Device Deselected, 7.5-ns cycle, 133 MHz VIN ≥ VDDQ – 0.3V or VIN ≤ 0.3V, 8.0-ns cycle, 117 MHz f = fMAX, inputs switching 10-ns cycle, 100 MHz 15-ns cycle, 66 MHz ISB4 Automatic CE Power-down Current—TTL Inputs Max. VDD, Device Deselected, All speeds VIN ≥ VDD – 0.3V or VIN ≤ 0.3V, f = 0, inputs static Max. Unit 75 mA 70 mA 65 mA 45 mA 45 mA Thermal Resistance[10] Parameter Description ΘJA Thermal Resistance (Junction to Ambient) ΘJC Thermal Resistance (Junction to Case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA / JESD51. TQFP Package BGA Package Unit 41.83 47.63 °C/W 9.99 11.71 °C/W Capacitance[10] Parameter Description CIN Input Capacitance CCLK Clock Input Capacitance CI/O Input/Output Capacitance Test Conditions TQFP Package BGA Package Unit 5 5 pF 5 5 pF 5 7 pF TA = 25°C, f = 1 MHz, VDD = 3.3V. VDDQ = 3.3V AC Test Loads and Waveforms 3.3V I/O Test Load R = 317Ω 3.3V OUTPUT OUTPUT RL = 50Ω Z0 = 50Ω GND 5 pF R = 351Ω INCLUDING JIG AND SCOPE 10% 90% 10% 90% ≤ 1ns ≤ 1ns VL = 1.5V (a) ALL INPUT PULSES VDD (c) (b) 2.5V I/O Test Load R = 1667Ω 2.5V OUTPUT OUTPUT RL = 50Ω Z0 = 50Ω VL = 1.25V (a) ALL INPUT PULSES VDD GND 5 pF INCLUDING JIG AND SCOPE R =1538Ω (b) 10% 90% 10% 90% ≤ 1ns ≤ 1ns (c) Note: 10. Tested initially and after any design or process change that may affect these parameters. Document #: 38-05214 Rev. *C Page 9 of 17 [+] Feedback CY7C1345F Switching Characteristics Over the Operating Range [15, 16] 133 MHz Parameter tPOWER Description VDD(Typical) to the first Access 117 MHz 100 MHz 66 MHz Min. Max. Min. Max. Min. Max. Min. Max. [11] 1 1 1 Unit 1 ms Clock tCYC Clock Cycle Time 7.5 8.5 10 15 ns tCH Clock HIGH 2.5 3.0 4.0 5.0 ns tCL Clock LOW 2.5 3.0 4.0 5.0 ns Output Times tCDV Data Output Valid After CLK Rise tDOH Data Output Hold After CLK Rise 2.0 tCLZ Clock to Low-Z[12, 13, 14] 0 tCHZ Clock to High-Z[12, 13, 14] tOEV OE LOW to Output Valid tOELZ OE LOW to Output Low-Z[12, 13, 14] tOEHZ OE HIGH to Output 6.5 7.5 2.0 0 3.5 High-Z[12, 13, 14] 3.5 3.5 0 3.5 ns 5.0 ns 6.0 ns 0 3.5 ns ns 0 3.5 3.5 0 11.0 2.0 0 3.5 3.5 0 8.0 2.0 ns 6.0 ns Setup Times tAS Address Set-up Before CLK Rise 1.5 2.0 2.0 2.0 ns tADS ADSP, ADSC Set-up Before CLK Rise 1.5 2.0 2.0 2.0 ns tADVS ADV Set-up Before CLK Rise 1.5 2.0 2.0 2.0 ns tWES 1.5 2.0 2.0 2.0 ns tDS GW, BWE, BW[A:D] Set-up Before CLK Rise Data Input Set-up Before CLK Rise 1.5 2.0 2.0 2.0 ns tCES Chip Enable Set-up 1.5 2.0 2.0 2.0 ns tAH Address Hold After CLK Rise 0.5 0.5 0.5 0.5 ns tADH ADSP, ADSC Hold After CLK Rise GW,BWE, BW[A:D] Hold After CLK Rise 0.5 0.5 0.5 0.5 ns tWEH 0.5 0.5 0.5 0.5 ns tADVH ADV Hold After CLK Rise 0.5 0.5 0.5 0.5 ns tDH Data Input Hold After CLK Rise 0.5 0.5 0.5 0.5 ns tCEH Chip Enable Hold After CLK Rise 0.5 0.5 0.5 0.5 ns Hold Times Shaded areas contain advance information. Notes: 11. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a read or write operation can be initiated. 12. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage. 13. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z prior to Low-Z under the same system conditions. 14. This parameter is sampled and not 100% tested. 15. Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V. 16. Test conditions shown in (a) of AC Test Loads unless otherwise noted. Document #: 38-05214 Rev. *C Page 10 of 17 [+] Feedback CY7C1345F Timing Diagrams Read Cycle Timing[17] tCYC CLK t tADS t CL CH tADH ADSP tADS tADH ADSC tAS tAH A1 ADDRESS A2 t WES t WEH GW, BWE,BW [A:D] tCES Deselect Cycle t CEH CE t ADVS t ADVH ADV ADV suspends burst. OE t OEV t OEHZ t CLZ Data Out (Q) High-Z Q(A1) t OELZ tCDV t CHZ tDOH Q(A2) Q(A2 + 1) Q(A2 + 2) t CDV Q(A2 + 3) Q(A2) Q(A2 + 1) Q(A2 + 2) Burst wraps around to its initial state Single READ BURST READ DON’T CARE UNDEFINED Note: 17. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH. Document #: 38-05214 Rev. *C Page 11 of 17 [+] Feedback CY7C1345F Timing Diagrams (continued) Write Cycle Timing[17, 18] t CYC CLK t tADS t CH CL tADH ADSP tADS ADSC extends burst tADH tADS tADH ADSC tAS tAH A1 ADDRESS A2 A3 Byte write signals are ignored for first cycle when ADSP initiates burst tWES tWEH BWE, BWX t t WES WEH GW tCES tCEH CE tADVS tADVH ADV ADV suspends burst OE t Data in (D) High-Z t OEHZ t DS DH D(A1) D(A2) D(A2 + 1) D(A2 + 1) D(A2 + 2) D(A2 + 3) D(A3) D(A3 + 1) D(A3 + 2) Data Out (Q) BURST READ Single WRITE BURST WRITE Extended BURST WRITE Note: DON’T CARE UNDEFINED 18. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW[A:D] LOW. Document #: 38-05214 Rev. *C Page 12 of 17 [+] Feedback CY7C1345F Timing Diagrams (continued) Read/Write Timing[17, 19, 20] CLK t CH tADS tADH tAS tAH t CL ADSP ADSC ADDRESS A1 A2 A3 A4 A5 A6 D(A5) D(A6) t t WES WEH BWE, BWX tCES tCEH CE ADV OE tDS Data In (D) Data Out (Q) High-Z t OEHZ Q(A1) tDH D(A3) tCDV Q(A2) Back-to-Back READs tOELZ Q(A4) Single WRITE Q(A4+1) Q(A4+2) BURST READ Q(A4+3) Back-to-Back WRITEs Notes: 19. The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC. 20. GW is HIGH. Document #: 38-05214 Rev. *C Page 13 of 17 [+] Feedback CY7C1345F Timing Diagrams (continued) ZZ Mode Timing[21, 22] CLK t ZZ ZZ I t ZZREC t ZZI SUPPLY I DDZZ t RZZI ALL INPUTS (except ZZ) DESELECT or READ Only Outputs (Q) High-Z DON’T CARE Ordering Information Speed (MHz) 133 Ordering Code CY7C1345F-133AC CY7C1345F-133BGC CY7C1345F-133AI 117 Operating Range A101 100-Lead Thin Quad Flat Pack (14 x 20 x 1.4mm) Commercial BG119 A101 BG119 CY7C1345F-117AC A101 CY7C1345F-117AI CY7C1345F-117BGI CY7C1345F-100AC CY7C1345F-100BGC CY7C1345F-100AI CY7C1345F-100BGI 66 Package Type CY7C1345F-133BGI CY7C1345F-117BGC 100 Package Name CY7C1345F-66AC CY7C1345F-66BGC CY7C1345F-66AI CY7C1345F-66BGI BG119 A101 BG119 A101 BG119 A101 BG119 A101 BG119 A101 BG119 119-Ball PBGA (14 x 22 x 2.4mm) 100-Lead Thin Quad Flat Pack (14 x 20 x 1.4mm) Industrial 119-Ball PBGA (14 x 22 x 2.4mm) 100-Lead Thin Quad Flat Pack (14 x 20 x 1.4mm) Commercial 119-Ball PBGA (14 x 22 x 2.4mm) 100-Lead Thin Quad Flat Pack (14 x 20 x 1.4mm) Industrial 119-Ball PBGA (14 x 22 x 2.4mm) 100-Lead Thin Quad Flat Pack (14 x 20 x 1.4mm) Commercial 119-Ball PBGA (14 x 22 x 2.4mm) 100-Lead Thin Quad Flat Pack (14 x 20 x 1.4mm) Industrial 119-Ball PBGA (14 x 22 x 2.4mm) 100-Lead Thin Quad Flat Pack (14 x 20 x 1.4mm) Commercial 119-Ball PBGA (14 x 22 x 2.4mm) 100-Lead Thin Quad Flat Pack (14 x 20 x 1.4mm) Industrial 119-Ball PBGA (14 x 22 x 2.4mm) Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts. Notes: 21. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device. 22. DQs are in high-Z when exiting ZZ sleep mode. Document #: 38-05214 Rev. *C Page 14 of 17 [+] Feedback CY7C1345F Package Diagrams 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101 51-85050-*A Document #: 38-05214 Rev. *C Page 15 of 17 [+] Feedback CY7C1345F Package Diagrams (continued) 119-Lead BGA (14 x 22 x 2.4 mm) BG119 51-85115-*B Intel and Pentium are registered trademarks of Intel Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05214 Rev. *C Page 16 of 17 © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback CY7C1345F Document History Page Document Title: CY7C1345F 4-Mb (128K x 36) Flow-Through Sync SRAM Document Number: 38-05214 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 119831 12/11/02 HGK New data sheet *A 123118 01/18/03 RBI Added power-up requirements to AC test loads and waveforms information *B 200663 12/19/03 REF Final data sheet *C 280230 See ECN NJY Corrected the timing diagrams for Write Cycle and Read/Write Cycle Timing on page 12 and 13 of the data sheet Corrected typo in the part number in the Document Title on page 17 from CY7C1345B to CY7C1345F Document #: 38-05214 Rev. *C Page 17 of 17 [+] Feedback