CY7C1345G-133BGC

PRELIMINARY CY7C1345G 4-Mbit (128K x 36) Flow-Through Sync SRAM Features • 128K X 36 common I/O • 3.3V –5% and +10% core power supply (VDD) • 2.5V or 3.3V I/O supply (VDDQ) • Fast clock-to-output times — 6.5 ns (133-MHz version) — 7.5 ns (117-MHz version) — 8.0 ns (100-MHz version) • Provide high-performance 2-1-1-1 access rate • User-selectable burst counter supporting Intel® Pentium® interleaved or linear burst sequences • Separate processor and controller address strobes • Synchronous self-timed write • Asynchronous output enable • Lead-Free 100-pin TQFP and 119-ball BGA packages • “ZZ” Sleep Mode option Functional Description[1] The CY7C1345G is a 131,072 x 36 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BWx, and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin. The CY7C1345G allows either interleaved or linear burst sequences, selected by the MODE input pin. A HIGH selects an interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses can be initiated with the Processor Address Strobe (ADSP) or the cache Controller Address Strobe (ADSC) inputs. Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor (ADSP) or Address Strobe Controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin (ADV). The CY7C1345G operates from a +3.3V core power supply while all outputs may operate with either a +2.5 or +3.3V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible. Logic Block Diagram A0, A1, A ADDRESS REGISTER A[1:0] MODE ADV CLK BURST Q1 COUNTER AND LOGIC Q0 CLR ADSC ADSP DQD, DQPD BWD BYTE WRITE REGISTER DQC, DQPC BYTE WRITE REGISTER DQB, DQPB BYTE WRITE REGISTER DQA, DQPA BWA BWE GW CE1 CE2 CE3 OE DQA, DQPA BYTE WRITE REGISTER BYTE WRITE REGISTER DQD, DQPD BYTE WRITE REGISTER DQC, DQPC BYTE WRITE REGISTER DQB, DQPB BWB BYTE WRITE REGISTER BWC MEMORY ARRAY SENSE AMPS OUTPUT BUFFERS DQs DQPA DQPB DQPC DQPD ENABLE REGISTER INPUT REGISTERS ZZ SLEEP CONTROL Note: 1. For best–practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05517 Rev. *A • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised October 21, 2004 PRELIMINARY Selection Guide Maximum Access Time Maximum Operating Current Maximum Standby Current 133 MHz 6.5 225 40 117 MHz 7.5 220 40 100 MHz 8.0 205 40 CY7C1345G Unit ns mA mA Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts. Pin Configurations 100-Pin TQFP BWD BWC BWB BWA CE3 CE1 VDD VSS OE ADSC ADSP ADV 86 85 84 83 CE2 CLK GW BWE A A 82 A 99 98 97 96 95 94 93 92 91 90 89 88 87 DQPC DQC DQC VDDQ VSSQ DQC DQC BYTE C DQC DQC VSSQ VDDQ DQC DQC NC VDD NC VSS DQD DQD VDDQ VSSQ DQD DQD DQD DQD VSSQ VDDQ DQD DQD DQPD BYTE D 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 100 81 A CY7C1345G 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 44 45 46 47 48 49 50 DQPB DQB DQB VDDQ VSSQ DQB DQB DQB DQB VSSQ VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSSQ DQA DQA DQA DQA VSSQ VDDQ DQA DQA DQPA BYTE B BYTE A 38 39 40 41 VDD 42 MODE A VSS NC NC A A NC NC A1 A0 A A A 43 A A A A Document #: 38-05517 Rev. *A A Page 2 of 17 PRELIMINARY Pin Configurations (continued) 119-Ball BGA 1 A B C D E F G H J K L M N P R T U VDDQ NC NC DQC DQC VDDQ DQC DQC VDDQ DQD DQD VDDQ DQD DQD NC NC VDDQ 2 A CE2 A DQPC DQC DQC DQC DQC VDD DQD DQD DQD DQD DQPD A NC NC 3 A A A VSS VSS VSS BWC VSS NC VSS BWD VSS VSS VSS MODE A NC 4 ADSP ADSC VDD NC CE1 OE ADV GW VDD CLK NC BWE A1 A0 VDD A NC 5 A A A VSS VSS VSS BWB VSS NC VSS BWA VSS VSS VSS NC A NC 6 A CE3 A DQPB DQB DQB DQB DQB VDD DQA DQA DQA DQA DQPA A NC NC 7 VDDQ NC NC DQB DQB VDDQ DQB DQB VDDQ DQA DQA VDDQ DQA DQA NC ZZ VDDQ CY7C1345G Pin Definitions Name A0, A1, A I/O Description InputAddress Inputs used to select one of the 128K address locations. Sampled at the rising edge Synchronous of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A[1:0] feed the 2-bit counter. InputByte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM. Synchronous Sampled on the rising edge of CLK. InputGlobal Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global Synchronous write is conducted (ALL bytes are written, regardless of the values on BW[A:D] and BWE). InputByte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be Synchronous asserted LOW to conduct a byte write. Input-Clock Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst counter when ADV is asserted LOW, during a burst operation. BWA,BWB BWC,BWD GW BWE CLK CE1 CE2 CE3 OE InputChip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with Synchronous CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only when a new external address is loaded. InputChip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with Synchronous CE1 and CE3 to select/deselect the device.CE2 is sampled only when a new external address is loaded. InputChip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 Synchronous and CE2 to select/deselect the device. CE3 is sampled only when a new external address is loaded. InputOutput Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When Asynchronous LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked during the first clock of a read cycle when emerging from a deselected state. InputAdvance Input signal, sampled on the rising edge of CLK. When asserted, it automatically Synchronous increments the address in a burst cycle. ADV Document #: 38-05517 Rev. *A Page 3 of 17 PRELIMINARY Pin Definitions (continued) Name ADSP I/O Description CY7C1345G ADSC ZZ InputAddress Strobe from Processor, sampled on the rising edge of CLK, active LOW. When Synchronous asserted LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH InputAddress Strobe from Controller, sampled on the rising edge of CLK, active LOW. When Synchronous asserted LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. InputZZ “sleep” Input, active HIGH. When asserted HIGH places the device in a non-time-critical “sleep” Asynchronous condition with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin has an internal pull-down. I/OBidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by Synchronous the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQP[A:D] are placed in a tri-state condition. Power Supply Power supply inputs to the core of the device. Ground I/O Power Supply I/O Ground InputStatic Ground for the core of the device. Power supply for the I/O circuitry. Ground for the I/O circuitry. Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD or left floating selects interleaved burst sequence. This is a strap pin and should remain static during device operation. Mode Pin has an internal pull-up. No Connects. Not Internally connected to the die. Single Read Accesses A single read access is initiated when the following conditions are satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted active, and (2) ADSP or ADSC is asserted LOW (if the access is initiated by ADSC, the write inputs must be deasserted during this first cycle). The address presented to the address inputs is latched into the address register and the burst counter/control logic and presented to the memory core. If the OE input is asserted LOW, the requested data will be available at the data outputs a maximum to tCDV after clock rise. ADSP is ignored if CE1 is HIGH. Single Write Accesses Initiated by ADSP This access is initiated when the following conditions are satisfied at clock rise: (1) CE1, CE2, CE3 are all asserted active, and (2) ADSP is asserted LOW. The addresses presented are loaded into the address register and the burst inputs (GW, BWE, and BWx )are ignored during this first clock cycle. If the write inputs are asserted active ( see Write Cycle Descriptions table for appropriate states that indicate a write) on the next clock rise,the appropriate data will be latched and written into the device.Byte writes are allowed. During byte writes, BWA controls DQA and BWB controls DQB, BWC controls DQC, and BWD controls DQD.All I/Os are tri-stated during a byte write.Since this is a common I/O device, the asynchronous OE input signal must be deasserted and the I/Os must be tri-stated prior to the presentation of data to DQs. As a safety precaution, the data lines are tri-stated once a write cycle is detected, regardless of the state of OE. DQs DQPA, DQPB DQPC, DQPD VDD VSS VDDQ VSSQ MODE NC Functional Overview All synchronous inputs pass through input registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (t C0) is 6.5 ns (133-MHz device). The CY7C1345G supports secondary cache in systems utilizing either a linear or interleaved burst sequence. The interleaved burst order supports Pentium® and i486 processors. The linear burst sequence is suited for processors that utilize a linear burst sequence. The burst order is user-selectable, and is determined by sampling the MODE input. Accesses can be initiated with either the Processor Address Strobe (ADSP) or the Controller Address Strobe (ADSC). Address advancement through the burst sequence is controlled by the ADV input. A two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. Byte write operations are qualified with the Byte Write Enable (BWE) and Byte Write Select (BW[A:D]) inputs. A Global Write Enable (GW) overrides all byte write inputs and writes data to all four bytes. All writes are simplified with on-chip synchronous self-timed write circuitry. Three synchronous Chip Selects (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output tri-state control. ADSP is ignored if CE1 is HIGH. Document #: 38-05517 Rev. *A Page 4 of 17 PRELIMINARY Single Write Accesses Initiated by ADSC This write access is initiated when the following conditions are satisfied at clock rise: (1) CE1, CE2, and CE3 are all asserted active, (2) ADSC is asserted LOW, (3) ADSP is deasserted HIGH, and (4) the write input signals (GW, BWE, and BWx) indicate a write access. ADSC is ignored if ADSP is active LOW. The addresses presented are loaded into the address register and the burst counter/control logic and delivered to the memory core. The information presented to DQ[D:A] will be written into the specified address location. Byte writes are allowed. During byte writes, BWA controls DQA, BWB controls DQB, BWC controls DQC, and BWD controls DQD. All I/Os are tri-stated when a write is detected, even a byte write. Since this is a common I/O device, the asynchronous OE input signal must be deasserted and the I/Os must be tri-stated prior to the presentation of data to DQs. As a safety precaution, the data lines are tri-stated once a write cycle is detected, regardless of the state of OE. Burst Sequences The CY7C1345G provides an on-chip two-bit wraparound burst counter inside the SRAM. The burst counter is fed by A[1:0], and can follow either a linear or interleaved burst order. The burst order is determined by the state of the MODE input. A LOW on MODE will select a linear burst sequence. A HIGH on MODE will select an interleaved burst order. Leaving MODE unconnected will cause the device to default to a interleaved burst sequence. CY7C1345G Interleaved Burst Address Table (MODE = Floating or VDD) First Address A1, A0 00 01 10 11 Second Address A1, A0 01 00 11 10 Third Address A1, A0 10 11 00 01 Fourth Address A1, A0 11 10 01 00 Linear Burst Address Table (MODE = GND) First Address A1, A0 00 01 10 11 Second Address A1, A0 01 10 11 00 Third Address A1, A0 10 11 00 01 Fourth Address A1, A0 11 00 01 10 Sleep Mode The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the “sleep” mode. CEs, ADSP, and ADSC must remain inactive for the duration of tZZREC after the ZZ input returns LOW. Test Conditions ZZ > VDD – 0.2V ZZ > VDD – 0.2V ZZ < 0.2V This parameter is sampled This parameter is sampled 0 2tCYC 2tCYC Min. Max. 40 2tCYC Unit mA ns ns ns ns ZZ Mode Electrical Characteristics Parameter IDDZZ tZZS tZZREC tZZI tRZZI Description Snooze mode standby current Device operation to ZZ ZZ recovery time ZZ Active to snooze current ZZ Inactive to exit snooze current Document #: 38-05517 Rev. *A Page 5 of 17 PRELIMINARY Truth Table[2, 3, 4, 5, 6] Cycle Description Deselected Cycle, Power-down Deselected Cycle, Power-down Deselected Cycle, Power-down Deselected Cycle, Power-down Deselected Cycle, Power-down Snooze Mode, Power-down Read Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Begin Burst Read Cycle, Begin Burst Read Cycle, Begin Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Continue Burst Write Cycle, Continue Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Write Cycle, Suspend Burst Write Cycle, Suspend Burst Address Used None None None None None None External External External External External Next Next Next Next Next Next Current Current Current Current Current Current CE1 CE2 CE3 H L L L X X L L L L L X X H H X H X X H H X H X L X L X X H H H H H X X X X X X X X X X X X X X H X X X L L L L L X X X X X X X X X X X X ZZ L L L L L H L L L L L L L L L L L L L L L L L ADSP X L L H H X L L H H H H H X X H X H H X X H X ADSC L X X L L X X X L L L H H H H H H H H H H H H ADV WRITE X X X X X X X X X X X L L L L L L H H H H H H X X X X X X X X L H H H H H H L L H H H H L L CY7C1345G OE X X X X X X L H X L H L H L H X X L H L H X X CLK DQ L-H tri-state L-H tri-state L-H tri-state L-H tri-state L-H tri-state X tri-state L-H Q L-H tri-state L-H D L-H Q L-H tri-state L-H Q L-H tri-state L-H Q L-H tri-state L-H D L-H D L-H Q L-H tri-state L-H Q L-H tri-state L-H D L-H D Notes: 2. X = “Don't Care.” H = Logic HIGH, L = Logic LOW. 3. WRITE = L when any one or more Byte Write enable signals (BWA, BWB, BWC, BWD) and BWE = L or GW= L. WRITE = H when all Byte write enable signals (BWA, BWB, BWC, BWD), BWE, GW = H. 4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock. 5. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW[A: D]. Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a don't care for the remainder of the write cycle. 6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW). Document #: 38-05517 Rev. *A Page 6 of 17 PRELIMINARY Partial Truth Table for Read/Write[2, 7] Function Read Read Write Byte (A, DQPA) Write Byte (B, DQPB) Write Bytes (B, A, DQPA, DQPB) Write Byte (C, DQPC) Write Bytes (C, A, DQPC, DQPA) Write Bytes (C, B, DQPC, DQPB) Write Bytes (C, B, A, DQPC, DQPB, DQPA) Write Byte (D, DQPD) Write Bytes (D, A, DQPD, DQPA) Write Bytes (D, B, DQPD, DQPA) Write Bytes (D, B, A, DQPD, DQPB, DQPA) Write Bytes (D, B, DQPD, DQPB) Write Bytes (D, B, A, DQPD, DQPC, DQPA) Write Bytes (D, C, A, DQPD, DQPB, DQPA) Write All Bytes Write All Bytes GW H H H H H H H H H H H H H H H H H L BWE H L L L L L L L L L L L L L L L L X BWD X H H H H H H H H L L L L L L L L X BWC X H H H H L L L L H H H H L L L L X CY7C1345G BWB X H H L L H H L L H H L L H H L L X BWA X H L H L H L H L H L H L H L H L X Note: 7. Table only lists a partial listing of the byte write combinations. Any combination of BWx is valid. Appropriate write will be done based on which byte write is active. Document #: 38-05517 Rev. *A Page 7 of 17 PRELIMINARY Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage on VDD Relative to GND........ –0.5V to +4.6V DC Voltage Applied to Outputs in tri-state ............................................ –0.5V to VDDQ + 0.5V DC Input Voltage....................................–0.5V to VDD + 0.5V CY7C1345G Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage........................................... >2001V (per MIL-STD-883, Method 3015) Latch-up Current..................................................... >200 mA Operating Range Range Commercial Industrial [8, 9] Ambient Temperature] 0°C to +70°C VDD VDDQ 3.3V −5%/+10% 2.5V –5% to VDD –40°C to +85°C Electrical Characteristics Over the Operating Range Parameter VDD VDDQ VOH VOL VIH VIL IX Description Power Supply Voltage I/O Supply Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[8] Input Load Current (except ZZ and MODE) Input Current of MODE Input Current of ZZ IOZ IDD Output Leakage Current VDD Operating Supply Current CY7C1345F Test Conditions Min. 3.135 2.375 VDDQ = 3.3V, VDD = Min., IOH = –4.0 mA VDDQ = 2.5V, VDD = Min., IOH = –1.0 mA VDDQ = 3.3V, VDD = Min., IOL = 8.0 mA VDDQ = 2.5V, VDD = Min., IOL = 1.0 mA VDDQ = 3.3V VDDQ = 2.5V VDDQ = 3.3V VDDQ = 2.5V GND ≤ VI ≤ VDDQ Input = VSS Input = VDD Input = VSS Input = VDD GND ≤ VI ≤ VDD, Output Disabled VDD = Max., IOUT = 0 mA, f = fMAX= 1/tCYC Max. VDD, Device Deselected, VIN ≥ VIH or VIN ≤ VIL, f = fMAX, inputs switching 7.5-ns cycle, 133 MHz 8.0-ns cycle, 117 MHz 10-ns cycle, 100 MHz ISB1 Automatic CE Power-down Current—TTL Inputs 7.5-ns cycle, 133 MHz 8.0-ns cycle, 117 MHz 10-ns cycle, 100 MHz –5 –5 30 5 225 220 205 90 85 80 40 2.0 1.7 –0.3 –0.3 −5 –30 5 2.4 2.0 0.4 0.4 VDD + 0.3V VDD + 0.3V 0.8 0.7 5 Max. 3.6 VDD Unit V V V V V V V V V V µA µA µA µA µA µA mA mA mA mA mA mA mA ISB2 Automatic CE Power-down Current—CMOS Inputs Automatic CE Power-down Current—CMOS Inputs Max. VDD, Device Deselected, All speeds VIN ≥ VDD – 0.3V or VIN ≤ 0.3V, f = 0, inputs static Max. VDD, Device Deselected, 7.5-ns cycle, 133 MHz VIN ≥ VDDQ – 0.3V or VIN ≤ 0.3V, 8.0-ns cycle, 117 MHz f = fMAX, inputs switching 10-ns cycle, 100 MHz Max. VDD, Device Deselected, All speeds VIN ≥ VDD – 0.3V or VIN ≤ 0.3V, f = 0, inputs static ISB3 75 70 65 45 mA mA mA mA ISB4 Automatic CE Power-down Current—TTL Inputs Shaded areas contain advance information. Notes: 8. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC) > -2V (Pulse width less than tCYC/2). 9. TPower-up: Assumes a linear ramp from 0v to VDD(min.) within 200ms. During this time VIH < VDD and VDDQ < VDD. Document #: 38-05517 Rev. *A Page 8 of 17 PRELIMINARY Thermal Resistance[10] Parameter ΘJA ΘJC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA / JESD51. TQFP Package TBD TBD CY7C1345G BGA Package TBD TBD Unit °C/W °C/W Capacitance[10] Parameter CIN CCLK CI/O Description Input Capacitance Clock Input Capacitance Input/Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VDD = 3.3V. VDDQ = 3.3V TQFP Package BGA Package 5 5 5 5 5 7 Unit pF pF pF AC Test Loads and Waveforms 3.3V I/O Test Load OUTPUT Z0 = 50Ω 3.3V OUTPUT RL = 50Ω 5 pF R = 351Ω R = 317Ω ALL INPUT PULSES VDDQ 10% GND ≤ 1ns 90% 90% 10% ≤ 1ns VT = 1.5V (a) 2.5V I/O Test Load OUTPUT Z0 = 50Ω INCLUDING JIG AND SCOPE (b) R = 1667Ω VDDQ 10% GND R =1538Ω ≤ 1ns (c) 2.5V OUTPUT RL = 50Ω VT = 1.25V 5 pF INCLUDING JIG AND SCOPE ALL INPUT PULSES 90% 90% 10% ≤ 1ns (a) (b) (c) Switching Characteristics Over the Operating Range [15, 16] 133 MHz Parameter tPOWER Clock tCYC tCH tCL Output Times tCDV tDOH tCLZ Data Output Valid After CLK Rise Data Output Hold After CLK Rise Clock to Low-Z[12, 13, 14] 2.0 0 6.5 2.0 0 7.5 2.0 0 8.0 ns ns ns Clock Cycle Time Clock HIGH Clock LOW 7.5 2.5 2.5 8.5 3.0 3.0 10 4.0 4.0 ns ns ns Description VDD(Typical) to the first Access[11] Min. 1 Max. 117 MHz Min. 1 Max. 100 MHz Min. 1 Max. Unit ms Notes: 10. Tested initially and after any design or process change that may affect these parameters. 11. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a read or write operation can be initiated. 12. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage. 13. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z prior to Low-Z under the same system conditions. 14. This parameter is sampled and not 100% tested. 15. Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V. 16. Test conditions shown in (a) of AC Test Loads unless otherwise noted. Document #: 38-05517 Rev. *A Page 9 of 17 PRELIMINARY Switching Characteristics Over the Operating Range (continued)[15, 16] 133 MHz Parameter tCHZ tOEV tOELZ tOEHZ Set-up Times tAS tADS tADVS tWES tDS tCES Hold Times tAH tADH tWEH tADVH tDH tCEH Address Hold After CLK Rise ADSP, ADSC Hold After CLK Rise GW,BWE, BWx Hold After CLK Rise ADV Hold After CLK Rise Data Input Hold After CLK Rise Chip Enable Hold After CLK Rise 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 Address Set-up Before CLK Rise ADSP, ADSC Set-up Before CLK Rise ADV Set-up Before CLK Rise GW, BWE, BWx Set-up Before CLK Rise Data Input Set-up Before CLK Rise Chip Enable Set-up 1.5 1.5 1.5 1.5 1.5 1.5 2.0 2.0 2.0 2.0 2.0 2.0 Clock to High-Z Description [12, 13, 14] CY7C1345G 117 MHz Min. Max. 3.5 3.5 0 3.5 3.5 2.0 2.0 2.0 2.0 2.0 2.0 0.5 0.5 0.5 0.5 0.5 0.5 0 3.5 100 MHz Min. Max. 3.5 3.5 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Min. Max. 3.5 3.5 OE LOW to Output Valid OE LOW to Output Low-Z [12, 13, 14] 0 OE HIGH to Output High-Z[12, 13, 14] Document #: 38-05517 Rev. *A Page 10 of 17 PRELIMINARY Timing Diagrams Read Cycle Timing[17] tCYC CY7C1345G CLK t CH t CL tADS tADH ADSP tADS tADH ADSC tAS tAH ADDRESS A1 t WES t WEH A2 GW, BWE,BW [A:D] tCES t CEH Deselect Cycle CE t ADVS t ADVH ADV ADV suspends burst. OE t OEV t CLZ t OEHZ t OELZ tCDV tDOH t CHZ Data Out (Q) High-Z Q(A1) t CDV Q(A2) Q(A2 + 1) Q(A2 + 2) Q(A2 + 3) Q(A2) Q(A2 + 1) Q(A2 + 2) Burst wraps around to its initial state Single READ DON’T CARE BURST READ UNDEFINED Notes: 17. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH. 18. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BWx LOW. Document #: 38-05517 Rev. *A Page 11 of 17 PRELIMINARY Timing Diagrams (continued) Write Cycle Timing[17, 18] tCYC CY7C1345G CLK t CH t CL tADS tADH ADSP tADS tADH ADSC tAS tAH ADDRESS A1 t WES t WEH A2 GW, BWE,BW [A:D] tCES t CEH Deselect Cycle CE t ADVS t ADVH ADV ADV suspends burst. OE t OEV t CLZ t OEHZ t OELZ tCDV tDOH t CHZ Data Out (Q) High-Z Q(A1) t CDV Q(A2) Q(A2 + 1) Q(A2 + 2) Q(A2 + 3) Q(A2) Q(A2 + 1) Q(A2 + 2) Single READ DON’T CARE BURST READ UNDEFINED Burst wraps around to its initial state Document #: 38-05517 Rev. *A Page 12 of 17 PRELIMINARY Timing Diagrams (continued) Read/Write Timing[17, 19, 20] t CYC CY7C1345G CLK t CH t CL tADS tADH ADSP tADS tADH ADSC extends burst tADS tADH ADSC tAS tAH ADDRESS A1 A2 Byte write signals are ignored for first cycle when ADSP initiates burst A3 tWES tWEH BWE, BW[A:D] t t WES WEH GW tCES tCEH CE tADVS tADVH ADV ADV suspends burst OE t DS t DH D(A2) D(A2 + 1) D(A2 + 1) D(A2 + 2) D(A2 + 3) D(A3) D(A3 + 1) D(A3 + 2) Data in (D) High-Z t OEHZ D(A1) Data Out (Q) BURST READ Single WRITE BURST WRITE Extended BURST WRITE DON’T CARE UNDEFINED Notes: 19. The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC. 20. GW is HIGH. Document #: 38-05517 Rev. *A Page 13 of 17 PRELIMINARY Timing Diagrams (continued) ZZ Mode Timing [21, 22] CLK t ZZ t ZZREC CY7C1345G ZZ t ZZI I SUPPLY I DDZZ t RZZI DESELECT or READ Only ALL INPUTS (except ZZ) Outputs (Q) High-Z DON’T CARE Ordering Information Speed (MHz) 133 Ordering Code CY7C1345G-133AXC CY7C1345G-133BGC CY7C1345G-133BGXC CY7C1345G-133AXI CY7C1345G-133BGI CY7C1345G-133BGXI 117 CY7C1345G-117AXC CY7C1345G-117BGC CY7C1345G-117BGXC CY7C1345G-117AXI CY7C1345G-117BGI CY7C1345G-117BGXI 100 CY7C1345G-100AXC CY7C1345G-100BGC CY7C1345G-100BGXC CY7C1345G-100AXI CY7C1345G-100BGI CY7C1345G-100BGXI Package Name A101 BG119 BG119 A101 BG119 BG119 A101 BG119 BG119 A101 BG119 BG119 A101 BG119 BG119 A101 BG119 BG119 Package Type Lead-free 100-Lead Thin Quad Flat Pack (14 x 20 x 1.4mm) 119-Ball PBGA (14 x 22 x 2.4mm) Lead-free 119-Ball PBGA (14 x 22 x 2.4mm) Lead-free 100-Lead Thin Quad Flat Pack (14 x 20 x 1.4mm) 119-Ball PBGA (14 x 22 x 2.4mm) Lead-free 119-Ball PBGA (14 x 22 x 2.4mm) Lead-free 100-Lead Thin Quad Flat Pack (14 x 20 x 1.4mm) 119-Ball PBGA (14 x 22 x 2.4mm) Lead-free 119-Ball PBGA (14 x 22 x 2.4mm) Lead-free 100-Lead Thin Quad Flat Pack (14 x 20 x 1.4mm) 119-Ball PBGA (14 x 22 x 2.4mm) Lead-free 119-Ball PBGA (14 x 22 x 2.4mm) Lead-free 100-Lead Thin Quad Flat Pack (14 x 20 x 1.4mm) 119-Ball PBGA (14 x 22 x 2.4mm) Lead-free 119-Ball PBGA (14 x 22 x 2.4mm) Lead-free 100-Lead Thin Quad Flat Pack (14 x 20 x 1.4mm) 119-Ball PBGA (14 x 22 x 2.4mm) Lead-free 119-Ball PBGA (14 x 22 x 2.4mm) Industrial Commercial Industrial Commercial Industrial Operating Range Commercial Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts. Lead-Free BG pkg will be available in 2005. Notes: 21. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device. 22. DQs are in high-Z when exiting ZZ sleep mode. Document #: 38-05517 Rev. *A Page 14 of 17 PRELIMINARY Package Diagrams 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101 CY7C1345G 51-85050-*A Document #: 38-05517 Rev. *A Page 15 of 17 PRELIMINARY Package Diagrams (continued) 119-Lead BGA (14 x 22 x 2.4 mm) BG119 CY7C1345G 51-85115-*B Intel and Pentium are registered trademarks of Intel Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05517 Rev. *A Page 16 of 17 © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. PRELIMINARY Document History Page Document Title: CY7C1345G 4-Mbit (128K x 36) Flow-Through Sync SRAM Document Number: 38-05517 REV. ** *A ECN NO. 224365 278513 Issue Date See ECN See ECN CY7C1345G Orig. of Change RKF VBL New data sheet Description of Change Deleted 66 MHz Changed TQFP package to lead-free TQFP in Ordering Information section Added BG lead-free package Document #: 38-05517 Rev. *A Page 17 of 17