CY7C1347B-133BGI

1CY7C1347 CY7C1347B 128K x 36 Synchronous-Pipelined Cache RAM Features • Supports 100-MHz bus for Pentium and PowerPC™ operations with zero wait states • Fully registered inputs and outputs for pipelined operation • 128K by 36 common I/O architecture • 3.3V core power supply • 2.5V/3.3V I/O operation • Fast clock-to-output times — 3.5 ns (for 166-MHz device) — 4.0 ns (for 133-MHz device) • • • • • • • — 5.5 ns (for 100-MHz device) User-selectable burst counter supporting Intel Pentium interleaved or linear burst sequences Separate processor and controller address strobes Synchronous self-timed writes Asynchronous output enable JEDEC-standard 100 TQFP pinout “ZZ” Sleep Mode option and Stop Clock option Available in Industrial and Commercial Temperature ranges The CY7C1347B I/O pins can operate at either the 2.5V or the 3.3V level, the I/O pins are 3.3V tolerant when VDDQ = 2.5V. All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise is 3.5 ns (166-MHz device). The CY7C1347B supports either the interleaved burst sequence used by the Intel Pentium processor or a linear burst sequence used by processors such as the PowerPC. The burst sequence is selected through the MODE pin. Accesses can be initiated by asserting either the Processor Address Strobe (ADSP) or the Controller Address Strobe (ADSC) at clock rise. Address advancement through the burst sequence is controlled by the ADV input. A 2-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. Byte write operations are qualified with the four Byte Write Select (BW[3:0]) inputs. A Global Write Enable (GW) overrides all byte write inputs and writes data to all four bytes. All writes are conducted with on-chip synchronous self-timed write circuitry. Three synchronous Chip Selects (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output three-state control. In order to provide proper data during depth expansion, OE is masked during the first clock of a read cycle when emerging from a deselected state. Functional Description The CY7C1347B is a 3.3V, 128K by 36 synchronous-pipelined cache SRAM designed to support zero-wait-state secondary cache with minimal glue logic. Logic Block Diagram CLK ADV ADSC ADSP A[16:0] GW BWE BW 3 BW2 BW1 BW0 CE1 CE2 CE3 MODE (A[1;0]) 2 BURST Q0 CE COUNTER Q1 CLR Q ADDRESS CE REGISTER D 15 17 17 15 D DQ[31:24], DP[3] Q BYTEWRITE REGISTERS D DQ[23:16], DP[2] Q BYTEWRITE REGISTERS D DQ[15:8], DP[1] Q BYTEWRITE REGISTERS D DQ[7:0], DP[0] Q BYTEWRITE REGISTERS D ENABLE CE REGISTER Q 128KX36 MEMORY ARRAY 36 36 D ENABLE DELAY Q REGISTER OE ZZ SLEEP CONTROL OUTPUT REGISTERS CLK INPUT REGISTERS CLK DQ[31:0] DP[3:0] Pentium and Intel are registered trademarks of Intel Corporation. PowerPC is a trademark of IBM Corporation. Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 March 11, 2001 CY7C1347B Pin Configurations 100-Pin TQFP A6 A7 CE1 CE2 BW3 BW2 BW1 BW0 CE3 VDD VSS CLK GW BWE OE ADSC ADSP ADV A8 A9 DP2 DQ16 DQ17 VDDQ VSSQ DQ18 DQ19 DQ20 DQ21 VSSQ VDDQ DQ22 DQ23 NC VDD NC VSS DQ24 DQ25 VDDQ VSSQ DQ26 DQ27 DQ28 DQ29 VSSQ VDDQ DQ30 DQ31 DP3 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 BYTE2 BYTE3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 CY7C1347B 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 DP1 DQ15 DQ14 VDDQ VSSQ DQ13 DQ12 DQ11 DQ10 VSSQ VDDQ DQ9 DQ8 VSS NC VDD ZZ DQ7 DQ6 VDDQ VSSQ DQ5 DQ4 DQ3 DQ2 VSSQ VDDQ DQ1 DQ0 DP0 BYTE1 BYTE0 MODE A5 A4 A3 A2 A1 A0 NC NC VSS VDD NC NC A10 A11 A12 A13 A14 A15 A16 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 2 CY7C1347B Pin Configurations (continued) 119-Ball BGA 1 A B C D E F G H J K L M N P R T U VDDQ NC NC DQc DQc VDDQ DQc DQc VDDQ DQd DQd VDDQ DQd DQd NC NC VDDQ 2 A CE2 A DQPc DQc DQc DQc DQc VDD DQd DQd DQd DQd DQPd A NC NC 3 A A A VSS VSS VSS BWc VSS NC VSS BWd VSS VSS VSS MODE A NC 4 ADSP ADSC VDD NC CE1 OE ADV GW VDD CLK NC BWE A1 A0 VDD A NC 5 A A A VSS VSS VSS BWb VSS NC VSS BWa VSS VSS VSS VDD A NC 6 A CE3 A DQPb DQb DQb DQb DQb VDD DQa DQa DQa DQa DQPa A NC NC 7 VDDQ NC NC DQb DQb VDDQ DQb DQb VDDQ DQa DQa VDDQ DQa DQa NC ZZ VDDQ Selection Guide 7C1347B-166 Maximum Access Time (ns) Maximum Operating Current (mA) Maximum CMOS Standby Current (mA) 3.5 420 10 7C1347B-133 4.0 375 10 7C1347B-100 5.5 325 10 3 CY7C1347B Pin Definitions Name A[16:0] I/O InputSynchronous InputSynchronous InputSynchronous InputSynchronous Input-Clock InputSynchronous InputSynchronous InputSynchronous InputAsynchronous Description Address Inputs used to select one of the 64K address locations. Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A[1:0] feed the 2-bit counter. Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM. Sampled on the rising edge of CLK. Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global write is conducted (ALL bytes are written, regardless of the values on BW[3:0] and BWE). Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted LOW to conduct a byte write. Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst counter when ADV is asserted LOW, during a burst operation. Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3 to select/deselect the device. Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select/deselect the device. Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE is masked during the first clock of a read cycle when emerging from a deselected state. Advance Input signal, sampled on the rising edge of CLK. When asserted, it automatically increments the address in a burst cycle. Address Strobe from Processor, sampled on the rising edge of CLK. When asserted LOW, A[16:0] is captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH. Address Strobe from Controller, sampled on the rising edge of CLK. When asserted LOW, A[16:0] is captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ZZ “sleep” Input. This active HIGH input places the device in a non-time-critical “sleep” condition with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin has an internal pull-down. Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by A[16:0] during the previous clock rise of the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQ[31:0] and DP[3:0] are placed in a three-state condition. Power supply inputs to the core of the device. Should be connected to 3.3V power supply. Ground for the core of the device. Should be connected to ground of the system. Power supply for the I/O circuitry. Should be connected to a 3.3V or 2.5V power supply. Ground for the I/O circuitry. Should be connected to ground of the system. Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDDQ or left floating selects interleaved burst sequence. This is a strap pin and should remain static during device operation. Mode Pin has an internal pull-up. No Connects. BW[3:0] GW BWE CLK CE1 CE2 CE3 OE ADV ADSP InputSynchronous InputSynchronous ADSC InputSynchronous InputAsynchronous I/OSynchronous ZZ DQ[31:0] DP[3:0] VDD VSS VDDQ VSSQ MODE Power Supply Ground I/O Power Supply I/O Ground InputStatic NC 4 CY7C1347B Introduction Functional Overview All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (t CO) is 3.5 ns (166-MHz device). The CY7C1347B supports secondary cache in systems utilizing either a linear or interleaved burst sequence. The interleaved burst order supports Pentium and i486 processors. The linear burst sequence is suited for processors that utilize a linear burst sequence. The burst order is user selectable, and is determined by sampling the MODE input. Accesses can be initiated with either the Processor Address Strobe (ADSP) or the Controller Address Strobe (ADSC). Address advancement through the burst sequence is controlled by the ADV input. A two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. Byte write operations are qualified with the Byte Write Enable (BWE) and Byte Write Select (BW[3:0]) inputs. A Global Write Enable (GW) overrides all byte write inputs and writes data to all four bytes. All writes are simplified with on-chip synchronous self-timed write circuitry. Three synchronous Chip Selects (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output three-state control. ADSP is ignored if CE1 is HIGH. Single Read Accesses This access is initiated when the following conditions are satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2) CE1, CE2, CE3 are all asserted active, and (3) the write signals (GW, BWE) are all deasserted HIGH. ADSP is ignored if CE1 is HIGH. The address presented to the address inputs (A[16:0]) is stored into the address advancement logic and the Address Register while being presented to the memory core. The corresponding data is allowed to propagate to the input of the Output Registers. At the rising edge of the next clock the data is allowed to propagate through the Output Register and onto the data bus within 3.5 ns (166-MHz device) if OE is active LOW. The only exception occurs when the SRAM is emerging from a deselected state to a selected state, its outputs are always three-stated during the first cycle of the access. After the first cycle of the access, the outputs are controlled by the OE signal. Consecutive single read cycles are supported. Once the SRAM is deselected at clock rise by the chip select and either ADSP or ADSC signals, its output will three-state immediately. Single Write Accesses Initiated by ADSP This access is initiated when both of the following conditions are satisfied at clock rise: (1) ADSP is asserted LOW, and (2) CE1, CE2, CE3 are all asserted active. The address presented to A[16:0] is loaded into the Address Register and the address advancement logic while being delivered to the RAM core. The write signals (GW, BWE, and BW[3:0]) and ADV inputs are ignored during this first cycle. ADSP-triggered write accesses require two clock cycles to complete. If GW is asserted LOW on the second clock rise, the data presented to the DQ[31:0] and DP[3:0] inputs is written into the corresponding address location in the RAM core. If GW is HIGH, then the write operation is controlled by BWE and BW[3:0] signals. The CY7C1347B provides byte write capability that is described in the Write Cycle Description table. Asserting the Byte Write Enable input (BWE) with the selected Byte Write (BW[3:0]) input will selectively write to only the desired bytes. Bytes not selected during a byte write operation will remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. Because the CY7C1347B is a common I/O device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQ[31:0] and DP[3:0] inputs. Doing so will three-state the output drivers. As a safety precaution, DQ[31:0] and DP[3:0] are automatically three-stated whenever a write cycle is detected, regardless of the state of OE. Single Write Accesses Initiated by ADSC ADSC write accesses are initiated when the following conditions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deasserted HIGH, (3) CE1, CE2, CE3 are all asserted active, and (4) the appropriate combination of the write inputs (GW, BWE, and BW[3:0]) are asserted active to conduct a write to the desired byte(s). ADSC-triggered write accesses require a single clock cycle to complete. The address presented to A[16:0] is loaded into the address register and the address advancement logic while being delivered to the RAM core. The ADV input is ignored during this cycle. If a global write is conducted, the data presented to the DQ[31:0] and DP[3:0] is written into the corresponding address location in the RAM core. If a byte write is conducted, only the selected bytes are written. Bytes not selected during a byte write operation will remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. Because the CY7C1347B is a common I/O device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQ[31:0] and DP[3:0] inputs. Doing so will three-state the output drivers. As a safety precaution, DQ[31:0] and DP[3:0] are automatically three-stated whenever a write cycle is detected, regardless of the state of OE. Burst Sequences The CY7C1347B provides a two-bit wraparound counter, fed by A[1:0], that implements either an interleaved or linear burst sequence. The interleaved burst sequence is designed specifically to support Intel Pentium applications. The linear burst sequence is designed to support processors that follow a linear burst sequence. The burst sequence is user-selectable through the MODE input. Asserting ADV LOW at clock rise will automatically increment the burst counter to the next address in the burst sequence. Both read and write burst operations are supported. 5 CY7C1347B Interleaved Burst Sequence First Address A[1:0] 00 01 10 11 Second Address A[1:0] 01 00 11 10 Third Address A[1:0] 10 11 00 01 Fourth Address A[1:0] 11 10 01 00 Sleep Mode The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the “sleep” mode. , CE1, CE2, CE3, ADSP and ADSC must remain inactive for the duration of tZZREC after the ZZ input returns LOW. Linear Burst Sequence First Address A[1:0] 00 01 10 11 Second Address A[1:0] 01 10 11 00 Third Address A[1:0] 10 11 00 01 Fourth Address A[1:0] 11 00 01 10 ZZ Mode Electrical Characteristics Parameter IDDZZ tZZS tZZREC . Description Snooze mode standby current Device operation to ZZ ZZ recovery time Test Conditions ZZ > VDD − 0.2V ZZ > VDD − 0.2V ZZ < 0.2V 2tCYC Min. Max. 10 2tCYC Unit mA ns ns 6 CY7C1347B Cycle Descriptions[1, 2, 3] Next Cycle Unselected Unselected Unselected Unselected Unselected Begin Read Begin Read Continue Read Continue Read Continue Read Continue Read Suspend Read Suspend Read Suspend Read Suspend Read Begin Write Begin Write Begin Write Continue Write Continue Write Suspend Write Suspend Write ZZ “Sleep” Add. Used None None None None None External External Next Next Next Next Current Current Current Current Current Current External Next Next Current Current None ZZ L L L L L L L L L L L L L L L L L L L L L L H CE3 X 1 X 1 X 0 0 X X X X X X X X X X 0 X X X X X CE2 X X 0 X 0 1 1 X X X X X X X X X X 1 X X X X X CE1 1 0 0 0 0 0 0 X X 1 1 X X 1 1 X 1 0 X 1 X 1 X ADSP X 0 0 1 1 0 1 1 1 X X 1 1 X X 1 X 1 1 X 1 X X ADSC 0 X X 0 0 X 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 X ADV X X X X X X X 0 0 0 0 1 1 1 1 1 1 X 0 0 1 1 X OE X X X X X X X 1 0 1 0 1 0 1 0 X X X X X X X X DQ Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z DQ Hi-Z DQ Hi-Z DQ Hi-Z DQ Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Write X X X X X X Read Read Read Read Read Read Read Read Read Write Write Write Write Write Write Write X Notes: 1. X = “Don't Care,” 1 = HIGH, 0 = LOW. 2. Write is defined by BWE, BW[3:0], and GW. See Write Cycle Description Table. 3. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock. 7 CY7C1347B Write Cycle Description[4, 5, 6] Function Read Read Write Byte 0 - DQ[7:0] Write Byte 1 - DQ[15:8] Write Bytes 1, 0 Write Byte 2 - DQ[23:16] Write Bytes 2, 0 Write Bytes 2, 1 Write Bytes 2, 1, 0 Write Byte 3 - DQ[31:24] Write Bytes 3, 0 Write Bytes 3, 1 Write Bytes 3, 1, 0 Write Bytes 3, 2 Write Bytes 3, 2, 0 Write Bytes 3, 2, 1 Write All Bytes Write All Bytes GW 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 BWE 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X BW3 X 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 X BW2 X 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 X BW1 X 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 X BW0 X 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 X Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ..................................... −65°C to +150°C Ambient Temperature with Power Applied .................................................. −55°C to +125°C Supply Voltage on VDD Relative to GND .........−0.5V to +4.6V DC Voltage Applied to Outputs in High Z State[7] ....................................... −0.5V to VDD + 0.5V DC Input Voltage[7] .................................... −0.5V to VDD + 0.5V Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage .......................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current.................................................... >200 mA Operating Range Range Com’l Ind’l Ambient Temperature[8] 0°C to +70°C –40°C to +85°C VDD 3.3V −5%/+10% VDDQ 2.5V −5% 3.3V /+10% Notes: 4. X = “Don't Care,” 1 = Logic HIGH, 0 = Logic LOW. 5. The SRAM always initiates a read cycle when ADSP asserted, regardless of the state of GW, BWE, or BW[3:0]. Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to three-state. OE is a don't care for the remainder of the write cycle. 6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQ[31:0];DP[3:0] = High-Z when OE is inactive or when the device is deselected, and DQ[31:0];DP[3:0] = data when OE is active. 7. Minimum voltage equals −2.0V for pulse durations of less than 20 ns. 8. TA is the case temperature. 8 CY7C1347B Electrical Characteristics Over the Operating Range Parameter VDD VDDQ VOH VOL VIH VIL IX Description Power Supply Voltage I/O Supply Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage [7] Test Conditions 3.3V −5%/+10% 2.5V −5% to 3.3V +10% VDD = Min., IOH = −4.0 mA VDD = Min., IOL = 8.0 mA Min. 3.135 2.375 2.4 Max. 3.6 3.6 Unit V V V 0.4 2.0 –0.3 VDD + 0.3V 0.8 5 V V V µA µA Input Load Current except ZZ and MODE GND ≤ VI ≤ VDDQ −5 –30 Input Current of MODE Input = VSS Input = VDDQ Input Current of ZZ Input = VSS Input = VDDQ IOZ IDD Output Leakage Current VDD Operating Supply Current GND ≤ VI ≤ VDDQ, Output Disabled VDD = Max., IOUT = 0 mA, f = fMAX = 1/tCYC 6-ns cycle, 166 MHz 7.5-ns cycle, 133 MHz 10-ns cycle, 100 MHz ISB1 Automatic CS Power-Down Current—TTL Inputs Max. VDD, Device Deselected, VIN ≥ VIH or VIN ≤ VIL f = fMAX = 1/tCYC 6-ns cycle, 166 MHz 7.5-ns cycle, 133 MHz 10-ns cycle, 100 MHz ISB2 Automatic CS Max. VDD, Device Deselected, VIN All speeds Power-Down ≤ 0.3V or VIN > VDDQ – 0.3V, f = 0 Current—CMOS Inputs Automatic CS Max. VDD, Device Deselected, or Power-Down VIN ≤ 0.3V or VIN > VDDQ – 0.3V Current—CMOS Inputs f = fMAX = 1/tCYC Automatic CS Power-Down Current—TTL Inputs Max. VDD, Device Deselected, VIN ≥ VIH or VIN ≤ VIL, f = 0 6-ns cycle, 166 MHz 7.5-ns cycle, 133 MHz 10-ns cycle, 100 MHz ISB4 5 –5 30 −5 5 420 375 325 150 125 115 10 µA µA µA µA mA mA mA mA mA mA mA ISB3 120 95 85 18 mA mA mA mA Capacitance[9] Parameter CIN CCLK CI/O Description Input Capacitance Clock Input Capacitance Input/Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VDD = 3.3V. VDDQ = 3.3V Max. 6 8 8 Unit pF pF pF Note: 9. Tested initially and after any design or process changes that may affect these parameters. 9 CY7C1347B AC Test Loads and Waveforms OUTPUT Z0 =50Ω RL =50Ω VL = 1.5V 3.3V OUTPUT 5 pF INCLUDING JIG AND SCOPE R=351Ω R=317Ω ALL INPUT PULSES 2.5V 10% GND ≤ 2.5 ns 90% [10] 90% 10% ≤ 2.5 ns (a) (b) (c) Switching Characteristics Over the Operating Range[11, 12, 13] -166 Parameter tCYC tCH tCL tAS tAH tCO tDOH tADS tADH tWES tWEH tADVS tADVH tDS tDH tCES tCEH tCHZ tCLZ tOEHZ tOELZ tOEV Description Clock Cycle Time Clock HIGH Clock LOW Address Set-Up Before CLK Rise Address Hold After CLK Rise Data Output Valid After CLK Rise Data Output Hold After CLK Rise ADSP ADSC Set-Up Before CLK Rise , ADSP ADSC Hold After CLK Rise , BWE, GW, BW[3:0] Set-Up Before CLK Rise BWE, GW, BW[3:0] Hold After CLK Rise ADV Set-Up Before CLK Rise ADV Hold After CLK Rise Data Input Set-Up Before CLK Rise Data Input Hold After CLK Rise Chip Select Set-Up Chip Select Hold After CLK Rise Clock to High-Z[12] Clock to Low-Z[12] High-Z[12, 13] Low-Z[12, 13] 0 3.5 0 3.5 0 4.0 1.5 1.5 0.5 1.5 0.5 1.5 0.5 1.5 0.5 1.5 0.5 3.5 0 3.5 0 5.5 Min. 6.0 1.7 1.7 1.5 0.5 3.5 2.0 1.5 0.5 1.5 0.5 1.5 0.5 1.5 0.5 1.5 0.5 3.5 0 5.5 Max. Min. 7.5 1.9 1.9 1.5 0.5 4.0 2.0 1.5 0.5 1.5 0.5 1.5 0.5 1.5 0.5 1.5 0.5 3.5 -133 Max. Min. 10 3.5 3.5 1.5 0.5 5.5 -100 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns OE HIGH to Output OE LOW to Output OE LOW to Output Valid[12] Notes: 10. Input waveform should have a slew rate of 1 V/ns. 11. Unless otherwise noted, test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and load capacitance. Shown in (a) and (b) of AC test loads. 12. tCHZ, tCLZ, tEOV, tEOLZ, and tEOHZ are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage. 13. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ . 10 CY7C1347B 1 Switching Waveforms Write Cycle Timing[14, 15] Single Write tCH tCYC Burst Write Pipelined Write Unselected CLK tADH tADS tCL ADSP ignored with CE1 inactive ADSP tADS tADH ADSC initiated write ADSC tADVS tADVH ADV tAS ADV Must Be Inactive for ADSP Write WD1 tAH WD2 WD3 ADD GW tWS tWH tWS CE1 masks ADSP tWH WE tCES tCEH CE1 tCES tCEH Unselected with CE2 CE2 CE3 tCES tCEH OE tDS tDH High-Z Data In High-Z 1a 1a 2a = UNDEFINED 2b 2c 2d 3a = DON’T CARE Notes: 14. WE is the combination of BWE, BW[3:0], and GW to define a write cycle (see Write Cycle Description table). 15. WDx stands for Write Data to Address X. 11 CY7C1347B Switching Waveforms (continued) Read Cycle Timing[14, 16] Single Read tCYC Burst Read tCH Pipelined Read Unselected CLK tADS tADH tCL ADSP ignored with CE1 inactive ADSP tADS ADSC initiated read ADSC tADVS tADH tADVH RD1 tAH RD2 RD3 Suspend Burst ADV tAS ADD GW tWS tWH tWS WE tCES tCEH tWH CE1 masks ADSP CE1 Unselected with CE2 CE2 tCES tCEH CE3 tCES tCEH tEOV tOEHZ tDOH tCO OE Data Out 1a 1a tCLZ 2a 2b 2c 2c 2d 3a tCHZ = DON’T CARE = UNDEFINED Note: 16. RDx stands for Read Data from Address X. 12 CY7C1347B Switching Waveforms (continued) Read/Write Cycle Timing[14, 15, 16, 17] Single Read tCYC Single Write tCH Burst Read Pipelined Read Unselected CLK tADS tADH tCL ADSP ignored with CE1 inactive ADSP tADS ADSC tADVS tADH ADV tAS tADVH RD1 tAH WD2 RD3 ADD GW tWS tWH tWS WE tCES tCEH tWH CE1 masks ADSP CE1 CE2 tCES tCEH CE3 tCES tCEH tEOV tEOHZ tEOLZ tCO 1a 1a Out 2a In See Note. 2a Out OE tDS 3a Out tDH 3b Out 3c Out tDOH 3d Out tCHZ Data In/Out = DON’T CARE = UNDEFINED Note: 17. Data bus is driven by SRAM, but data is not guaranteed. 13 CY7C1347B Switching Waveforms (continued) Pipeline Timing[18, 19] tCH tCYC tCL CLK tAS ADD RD1 RD2 RD3 RD4 WD1 WD2 WD3 WD4 tADS ADSC initiated Reads tADH ADSC ADSP initiated Reads ADSP ADV tCES tCEH CE1 CE tWES tWEH WE ADSP ignored with CE1 HIGH OE tCLZ Data In/Out tCO 1a Out 2a Out 3a Out 4a Out 1a In 2a In tDOH 3a In 4a D(C) In Back to Back Reads = DON’T CARE tCHZ = UNDEFINED Notes: 18. Device originally deselected. 19. CE is the combination of CE2 and CE3. All chip selects need to be active in order to select the device. 14 CY7C1347B Switching Waveforms (continued) ZZ Mode Timing [20, 21] CLK ADSP HIGH ADSC CE1 CE2 LOW HIGH CE3 ZZ tZZS IDD IDD(active) IDDZZ tZZREC I/Os Three-state Notes: 20. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device. 21. I/Os are in three-state when exiting ZZ sleep mode. 15 CY7C1347B Ordering Information Speed (MHz) 166 133 Ordering Code CY7C1347B-166AC CY7C1347B-166BGC CY7C1347B-133AC CY7C1347B-133BGC CY7C1347B-133AI CY7C1347B-133BGI 100 CY7C1347B-100AC CY7C1347B-100BGC CY7C1347B-100AI CY7C1347B-100BGI Document #: 38-00909-*D Package Name A101 BG119 A101 BG119 A101 BG119 A101 BG119 A101 BG119 119-Ball BGA 100-Lead Thin Quad Flat Pack 119-Ball BGA 100-Lead Thin Quad Flat Pack 119-Ball BGA 100-Lead Thin Quad Flat Pack 119-Ball BGA 100-Lead Thin Quad Flat Pack 119-Ball BGA Industrial Commercial Industrial Package Type 100-Lead Thin Quad Flat Pack Operating Range Commercial Package Diagrams 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101 51-85050-A 16 CY7C1347B Package Diagrams (continued) 119-Lead FBGA (14 x 22 x 2.4 mm) BG119 51-85115 © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. 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