CY7C1347D-166AC

CY7C1347D 128K x 36 Synchronous-Pipelined Cache SRAM Features • Fast access times: 2.5 and 3.5 ns • Fast clock speed: 250, 225, 200, and 166 MHz • 1.5-ns set-up time and 0.5-ns hold time • Fast OE access times: 2.5 ns and 3.5 ns • Optimal for depth expansion (one cycle chip deselect to eliminate bus contention) • 3.3V –5% and +10% power supply • 3.3V or 2.5V I/O supply • 5V tolerant inputs except I/Os • Clamp diodes to VSS at all inputs and outputs • Common data inputs and data outputs • Byte Write Enable and Global Write control • Three chip enables for depth expansion and address pipeline • Address, data, and control registers • Internally self-timed Write Cycle • Burst control pins (interleaved or linear burst sequence) • Automatic power-down for portable applications • JTAG boundary scan • JEDEC standard pinout • Low profile 119-lead, 14-mm x 22-mm BGA (Ball Grid Array) and 100-pin TQFP packages Functional Description This Cypress Synchronous Burst SRAM employs high-speed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of four transistors and two high-valued resistors. The CY7C1347D SRAM integrate 131,072 x 36 SRAM cells with advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE), depth-expansion Chip Enables (CE2 and CE2), Burst Control Inputs (ADSC, ADSP, and ADV), Write Enables (BWa, BWb, BWc, BWd, and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and Burst Mode Control (MODE). The data outputs (Q), enabled by OE, are also asynchronous. Addresses and chip enables are registered with either Address Status Processor (ADSP) or Address Status Controller (ADSC) input pins. Subsequent burst addresses can be internally generated as controlled by the Burst Advance pin (ADV). Address, data inputs, and write controls are registered on-chip to initiate self-timed Write cycle. Write cycles can be one to four bytes wide as controlled by the write control inputs. Individual byte write allows individual byte to be written. BWa controls DQa. BWb controls DQb. BWc controls DQc. BWd controls DQd. BWa, BWb, BWc, and BWd can be active only with BWE being LOW. GW being LOW causes all bytes to be written. Four pins are used to implement JTAG test capabilities: Test Mode Select (TMS), Test Data-in (TDI), Test Clock (TCK), and Test Data-out (TDO). The JTAG circuitry is used to serially shift data to and from the device. JTAG inputs use LVTTL/LVCMOS levels to shift data during this testing mode of operation. The CY7C1347D operates from a +3.3V power supply. All inputs and outputs are LVTTL-compatible Selection Guide CY7C1347D-250 Maximum Access Time (ns) Maximum Operating Current (mA) Maximum CMOS Standby Current (mA) 2.5 450 10 CY7C1347D-225 2.5 400 10 CY7C1347D-200 2.5 360 10 CY7C1347D-166 3.5 300 10 Cypress Semiconductor Corporation Document #: 38-05022 Rev. *D • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised March 30, 2004 CY7C1347D Functional Block Diagram—CY7C1347D[1] BYTE a WRITE BWa# BWE# CLK D Q BYTE b WRITE BWb# D Q GW# BYTE c WRITE BWc# D Q BYTE d WRITE BWd# D Q byte d write byte b write byte a write DQa,DQb DQc,DQd byte c write Output Buffers CE# CE2 CE2# OE# ZZ Power Down Logic ENABLE D Q D Q ADSP# A ADSC# CLR ADV# A1-A0 MODE Binary Counter & Logic 15 Input Register Address Register 128K x 9 x 4 SRAM Array OUTPUT REGISTER D Q Note: 1. The functional block diagram illustrates simplified device operation. See Truth Table, pin descriptions and timing diagrams for detailed information. Document #: 38-05022 Rev. *D Page 2 of 21 CY7C1347D Pin Configurations 100-Pin TQFP Top View A A CE CE2 BWd BWc BWb BWa CE2 VCC VSS CLK GW BWE OE ADSC ADSP ADV A A DQc DQc DQc VCCQ VSS DQc DQc DQc DQc VSS VCCQ DQc DQc NC VCC NC VSS DQd DQd VCCQ VSS DQd DQd DQd DQd VSS VCCQ DQd DQd DQd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 CY7C1347D 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 DQb DQb DQb VCCQ VSS DQb DQb DQb DQb VSS VCCQ DQb DQb VSS NC VCC ZZ DQa DQa VCCQ VSS DQa DQa DQa DQa VSS VCCQ DQa DQa DQa Document #: 38-05022 Rev. *D MODE A A A A A1 A0 TMS TDI VSS VCC TDO TCK A A A A A A A 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Page 3 of 21 CY7C1347D Pin Configurations (continued) 119-Ball BGA Top View 1 A B C D E F G H J K L M N P R T U VCCQ NC NC DQc DQc VCCQ DQc DQc VCCQ DQd DQd VCCQ DQd DQd NC NC VCCQ 2 A CE2 A DQc DQc DQc DQc DQc VCC DQd DQd DQd DQd DQd A NC TMS 3 A A A VSS VSS VSS BWc VSS NC VSS BWd VSS VSS VSS MODE A TDI 4 ADSP ADSC VCC NC CE OE ADV GW VCC CLK NC BWE A1 A0 VCC A TCK 5 A A A VSS VSS VSS BWb VSS NC VSS BWa VSS VSS VSS NC A TDO 6 A CE2 A DQb DQb DQb DQb DQb VCC DQa DQa DQa DQa DQa A NC NC 7 VCCQ NC NC DQb DQb VCCQ DQb DQb VCCQ DQa DQa VCCQ DQa DQa NC ZZ VCCQ CY7C1347D Pin Descriptions BGA Pins 4P 4N 2A, 3A, 5A, 6A, 3B, 5B, 2C, 3C, 5C, 6C, 2R, 6R, 3T, 4T, 5T 5L 5G 3G 3L 4M QFP Pins 37 36 35, 34, 33, 32, 100, 99, 82, 81, 44, 45, 46, 47, 48, 49, 50 93 94 95 96 87 Name A0 A1 A Type InputSynchronous Description Addresses: These inputs are registered and must meet the set-up and hold times around the rising edge of CLK. The burst counter generates internal addresses associated with A0 and A1, during burst cycle and wait cycle. BWa BWb BWc BWd BWE InputSynchronous Byte Write: A byte write is LOW for a Write cycle and HIGH for a Read cycle. BWa controls DQa. BWb controls DQb. BWc controls DQc. BWd controls DQd. Data I/O are high impedance if either of these inputs are LOW, conditioned by BWE being LOW. Write Enable: This active LOW input gates byte write operations and must meet the set-up and hold times around the rising edge of CLK. Global Write: This active LOW input allows a full 36-bit Write to occur independent of the BWE and BWn lines and must meet the set-up and hold times around the rising edge of CLK. Clock: This signal registers the addresses, data, chip enables, write control and burst control inputs on its rising edge. All synchronous inputs must meet set-up and hold times around the clock’s rising edge. Chip Enable: This active LOW input is used to enable the device and to gate ADSP. Chip Enable: This active LOW input is used to enable the device. IEEE 1149.1 test inputs. LVTTL-level inputs. If JTAG feature is not utilized, this pin can be disconnected or connected to VSS. InputSynchronous InputSynchronous InputSynchronous 4H 88 GW 4K 89 CLK 4E 6B 2U 98 92 38 CE CE2 TMS InputSynchronous InputSynchronous Input Document #: 38-05022 Rev. *D Page 4 of 21 CY7C1347D CY7C1347D Pin Descriptions (continued) BGA Pins 2U 3U QFP Pins 39 43 Name TDI TCK Type Input Input Description IEEE 1149.1 test inputs. LVTTL-level inputs. If JTAG feature is not utilized, this pin can be disconnected or connected to VCC. IEEE 1149.1 test inputs. LVTTL-level inputs. If JTAG feature is not utilized, this pin can be disconnected or connected to VSS or VCC. IEEE 1149.1 test output. LVTTL-level output. If JTAG feature is not utilized, this pin should be disconnected. No Connect: These signals are not internally connected. 5U 1B, 7B, 1C, 7C, 4D, 3J, 5J, 4L, 1R, 5R, 7R, 1T, 2T, 6T, 6U 42 14, 16, 66 TDO NC Output – Burst Address Table (MODE = NC/VCC) First Address (external) A...A00 A...A01 A...A10 A...A11 Second Address (internal) A...A01 A...A00 A...A11 A...A10 Third Address (internal) A...A10 A...A11 A...A00 A...A01 Fourth Address (internal) A...A11 A...A10 A...A01 A...A00 Burst Address Table (MODE = GND) First Address (external) A...A00 A...A01 A...A10 A...A11 Second Address (internal) A...A01 A...A10 A...A11 A...A00 Third Address (internal) A...A10 A...A11 A...A00 A...A01 Fourth Address (internal) A...A11 A...A00 A...A01 A...A10 Truth Table [2, 3, 4, 5, 6, 7] Operation Deselected Cycle, Power-down Deselected Cycle, Power-down Deselected Cycle, Power-down Deselected Cycle, Power-down Deselected Cycle, Power-down Read Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Begin Burst Read Cycle, Begin Burst Read Cycle, Begin Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Continue Burst Write Cycle, Continue Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Address Used None None None None None External External External External External Next Next Next Next Next Next Current Current CE H L L L L L L L L L X X H H X H X X CE2 CE2 ADSP X X H X H L L L L L X X X X X X X X X L X L X H H H H H X X X X X X X X X L L H H L L H H H H H X X H X H H ADSC L X X L L X X L L L H H H H H H H H ADV X X X X X X X X X X L L L L L L H H Write X X X X X X X L H H H H H H L L H H OE X X X X X L H X L H L H L H X X L H CLK L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H DQ High-Z High-Z High-Z High-Z High-Z Q High-Z D Q High-Z Q High-Z Q High-Z D D Q High-Z Notes: 2. X means “Don’t Care.” H means logic HIGH. L means logic LOW. Write = L means [BWE + BWa*BWb*BWc*BWd]*GW equals LOW. Write = H means [BWE + BWa*BWb*BWc*BWd]*GW equals HIGH. BWa enables write to DQa. BWb enables write to DQb. BWc enables write to DQc. BWd enables write to DQd. 3. All inputs except OE must meet set-up and hold times around the rising edge (LOW to HIGH) of CLK. 4. Suspending burst generates wait cycle. 5. For a write operation following a read operation, OE must be HIGH before the input data required set-up time plus High-Z time for OE and staying HIGH throughout the input data hold time. 6. This device contains circuitry that will ensure the outputs will be in High-Z during power-up. 7. ADSP LOW along with chip being selected always initiates a Read cycle at the L-H edge of CLK. A Write cycle can be performed by setting Write LOW for the CLK L-H edge of the subsequent wait cycle. Refer to Write timing diagram for clarification. Document #: 38-05022 Rev. *D Page 5 of 21 CY7C1347D Truth Table (continued)[2, 3, 4, 5, 6, 7] Operation Read Cycle, Suspend Burst Read Cycle, Suspend Burst Write Cycle, Suspend Burst Write Cycle, Suspend Burst Address Used Current Current Current Current CE H H X H CE2 CE2 ADSP X X X X X X X X X X H X ADSC H H H H ADV H H H H Write H H L L OE L H X X CLK L-H L-H L-H L-H DQ Q High-Z D D Partial Truth Table for Read/Write FUNCTION Read Read Write one byte Write all bytes Write all bytes GW H H H H L BWE H L L L X BWa X H L L X BWb X H H L X BWc X H H L X BWd X H H L X IEEE 1149.1 Serial Boundary Scan (JTAG) Overview This device incorporates a serial boundary scan access port (TAP). This port is designed to operate in a manner consistent with IEEE Standard 1149.1-1990 (commonly referred to as JTAG), but does not implement all of the functions required for IEEE 1149.1 compliance. Certain functions have been modified or eliminated because their implementation places extra delays in the critical speed path of the device. Nevertheless, the device supports the standard TAP controller architecture (the TAP controller is the state machine that controls the TAPs operation) and can be expected to function in a manner that does not conflict with the operation of devices with IEEE Standard 1149.1-compliant TAPs. The TAP operates using LVTTL/LVCMOS logic level signaling. Disabling the JTAG Feature It is possible to use this device without using the JTAG feature. To disable the TAP controller without interfering with normal operation of the device, TCK should be tied LOW (VSS) to prevent clocking the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be pulled up to VCC through a resistor. TDO should be left unconnected. Upon power-up the device will come up in a reset state which will not interfere with the operation of the device. TDI –Test Data In (INPUT) The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP controller state machine and the instruction that is currently loaded in the TAP instruction register (refer to Figure 1). It is allowable to leave this pin unconnected if it is not used in an application. The pin is pulled up internally, resulting in a logic HIGH level. TDI is connected to the most significant bit (MSB) of any register (see Figure 2). TDO – Test Data Out (OUTPUT) The TDO output pin is used to serially clock data-out from the registers. The output that is active depending on the state of the TAP state machine (refer to Figure 1). Output changes in response to the falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO. TDO is connected to the least significant bit (LSB) of any register (see Figure 2). Performing a TAP Reset The TAP circuitry does not have a reset pin (TRST, which is optional in the IEEE 1149.1 specification). A RESET can be performed for the TAP controller by forcing TMS HIGH (VCC) for five rising edges of TCK and pre-loads the instruction register with the IDCODE command. This type of reset does not affect the operation of the system logic. The reset affects test logic only. At power-up, the TAP is reset internally to ensure that TDO is in a High-Z state. Test Access Port (TAP) TCK –Test Clock (INPUT) Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK. TMS – Test Mode Select (INPUT) The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP controller state machine. It is allowable to leave this pin unconnected if the TAP is not used. The pin is pulled up internally, resulting in a logic HIGH level. Test Access Port (TAP) Registers Overview The various TAP registers are selected (one at a time) via the sequences of ones and zeros input to the TMS pin as the TCK is strobed. Each of the TAPs registers are serial shift registers that capture serial input data on the rising edge of TCK and push serial data out on subsequent falling edge of TCK. When a register is selected, it is connected between the TDI and TDO pins. Document #: 38-05022 Rev. *D Page 6 of 21 CY7C1347D Instruction Register The instruction register holds the instructions that are executed by the TAP controller when it is moved into the run test/idle or the various data register states. The instructions are three bits long. The register can be loaded when it is placed between the TDI and TDO pins. The parallel outputs of the instruction register are automatically preloaded with the IDCODE instruction upon power-up or whenever the controller is placed in the test-logic reset state. When the TAP controller is in the Capture-IR state, the two least significant bits of the serial instruction register are loaded with a binary “01” pattern to allow for fault isolation of the board-level serial test data path. Bypass Register The bypass register is a single-bit register that can be placed between TDI and TDO. It allows serial test data to be passed through the device TAP to another device in the scan chain with minimum delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. Boundary Scan Register The Boundary scan register is connected to all the input and bidirectional I/O pins (not counting the TAP pins) on the device. This also includes a number of NC pins that are reserved for future needs. There are a total of 70 bits for x36 device and 51 bits for x18 device. The boundary scan register, under the control of the TAP controller, is loaded with the contents of the device I/O ring when the controller is in Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. The EXTEST, SAMPLE/ PRELOAD and SAMPLE-Z instructions can be used to capture the contents of the I/O ring. The Boundary Scan Order table describes the order in which the bits are connected. The first column defines the bit’s position in the boundary scan register. The MSB of the register is connected to TDI, and LSB is connected to TDO. The second column is the signal name and the third column is the bump number. The third column is the TQFP pin number and the fourth column is the BGA bump number. Identification (ID) Register The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in Capture-DR state with the IDCODE command loaded in the instruction register. The register is then placed between the TDI and TDO pins when the controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins. The code is loaded from a 32-bit on-chip ROM. It describes various attributes of the device as described in the Identification Register Definitions table. The TAP on this device may be used to monitor all input and I/O pads, but can not be used to load address, data, or control signals into the device or to preload the I/O buffers. In other words, the device will not perform IEEE 1149.1 EXTEST, INTEST, or the preload portion of the SAMPLE/PRELOAD command. When the TAP controller is placed in Capture-IR state, the two least significant bits of the instruction register are loaded with 01. When the controller is moved to the Shift-IR state the instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction sets for this device are listed in the following tables. EXTEST EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with all 0s. EXTEST is not implemented in this device. The TAP controller does recognize an all-0 instruction. When an EXTEST instruction is loaded into the instruction register, the device responds as if a SAMPLE/PRELOAD instruction has been loaded. There is one difference between two instructions. Unlike SAMPLE/PRELOAD instruction, EXTEST places the device outputs in a High-Z state. IDCODE The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the ID register when the controller is in Capture-DR mode and places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction loaded in the instruction upon power-up and at any time the TAP controller is placed in the test-logic reset state. SAMPLE-Z If the High-Z instruction is loaded in the instruction register, all output pins are forced to a High-Z state and the boundary scan register is connected between TDI and TDO pins when the TAP controller is in a Shift-DR state. SAMPLE/PRELOAD SAMPLE/PRELOAD is an IEEE 1149.1 mandatory instruction. The PRELOAD portion of the command is not implemented in this device, so the device TAP controller is not fully IEEE 1149.1-compliant. When the SAMPLE/PRELOAD instruction is loaded in the instruction register and the TAP controller is in the Capture-DR state, a snap shot of the data in the device’s input and I/O buffers is loaded into the boundary scan register. Because the device system clock(s) are independent from the TAP clock (TCK), it is possible for the TAP to attempt to capture the input and I/O ring contents while the buffers are in transition (i.e., in a metastable state). Although allowing the TAP to sample metastable inputs will not harm the device, repeatable results can not be expected. To guarantee that the boundary scan register will capture the correct value of a signal, the device input signals must be stabilized long enough to meet the TAP controller’s capture setup plus hold time (tCS plus tCH). The device clock input(s) need not be paused for any other TAP operation except capturing the input and I/O ring contents into the boundary scan register. TAP Controller Instruction Set Overview There are two classes of instructions defined in the IEEE Standard 1149.1-1990; the standard (public) instructions and device specific (private) instructions. Some public instructions are mandatory for IEEE 1149.1 compliance. Optional public instructions must be implemented in prescribed ways. Although the TAP controller in this device follows the IEEE 1149.1 conventions, it is not IEEE 1149.1 compliant because some of the mandatory instructions are not fully implemented. Document #: 38-05022 Rev. *D Page 7 of 21 CY7C1347D Moving the controller to Shift-DR state then places the boundary scan register between the TDI and TDO pins. Because the PRELOAD portion of the command is not implemented in this device, moving the controller to the Update-DR state with the SAMPLE/PRELOAD instruction loaded in the instruction register has the same effect as the Pause-DR command. BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP controller is in the Shift-DR state, the bypass register is placed between TDI and TDO. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. Reserved Do not use these instructions. They are reserved for future use. 1 TEST-LOGIC RESET 0 1 0 REUN-TEST/ IDLE 1 SELECT DR-SCAN 0 1 CAPTURE-DR 0 SHIFT-DR 1 EXIT1-DR 0 PAUSE-DR 1 0 EXIT2-DR 1 UPDATE-DR 1 0 1 SELECT IR-SCAN 0 1 CAPTURE-IR 0 0 SHIFT-IR 1 0 1 EXIT1-IR 0 1 0 PAUSE-IR 1 0 EXIT2-IR 1 UPDATE-IR 1 0 0 Figure 1. TAP Controller State Diagram[8] Note: 8. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document #: 38-05022 Rev. *D Page 8 of 21 CY7C1347D 0 Bypass Register Selection Circuitry TDI Selection Circuitry TDO 2 Instruction Register 1 0 31 30 29 . . 2 1 0 Identification Register x . . . . 2 1 0 Boundary Scan Register [9] TDI TAP Controller TDI Figure 2. TAP Controller Block Diagram TAP DC Electrical Characteristics (20°C < Tj < 110°C; VCC = 3.3V –0.2V and +0.3V unless otherwise noted) Parameter VIH Description Input High (Logic 1) Voltage: Inputs[10, 11] Input High (Logic 1) Voltage: Data[10, 11] VIL ILI ILI ILO VOLC VOHC Test Conditions VCCQ = 3.3 V VCCQ = 2.5V VCCQ = 3.3 V VCCQ = 2.5V Min. 2.0 1.7 2.0 1.7 –0.5 –0.3 –5.0 –30 –5.0 Max. 4.6 4.6 VCCQ + 0.3 VCCQ + 0.3 0.8 0.7 5.0 30 5.0 0.2 VCCQ – 0.2 V V µA µA µA V V Unit V V V Input Low (Logic 0) Voltage: Inputs and VCCQ = 3.3 V Data[10, 11] VCCQ = 2.5V Input Leakage Current TMS and TDI Input Leakage Current Output Leakage Current LVCMOS Output Low Voltage[10, 12] LVCMOS Output High Voltage[10, 12] 0V < VIN < VCC 0V < VIN < VCC Output disabled, 0V < VIN < VCCQ IOLC = 100 µA IOHC = 100 µA Notes: 9. X = 69. 10. All Voltage referenced to VSS (GND). 11. Overshoot: VIH(AC)