CY7C1347G-133BGXC

CY7C1347G 4-Mbit (128 K × 36) Pipelined Sync SRAM 4-Mbit (128 K × 36) Pipelined Sync SRAM Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Functional Description The CY7C1347G[1] is a 3.3 V, 128 K × 36 synchronous pipelined SRAM designed to support zero-wait-state secondary cache with minimal glue logic. CY7C1347G I/O pins can operate at either the 2.5 V or the 3.3 V level. The I/O pins are 3.3 V tolerant when VDDQ = 2.5 V. All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise is 2.6 ns (250 MHz device). CY7C1347G supports either the interleaved burst sequence used by the Intel Pentium processor or a linear burst sequence used by processors such as the PowerPC. The burst sequence is selected through the MODE pin. Accesses can be initiated by asserting either the address strobe from processor (ADSP) or the address strobe from controller (ADSC) at clock rise. Address advancement through the burst sequence is controlled by the ADV input. A 2-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. Byte write operations are qualified with the four Byte Write Select (BW[A:D]) inputs. A global write enable (GW) overrides all byte write inputs and writes data to all four bytes. All writes are conducted with on-chip synchronous self timed write circuitry. Three synchronous chip Selects (CE1, CE2, CE3) and an asynchronous output enable (OE) provide for easy bank selection and output tristate control. To provide proper data during depth expansion, OE is masked during the first clock of a read cycle when emerging from a deselected state. Fully registered inputs and outputs for pipelined operation 128 K × 36 common I/O architecture 3.3 V core power supply (VDD) 2.5- / 3.3-V I/O power supply (VDDQ) Fast clock to output times: 2.6 ns (for 250 MHz device) User selectable burst counter supporting Intel Pentium interleaved or linear burst sequences Separate processor and controller address strobes Synchronous self timed writes Asynchronous output enable Offered in Pb-free 100-pin TQFP, Pb-free and non Pb-free 119-ball BGA package, and 165-ball FBGA package “ZZ” sleep mode option and stop clock option Available in Industrial and commercial temperature ranges Selection Guide Description Maximum access time Maximum operating current Maximum CMOS standby current 250 MHz 2.6 325 40 200 MHz 2.8 265 40 166 MHz 3.5 240 40 133 MHz 4.0 225 40 Unit ns mA mA Note 1. For best practice recommendations, refer to the Cypress application note, SRAM System Guidelines – AN1064. Cypress Semiconductor Corporation Document #: 38-05516 Rev. *I • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised March 29, 2011 [+] Feedback CY7C1347G Logic Block Diagram A0, A1, A ADDRESS REGISTER 2 A [1:0] MODE ADV CLK Q1 ADSC ADSP BW D DQ D ,DQP D BYTE WRITE REGISTER DQ C ,DQP C BYTE WRITE REGISTER DQ B ,DQP B BYTE WRITE REGISTER DQ A ,DQP A BYTE WRITE REGISTER BURST COUNTER CLR AND LOGIC Q0 DQ D ,DQPD BYTE WRITE DRIVER DQ C ,DQP C BYTE WRITE DRIVER DQ B ,DQP B BYTE WRITE DRIVER DQ A ,DQP A BYTE WRITE DRIVER BW C MEMORY ARRAY SENSE AMPS OUTPUT REGISTERS OUTPUT BUFFERS E BW B DQs DQP A DQP B DQP C DQP D BW A BWE GW CE 1 CE 2 CE 3 OE ENABLE REGISTER PIPELINED ENABLE INPUT REGISTERS ZZ SLEEP CONTROL Document #: 38-05516 Rev. *I Page 2 of 24 [+] Feedback CY7C1347G Contents Pin Configurations ........................................................... 4 Pin Definitions .................................................................. 6 Functional Overview ........................................................ 7 Single Read Accesses ................................................ 7 Single Write Accesses Initiated by ADSP ................... 7 Single Write Accesses Initiated by ADSC ................... 7 Burst Sequences ......................................................... 8 Sleep Mode ................................................................. 8 Interleaved Burst Sequence ............................................ 8 Linear Burst Sequence .................................................... 8 ZZ Mode Electrical Characteristics ................................. 8 Truth Table ........................................................................ 8 Partial Truth Table for Read/Write ................................ 10 Maximum Ratings ........................................................... 11 Operating Range ............................................................. 11 Neutron Soft Error Immunity ......................................... 11 Electrical Characteristics ............................................... 11 Capacitance .................................................................... 13 Thermal Resistance ........................................................ 13 Switching Characteristics .............................................. 14 Switching Waveforms .................................................... 15 Ordering Information ...................................................... 19 Ordering Code Definitions ......................................... 19 Package Diagrams .......................................................... 20 Acronyms ........................................................................ 22 Document History Page ................................................. 23 Sales, Solutions, and Legal Information ...................... 24 Worldwide Sales and Design Support ....................... 24 Products .................................................................... 24 PSoC Solutions ......................................................... 24 Document #: 38-05516 Rev. *I Page 3 of 24 [+] Feedback CY7C1347G Pin Configurations Figure 1. 100-pin TQFP Pinout A A CE1 CE2 BWD BWC BWB BWA CE3 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A DQPC DQC DQC VDDQ VSSQ DQC DQC DQC DQC VSSQ VDDQ DQC DQC NC VDD NC VSS DQD DQD VDDQ VSSQ DQD DQD DQD DQD VSSQ VDDQ DQD DQD DQPD 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 BYTE C BYTE D 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 CY7C1347G 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 DQPB DQB DQB VDDQ VSSQ DQB DQB DQB DQB VSSQ VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSSQ DQA DQA DQA DQA VSSQ VDDQ DQA DQA DQPA BYTE B BYTE A Document #: 38-05516 Rev. *I MODE A A A A A1 A0 NC/72M NC/36M VSS VDD NC/18M NC/9M A A A A A A A 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Page 4 of 24 [+] Feedback CY7C1347G Pin Configurations (continued) Figure 2. 119-ball BGA Pinout 1 A B C D E F G H J K L M N P R T U VDDQ NC/288 M NC/144 M DQC DQC VDDQ DQC DQC VDDQ DQD DQD VDDQ DQD DQD NC NC VDDQ 2 A CE2 A DQPC DQC DQC DQC DQC VDD DQD DQD DQD DQD DQPD A NC/72M NC 3 A A A VSS VSS VSS BWC VSS NC VSS BWD VSS VSS VSS MODE A NC 4 ADSP ADSC VDD NC CE1 OE ADV GW VDD CLK NC BWE A1 A0 VDD A NC 5 A A A VSS VSS VSS BWB VSS NC VSS BWA VSS VSS VSS NC A NC 6 A CE3 A DQPB DQB DQB DQB DQB VDD DQA DQA DQA DQA DQPA A NC/36M NC 7 VDDQ NC/576 M NC/1G DQB DQB VDDQ DQB DQB VDDQ DQA DQA VDDQ DQA DQA NC ZZ VDDQ Figure 3. 165-ball FBGA Pinout 1 A B C D E F G H J K L M N P R NC/288 M NC/144 M DQPC DQC DQC DQC DQC NC DQD DQD DQD DQD DQPD NC MODE 2 A A NC DQC DQC DQC DQC VSS DQD DQD DQD DQD NC NC/72 M NC/36 M 3 CE1 CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 4 BWC BWD VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A 5 BWB BWA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC NC NC 6 CE3 CLK 7 BWE GW 8 ADSC OE 9 ADV ADSP 10 A A NC/1G DQB DQB DQB DQB NC DQA DQA DQA DQA NC A A 11 NC NC/576 M DQPB DQB DQB DQB DQB ZZ DQA DQA DQA DQA DQPA NC/9 M A VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC/18M A1 A0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC NC VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A A A Document #: 38-05516 Rev. *I Page 5 of 24 [+] Feedback CY7C1347G Pin Definitions Name A0,A1,A BWA, BWB, BWC, BWD GW BWE CLK CE1 I/O InputSynchronous InputSynchronous InputSynchronous InputSynchronous Input-Clock InputSynchronous InputSynchronous InputSynchronous InputAsynchronous InputSynchronous InputSynchronous Description Address Inputs Used to Select One of the 128 K Address Locations. Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A[1:0] feeds the 2-bit counter. Byte Write Select Inputs, Active LOW. Qualified with BWE to conduct byte writes to the SRAM. Sampled on the rising edge of CLK. Global Write Enable Input, Active LOW. When asserted LOW on the rising edge of CLK, a global write is conducted (ALL bytes are written, regardless of the values on BW[A:D] and BWE). Byte Write Enable Input, Active LOW. Sampled on the rising edge of CLK. This signal must be asserted LOW to conduct a byte write. Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst counter when ADV is asserted LOW, during a burst operation. Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 and CE3 to select or deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only when a new external address is loaded. Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3 to select or deselect the device. CE2 is sampled only when a new external address is loaded. Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select or deselect the device. CE3 is sampled only when a new external address is loaded. Output Enable, Asynchronous Input, Active LOW. Controls the direction of the I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tristated, and act as input data pins. OE is masked during the first clock of a read cycle when emerging from a deselected state. Advance Input Signal, Sampled on the Rising Edge of CLK. When asserted, it automatically increments the address in a burst cycle. Address Strobe from Processor, Sampled on the Rising Edge of CLK. When asserted LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH. Address Strobe from Controller, Sampled on the Rising Edge of CLK. When asserted LOW, addresses presented to the device are captured in the address registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ZZ “Sleep” Input. This active HIGH input places the device in a non-time-critical “sleep” condition with data integrity preserved. During normal operation, this pin must be LOW or left floating. ZZ pin has an internal pull-down. Bidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPs are placed in a tristate condition. Power Supply Inputs to the Core of the Device. Ground for the Core of the Device. Ground for the I/O circuitry. Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDDQ or left floating selects interleaved burst sequence. This is a strap pin and must remain static during device operation. Mode pin has an internal pull-up. CE2 CE3 OE ADV ADSP ADSC InputSynchronous InputAsynchronous I/OSynchronous ZZ DQA, DQB, DQC, DQD, DQPA, DQPB, DQPC, DQPD VDD VSS VDDQ VSSQ MODE Power Supply Ground I/O Ground InputStatic I/O Power Supply Power Supply for the I/O circuitry. Document #: 38-05516 Rev. *I Page 6 of 24 [+] Feedback CY7C1347G Pin Definitions (continued) Name NC, NC/9M, NC/18M, NC/36M, NC/72M, NC/144M, NC/288M, NC/576M, NC/1G I/O – Description No Connects. Not internally connected to the die. NC/9M, NC/18M, NC/36M, NC/72M, NC/144M, NC/288M, NC/576M, and NC/1G are address expansion pins that are not internally connected to the die. Functional Overview All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (tCO) is 2.6 ns (250 MHz device). The CY7C1347G supports secondary cache in systems using either a linear or interleaved burst sequence. The linear burst sequence is suited for processors that use a linear burst sequence. The burst order is user selectable, and is determined by sampling the MODE input. Accesses can be initiated with either the Address Strobe from Processor (ADSP) or the Address Strobe from Controller (ADSC). Address advancement through the burst sequence is controlled by the ADV input. A two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. Byte write operations are qualified with the Byte Write Enable (BWE) and Byte Write Select (BW[A:D]) inputs. A Global Write Enable (GW) overrides all byte write inputs and writes data to all four bytes. All writes are simplified with on-chip synchronous self timed write circuitry. Three synchronous Chip Selects (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output tristate control. ADSP is ignored if CE1 is HIGH. Single Write Accesses Initiated by ADSP This access is initiated when both of the following conditions are satisfied at clock rise: (1) ADSP is asserted LOW, and (2) CE1, CE2, CE3 are all asserted active. The address presented to A[16:0] is loaded into the Address Register and the address advancement logic while being delivered to the RAM core. The write signals (GW, BWE, and BW[A:D]) and ADV inputs are ignored during this first cycle. ADSP-triggered write accesses require two clock cycles to complete. If GW is asserted LOW on the second clock rise, the data presented to the DQs and DQPs inputs is written into the corresponding address location in the RAM core. If GW is HIGH, then the write operation is controlled by BWE and BW[A:D] signals. The CY7C1347G provides byte write capability that is described in Partial Truth Table for Read/Write on page 10. Asserting the Byte Write Enable input (BWE) with the selected Byte Write (BW[A:D]) input selectively writes to only the desired bytes. Bytes not selected during a byte write operation remain unaltered. A synchronous self timed write mechanism is provided to simplify the write operations. Because the CY7C1347G is a common I/O device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQs and DQPs inputs. Doing so tristates the output drivers. As a safety precaution, DQs and DQPs are automatically tristated whenever a write cycle is detected, regardless of the state of OE. Single Read Accesses This access is initiated when the following conditions are satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2) CE1, CE2, CE3 are all asserted active, and (3) the write signals (GW, BWE) are all deasserted HIGH. ADSP is ignored if CE1 is HIGH. The address presented to the address inputs (A[16:0]) is stored into the address advancement logic and the Address Register while being presented to the memory core. The corresponding data is allowed to propagate to the input of the Output Registers. At the rising edge of the next clock the data is allowed to propagate through the Output Register and onto the data bus within 2.6 ns (250 MHz device) if OE is active LOW. The only exception occurs when the SRAM is emerging from a deselected state to a selected state, its outputs are always tristated during the first cycle of the access. After the first cycle of the access, the outputs are controlled by the OE signal. Consecutive single read cycles are supported. After the SRAM is deselected at clock rise by the chip select and either ADSP or ADSC signals, its output tristates immediately. Single Write Accesses Initiated by ADSC ADSC write accesses are initiated when the following conditions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deasserted HIGH, (3) CE1, CE2, CE3 are all asserted active, and (4) the appropriate combination of the write inputs (GW, BWE, and BW[A:D]) are asserted active to conduct a write to the desired byte(s). ADSC-triggered write accesses require a single clock cycle to complete. The address presented to A[16:0] is loaded into the address register and the address advancement logic while being delivered to the RAM core. The ADV input is ignored during this cycle. If a global write is conducted, the data presented to the DQs and DQPs is written into the corresponding address location in the RAM core. If a byte write is conducted, only the selected bytes are written. Bytes not selected during a byte write operation remain unaltered. A synchronous self timed write mechanism has been provided to simplify the write operations. Because the CY7C1347G is a common I/O device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQs and DQPs inputs. Doing so tristates the output Page 7 of 24 Document #: 38-05516 Rev. *I [+] Feedback CY7C1347G drivers. As a safety precaution, DQs and DQPs are automatically tristated whenever a write cycle is detected, regardless of the state of OE. Interleaved Burst Sequence First Address A[1:0] 00 01 10 11 01 00 11 10 Second Address A[1:0] 10 11 00 01 Third Address A[1:0] 11 10 01 00 Fourth Address A[1:0] Burst Sequences The CY7C1347G provides a two-bit wraparound counter, fed by A[1:0], that implements either an interleaved or linear burst sequence. The interleaved burst sequence is designed specifically to support Intel Pentium applications. The linear burst sequence is designed to support processors that follow a linear burst sequence. The burst sequence is user-selectable through the MODE input. Asserting ADV LOW at clock rise automatically increments the burst counter to the next address in the burst sequence. Both read and write burst operations are supported. Linear Burst Sequence First Address A[1:0] 00 01 10 11 01 10 11 00 Second Address A[1:0] 10 11 00 01 Third Address A[1:0] 11 00 01 10 Fourth Address A[1:0] Sleep Mode The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected before entering the “sleep” mode. CE1, CE2, CE3, ADSP, and ADSC must remain inactive for the duration of tZZREC after the ZZ input returns LOW. ZZ Mode Electrical Characteristics Parameter IDDZZ tZZS tZZREC tZZI tRZZI Description Snooze mode standby current Device operation to ZZ ZZ recovery time ZZ Active to snooze current ZZ Inactive to exit snooze current Test Conditions ZZ > VDD 0.2 V ZZ > VDD  0.2 V ZZ < 0.2 V This parameter is sampled This parameter is sampled Min – – 2tCYC – 0 Max 40 2tCYC – 2tCYC – Unit mA ns ns ns ns Truth Table The truth table for part number CY7C1347G follow. [2, 3, 4, 5, 6] Next Cycle Deselect cycle, power-down Deselect cycle, power-down Deselect cycle, power-down Deselect cycle, power-down Deselect cycle, power-down Add. Used None None None None None CE1 H L L L L CE2 X L X L X CE3 X X H X H ZZ L L L L L ADSP ADSC ADV WRITE X L L H H L X X L L X X X X X X X X X X OE X X X X X CLK DQ L-H Tristate L-H Tristate L-H Tristate L-H Tristate L-H Tristate Notes 2. X = “Do not Care.” H = Logic HIGH, L = Logic LOW. 3. WRITE = L when any one or more Byte Write Enable signals (BWA, BWB, BWC, BWD) and BWE = L or GW = L. WRITE = H when all Byte Write Enable signals (BWA, BWB, BWC, BWD), BWE, GW = H. 4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock. 5. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW[A:D]. Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH before the start of the write cycle to allow the outputs to tristate. OE is a do not care for the remainder of the write cycle. 6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tristate when OE is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW). Document #: 38-05516 Rev. *I Page 8 of 24 [+] Feedback CY7C1347G Truth Table (continued) The truth table for part number CY7C1347G follow. [2, 3, 4, 5, 6] Next Cycle Snooze mode, power-down Read Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Begin Burst Read Cycle, Begin Burst Read Cycle, Begin Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Write cycle, continue burst Write cycle, continue burst Read cycle, suspend burst Read cycle, suspend burst Read cycle, suspend burst Read cycle, suspend burst Write cycle, suspend burst Write cycle, suspend burst Add. Used None External External External External External Next Next Next Next Next Next Current Current Current Current Current Current CE1 X L L L L L X X H H X H X X H H X H CE2 X H H H H H X X X X X X X X X X X X CE3 X L L L L L X X X X X X X X X X X X ZZ H L L L L L L L L L L L L L L L L L ADSP ADSC ADV WRITE X L L H H H H H X X H X H H X X H X X X X L L L H H H H H H H H H H H H X X X X X X L L L L L L H H H H H H X X X L H H H H H H L L H H H H L L OE X L H X L H H L L H X X L H L H X X CLK X DQ Tristate L-H Q L-H Tristate L-H D L-H Q L-H Tristate L-H Tristate L-H Q L-H Q L-H Tristate L-H D L-H D L-H Q L-H Tristate L-H Q L-H Tristate L-H D L-H D Document #: 38-05516 Rev. *I Page 9 of 24 [+] Feedback CY7C1347G Partial Truth Table for Read/Write The partial truth table for read/write for part number CY7C1347G follow. [7, 8] Function Read Read Write byte A – DQA Write byte B – DQB Write bytes B, A Write byte C – DQC Write bytes C, A Write bytes C, B Write bytes C, B, A Write byte D – DQD Write bytes D, A Write bytes D, B Write bytes D, B, A Write bytes D, C Write bytes D, C, A Write bytes D, C, B Write all bytes Write all bytes GW H H H H H H H H H H H H H H H H H L BWE H L L L L L L L L L L L L L L L L X BWD X H H H H H H H H L L L L L L L L X BWC X H H H H L L L L H H H H L L L L X BWB X H H L L H H L L H H L L H H L L X BWA X H L H L H L H L H L H L H L H L X Notes 7. X = “Do not Care.” H = Logic HIGH, L = Logic LOW. 8. This table is only a partial listing of the byte write combinations. Any combination of BWx is valid. Appropriate write is based on which byte write is active. Document #: 38-05516 Rev. *I Page 10 of 24 [+] Feedback CY7C1347G Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Storage temperature 65 C to +150 C Ambient temperature with power applied 55 C to +125 C Supply voltage on VDD relative to GND  0.5 V to +4.6 V Supply voltage on VDDQ relative to GND0.5 V to +VDD DC voltage applied to outputs in high Z State  0.5 V to VDD + 0.5 V DC input voltage  0.5 V to VDD + 0.5 V Current into outputs (LOW) ......................................... 20 mA Static discharge voltage.......................................... > 2001 V (MIL-STD-883, Method 3015) Latch-up Current.................................................... > 200 mA Neutron Soft Error Immunity Parameter LSBU Description Logical single-bit upsets Logical multi-bit upsets Single event latch-up Test Conditions 25 °C Typ 361 Max* 394 Unit FIT/ Mb FIT/ Mb FIT/ Dev LMBU 25 °C 0 0.01 SEL 85 °C 0 0.1 * No LMBU or SEL events occurred during testing; this column represents a statistical 2, 95% confidence limit calculation. For more details refer to Application Note, Accelerated Neutron SER Testing and Calculation of Terrestrial Failure Rates – AN54908. Operating Range Range Commercial Industrial Ambient Temperature 0 °C to +70 °C –40 °C to +85 °C VDD VDDQ 3.3 V5% / 2.5 V  + 10% 5% to VDD Electrical Characteristics Over the Operating Range[9, 10] Parameter VDD VDDQ VOH VOL VIH VIL IX Description Power supply voltage I/O supply voltage Output HIGH voltage Output LOW voltage Input HIGH voltage[9] [9] Test Conditions Min 3.135 2.375 Max 3.6 VDD – – 0.4 0.4 VDD + 0.3 V VDD + 0.3 V 0.8 0.7 5 – 5 – 30 5 Unit V V V V V V V V V V A A A A A A For 3.3 V I/O, IOH = –4.0 mA For 2.5 V I/O, IOH = –1.0 mA For 3.3 V I/O, IOL = 8.0 mA For 2.5 V I/O, IOL = 1.0 mA For 3.3 V I/O For 2.5 V I/O For 3.3 V I/O For 2.5 V I/O GND < VI < VDDQ Input = VSS Input = VDD Input = VSS Input = VDD GND  VI  VDDQ, output disabled 2.4 2.0 – – 2.0 1.7 –0.3 –0.3 5 30 – 5 – 5 Input LOW voltage Input leakage current except ZZ and MODE Input current of MODE Input current of ZZ IOZ Output leakage current Notes 9. Overshoot: VIH(AC) < VDD +1.5 V (pulse width less than tCYC/2). Undershoot: VIL(AC) > –2 V (pulse width less than tCYC/2). 10. tpower-up: assumes a linear ramp from 0V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD. Document #: 38-05516 Rev. *I Page 11 of 24 [+] Feedback CY7C1347G Electrical Characteristics (continued) Over the Operating Range[9, 10] Parameter IDD Description VDD operating supply current Test Conditions VDD = Max., IOUT = 0 mA, f = fMAX = 1/tCYC 4 ns cycle, 250 MHz 5 ns cycle, 200 MHz 6 ns cycle, 166 MHz 7.5 ns cycle, 133 MHz ISB1 Automatic CE power-down current—TTL inputs Max. VDD, device deselected, VIN > VIH or VIN < VIL f = fMAX = 1/tCYC 4 ns cycle, 250 MHz 5 ns cycle, 200 MHz 6 ns cycle, 166 MHz 7.5 ns cycle, 133 MHz ISB2 ISB3 Automatic CE power-down current—CMOS inputs Automatic CE power-down current—CMOS inputs All speeds Max. VDD, device deselected, VIN < 0.3 V or VIN > VDDQ – 0.3 V, f=0 Max. VDD, device deselected, or 4 ns cycle, 250 MHz VIN < 0.3 V or VIN > VDDQ – 0.3 V 5 ns cycle, 200 MHz f = fMAX = 1/tCYC 6 ns cycle, 166 MHz 7.5 ns cycle, 133 MHz ISB4 Automatic CE power-down current—TTL inputs Max. VDD, device deselected, VIN  VIH or VIN  VIL, f = 0 Min – – – – – – – – – Max 325 265 240 225 120 110 100 90 40 Unit mA mA mA mA mA mA mA mA mA – – – – – 105 95 85 75 45 mA mA mA mA mA Document #: 38-05516 Rev. *I Page 12 of 24 [+] Feedback CY7C1347G Capacitance Tested initially and after any design or process changes that may affect these parameters. Parameter CIN CCLK CIO Description Input capacitance Clock input capacitance I/O capacitance Test Conditions TA = 25 C, f = 1 MHz, VDD = 3.3 V. VDDQ = 3.3 V 100-pin TQFP 119-ball BGA 165-ball FBGA Unit Max Max Max 5 5 5 5 5 7 5 5 7 pF pF pF Thermal Resistance Tested initially and after any design or process changes that may affect these parameters. Parameter JA JC Description Thermal resistance (junction to ambient) Thermal resistance (junction to case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51. 100-pin TQFP 119-ball BGA 165-ball FBGA Unit Package Package Package 30.32 6.85 34.1 14.0 20.3 4.6 C/W C/W Figure 4. AC Test Loads and Waveforms 3.3 V I/O Test Load OUTPUT Z0 = 50  3.3 V OUTPUT RL = 50  R = 317  VDDQ 5 pF GND R = 351  10% All input pulses 90% 90% 10%  1 ns  1 ns VT = 1.5 V (a) 2.5 V I/O Test Load OUTPUT Z0 = 50  2.5 V Including JIG and scope (b) R = 1667  VDDQ (c) All input pulses 10% 90% 90% 10%  1 ns OUTPUT RL = 50  VT = 1.25 V 5 pF GND R = 1538  (a) Including JIG and scope  1 ns (b) (c) Document #: 38-05516 Rev. *I Page 13 of 24 [+] Feedback CY7C1347G Switching Characteristics Over the Operating Range[11, 12] Parameter tPOWER Clock tCYC tCH tCL Output Times tCO tDOH tCLZ tCHZ tOEV tOELZ tOEHZ Setup Times tAS tADS tADVS tWES tDS tCES Hold Times tAH tADH tADVH tWEH tDH tCEH Address hold after CLK rise ADSP, ADSC hold after CLK rise ADV hold after CLK Rise GW, BWE, BWX hold after CLK rise Data input hold after CLK rise Chip enable hold after CLK rise 0.3 0.3 0.3 0.3 0.3 0.3 – – – – – – 0.5 0.5 0.5 0.5 0.5 0.5 – – – – – – 0.5 0.5 0.5 0.5 0.5 0.5 – – – – – – 0.5 0.5 0.5 0.5 0.5 0.5 – – – – – – ns ns ns ns ns ns Address setup before CLK rise ADSC, ADSP setup before CLK rise ADV setup before CLK rise GW, BWE, BWX setup before CLK rise Data input setup before CLK rise Chip enable setup before CLK rise 1.2 1.2 1.2 1.2 1.2 1.2 – – – – – – 1.2 1.2 1.2 1.2 1.2 1.2 – – – – – – 1.5 1.5 1.5 1.5 1.5 1.5 – – – – – – 1.5 1.5 1.5 1.5 1.5 1.5 – – – – – – ns ns ns ns ns ns Data output valid after CLK rise Data output hold after CLK rise Clock to low Z[14, 15, 16] Clock to high Z[14, 15, 16] OE LOW to output valid OE LOW to output low Z[14, 15, 16] OE HIGH to output high Z[14, 15, 16] – 1.0 0 – – 0 – 2.6 – – 2.6 2.6 – 2.6 – 1.0 0 – – 0 – 2.8 – – 2.8 2.8 – 2.8 – 1.5 0 – – 0 – 3.5 – – 3.5 3.5 – 3.5 – 1.5 0 – – 0 – 4.0 – – 4.0 4.5 – 4.0 ns ns ns ns ns ns ns Clock cycle time Clock HIGH Clock LOW 4.0 1.7 1.7 – – – 5.0 2.0 2.0 – – – 6.0 2.5 2.5 – – – 7.5 3.0 3.0 – – – ns ns ns Description VDD(Typical) to the first Access[13] –250 Min 1 Max – 1 –200 Min Max – 1 –166 Min Max – 1 –133 Min Max – Unit ms Notes 11. Timing references level is 1.5 V when VDDQ = 3.3 V and is 1.25 V when VDDQ = 2.5 V on all datasheets. 12. Test conditions shown in (a) of Figure 4 on page 13 unless otherwise noted. 13. This part has an internal voltage regulator; tPOWER is the time that the power must be supplied above VDD(min) initially before a read or write operation can be initiated. 14. tCHZ, tCLZ, tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of Figure 4 on page 13. Transition is measured ±200 mV from steady-state voltage. 15. At any voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High Z before Low Z under the same system conditions. 16. This parameter is sampled and not 100% tested. Document #: 38-05516 Rev. *I Page 14 of 24 [+] Feedback CY7C1347G Switching Waveforms Figure 5. Read Cycle Timing[17] t CYC CLK t CH t CL t ADS t ADH ADSP t ADS tADH ADSC t AS tAH ADDRESS A1 t WES tWEH A2 A3 Burst continued with new base address GW, BWE, BW [A:D] t CES tCEH Deselect cycle CE t ADVS tADVH ADV ADV suspends burst. t OEV t OEHZ t CLZ t OELZ t CO t DOH t CHZ OE D ata Out (Q) High-Z Q(A1) t CO Q(A2) Q(A2 + 1) Q(A2 + 2) Q(A2 + 3) Q(A2) Q(A2 + 1) Single READ DON’T CARE UNDEFINED BURST READ Burst wraps around to its initial state Note 17. In this diagram, when CE is LOW, CE1 is LOW, CE2 is HIGH, and CE3 is LOW. When CE is HIGH, CE1 is HIGH, CE2 is LOW, or CE3 is HIGH. Document #: 38-05516 Rev. *I Page 15 of 24 [+] Feedback CY7C1347G Switching Waveforms (continued) Figure 6. Write Cycle Timing[18, 19] t CYC CLK tCH t ADS ADSP ADSC extends burst t ADS tADH tADH tCL t ADS ADSC t AS A1 tAH tADH ADDRESS A2 Byte write signals are ignored for first cycle when ADSP initiates burst A3 t WES tWEH BWE, BW[A :B] t WES tWEH GW t CES CE t t ADVS ADVH ADV ADV suspends burst tCEH OE t DS tDH Data In (D) High-Z t OEHZ D(A1) D(A2) D(A2 + 1) D(A2 + 1) D(A2 + 2) D(A2 + 3) D(A3) D(A3 + 1) D(A3 + 2) D ata Out (Q) BURST READ Single WRITE BURST WRITE Extended BURST WRITE DON’T CARE UNDEFINED Notes 18. In this diagram, when CE is LOW, CE1 is LOW, CE2 is HIGH, and CE3 is LOW. When CE is HIGH, CE1 is HIGH, CE2 is LOW, or CE3 is HIGH. 19. Full width write can be initiated by either GW LOW, or by GW HIGH, BWE LOW, and BWx LOW. Document #: 38-05516 Rev. *I Page 16 of 24 [+] Feedback CY7C1347G Switching Waveforms (continued) Figure 7. Read/Write Cycle Timing[20, 21, 22] tCYC CLK tCH t ADS ADSP tADH tCL ADSC t AS tAH ADDRESS A1 A2 A3 t WES tWEH A4 A5 A6 BWE, BW[A:D] t CES CE tCEH ADV OE tCO t DS tDH t OELZ Data In (D) High-Z tCLZ D ata Out (Q) High-Z Q(A1) Back-to-Back READs tOEHZ Q(A2) Single WRITE D(A3) D(A5) D(A6) Q(A4) Q(A4+1) BURST READ Q(A4+2) Q(A4+3) Back-to-Back WRITEs DON’T CARE UNDEFINED Notes 20. In this diagram, when CE is LOW, CE1 is LOW, CE2 is HIGH, and CE3 is LOW. When CE is HIGH, CE1 is HIGH, CE2 is LOW, or CE3 is HIGH. 21. The data bus (Q) remains in High Z following a write cycle, unless a new read access is initiated by ADSP or ADSC. 22. GW is HIGH. Document #: 38-05516 Rev. *I Page 17 of 24 [+] Feedback CY7C1347G Switching Waveforms (continued) Figure 8. ZZ Mode Timing[23, 24] CLK t ZZ t ZZREC ZZ t ZZI I SUPPLY I DDZZ t RZZI DESELECT or READ Only A LL INPUTS (except ZZ) Outputs (Q) High-Z DON’T CARE Notes 23. Device must be deselected when entering ZZ mode. See Truth Table on page 8 for all possible signal conditions to deselect the device. 24. DQs are in High Z when exiting ZZ sleep mode. Document #: 38-05516 Rev. *I Page 18 of 24 [+] Feedback CY7C1347G Ordering Information The table below contains only the parts that are currently available. If you don’t see what you are looking for, please contact your local sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office closest to you, visit us at http://www.cypress.com/go/datasheet/offices Speed (MHz) 133 166 200 250 Ordering Code CY7C1347G-133AXC CY7C1347G-133BGXC CY7C1347G-166AXC CY7C1347G-200AXC CY7C1347G-250AXC Package Diagram Package Type Operating Range Commercial Commercial Commercial Commercial 51-85050 100-pin Thin Quad Flat Pack (14 × 20 × 1.4 mm) Pb-free 51-85115 119-ball Ball Grid Array (14 × 22 × 2.4 mm) Pb-free 51-85050 100-pin Thin Quad Flat Pack (14 × 20 × 1.4 mm) Pb-free 51-85050 100-pin Thin Quad Flat Pack (14 × 20 × 1.4 mm) Pb-free 51-85050 100-pin Thin Quad Flat Pack (14 × 20 × 1.4 mm) Pb-free Ordering Code Definitions CY 7C 1347 G - XXX XXX C Temperature range: C = Commercial Package Type: AX = 100-pin TQFP (Pb-free) BGX = 119-ball BGA (Pb-free) Speed Grade: XXX = 133 MHz or 166 MHz or 200 MHz or 250 MHz Process Technology  90 nm 1347 = SCD, 128 K × 36 (4 Mb) Marketing Code: 7C = SRAMs Company ID: CY = Cypress Document #: 38-05516 Rev. *I Page 19 of 24 [+] Feedback CY7C1347G Package Diagrams Figure 9. 100-pin TQFP (14 × 20 × 1.4 mm) 51-85050 *D Document #: 38-05516 Rev. *I Page 20 of 24 [+] Feedback CY7C1347G Package Diagrams (continued) Figure 10. 119-ball BGA (14 × 22 × 2.4 mm) 51-85115 *C Document #: 38-05516 Rev. *I Page 21 of 24 [+] Feedback CY7C1347G Package Diagrams (continued) Figure 11. 165-ball FBGA (13 × 15 × 1.4 mm) 51-85180 *C Acronyms Acronym DDR FBGA HSTL JEDEC JTAG ODT PLL QDR TAP TCK TDO TDI TMS double data rate fine-pitch ball grid array high-speed transceiver logic joint electron device engineering council joint test action group on-die termination phase-locked loop quad data rate test access port test clock test data out test data in test mode select Description Document #: 38-05516 Rev. *I Page 22 of 24 [+] Feedback CY7C1347G Document History Page Document Title: CY7C1347G 4-Mbit (128 K × 36) Pipelined Sync SRAM Document Number: 38-05516 Revision ** *A *B ECN 224364 276690 333625 Orig. of Change RKF VBL SYT Submission Description of Change Date See ECN See ECN See ECN New datasheet Changed TQFP package in Ordering Information section to Pb-Free TQFP Added comment of BG and BZ Pb-Free package availability Removed 225 MHz and 100 MHz speed grades Modified Address Expansion balls in the pinouts for 100 TQFP Package as per JEDEC standards and updated the Pin Definitions accordingly Modified VOL, VOH test conditions Replaced TBDs for JA and JC to their respective values on the Thermal Resistance table Changed the package name for 100 TQFP from A100RA to A101 Removed comment on the availability of BG Pb-Free package Updated the Ordering Information by shading and unshading MPNs as per availability Converted from Preliminary to Final. Changed address of Cypress Semiconductor Corporation on Page #1 from “3901 North First Street” to “198 Champion Court” Swapped typo CE2 and CE3 in the Truth Table column heading on Page #6 Modified test condition from VIH < VDD to VIH VDD. Modified test condition from VDDQ < VDD to VDDQ < VDD Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the Electrical Characteristics Table. Replaced Package Name column with Package Diagram in the Ordering Information table. Replaced Package Diagram of 51-85050 from *A to *B Replaced Package Diagram of 51-85180 from ** to *A Updated the Ordering Information. Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND. Updated the Ordering Information table. Corrected write timing diagram on page 12 Updated Ordering Information and data sheet template. Included Soft Error Immunity Data Modified Ordering Information table by including parts that are available and modified the disclaimer for the Ordering information. Updated Package Diagram for spec 51-85180. Template update. Updated package diagrams to latest revision. 51-85050 – *B to *C 51-85115 – *B to *C 51-85180 – *B to *C Updated Ordering Information and added Ordering Code Definitions. Updated Package Diagrams. *C 419256 RXU See ECN *D *E *F *G 480124 1078184 2756998 VKN VKN VKN See ECN See ECN 01/15/09 08/28/09 2633279 NXR/AESA *H 2998771 NJY 08/02/10 *I 3208774 NJY 03/29/2011 Document #: 38-05516 Rev. *I Page 23 of 24 [+] Feedback CY7C1347G Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5 © Cypress Semiconductor Corporation, 2004-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-05516 Rev. *I Revised March 29, 2011 Page 24 of 24 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback