CY7C1347G
4-Mbit (128K × 36) Pipelined Sync SRAM
4-Mbit (128K × 36) Pipelined Sync SRAM
Features
Functional Description
■
Fully registered inputs and outputs for pipelined operation
■
128K × 36 common I/O architecture
■
3.3 V core power supply (VDD)
■
2.5 V/ 3.3 V I/O power supply (VDDQ)
■
Fast clock to output times: 2.6 ns (for 250 MHz device)
■
User selectable burst counter supporting Intel Pentium
interleaved or linear burst sequences
■
Separate processor and controller address strobes
■
Synchronous self timed writes
■
Asynchronous output enable
■
Offered in Pb-free 100-pin TQFP package
■
“ZZ” sleep mode option and stop clock option
■
Available in commercial and industrial temperature range
The CY7C1347G is a 3.3 V, 128K × 36 synchronous pipelined
SRAM designed to support zero-wait-state secondary cache
with minimal glue logic. CY7C1347G I/O pins can operate at
either the 2.5 V or the 3.3 V level. The I/O pins are 3.3 V tolerant
when VDDQ = 2.5 V. All synchronous inputs pass through input
registers controlled by the rising edge of the clock. All data
outputs pass through output registers controlled by the rising
edge of the clock. Maximum access delay from the clock rise is
2.6 ns (250 MHz device). CY7C1347G supports either the
interleaved burst sequence used by the Intel Pentium processor
or a linear burst sequence used by processors such as the
PowerPC. The burst sequence is selected through the MODE
pin. Accesses can be initiated by asserting either the address
strobe from processor (ADSP) or the address strobe from
controller (ADSC) at clock rise. Address advancement through
the burst sequence is controlled by the ADV input. A 2-bit on-chip
wraparound burst counter captures the first address in a burst
sequence and automatically increments the address for the rest
of the burst access.
Byte write operations are qualified with the four Byte Write Select
(BW[A:D]) inputs. A global write enable (GW) overrides all byte
write inputs and writes data to all four bytes. All writes are
conducted with on-chip synchronous self timed write circuitry.
Three synchronous chip Selects (CE1, CE2, CE3) and an
asynchronous output enable (OE) provide for easy bank
selection and output tristate control. To provide proper data
during depth expansion, OE is masked during the first clock of a
read cycle when emerging from a deselected state.
For a complete list of related documentation, click here.
Selection Guide
Description
250 MHz
200 MHz
166 MHz
133 MHz
Unit
Maximum access time
2.6
2.8
3.5
4.0
ns
Maximum operating current
325
265
240
225
mA
Maximum CMOS standby current
40
40
40
40
mA
Errata: For information on silicon errata, see "Errata" on page 22. Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation
Document Number: 38-05516 Rev. *S
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised January 23, 2018
CY7C1347G
Logic Block Diagram
A0, A1, A
ADDRESS
REGISTER
2
A [1:0]
MODE
ADV
CLK
Q1
BURST
COUNTER
CLR AND
LOGIC
ADSC
Q0
ADSP
BW D
DQ D ,DQP D
BYTE
WRITE REGISTER
DQ D ,DQPD
BYTE
WRITE DRIVER
BW C
DQ C ,DQP C
BYTE
WRITE REGISTER
DQ C ,DQP C
BYTE
WRITE DRIVER
DQ B ,DQP B
BYTE
WRITE REGISTER
DQ B ,DQP B
BYTE
WRITE DRIVER
BW B
BW A
BWE
ZZ
ENABLE
REGISTER
SENSE
AMPS
OUTPUT
REGISTERS
OUTPUT
BUFFERS
E
DQs
DQP A
DQP B
DQP C
DQP D
DQ A ,DQP A
BYTE
WRITE DRIVER
DQ A ,DQP A
BYTE
WRITE REGISTER
GW
CE 1
CE 2
CE 3
OE
MEMORY
ARRAY
PIPELINED
ENABLE
INPUT
REGISTERS
SLEEP
CONTROL
Document Number: 38-05516 Rev. *S
Page 2 of 26
CY7C1347G
Contents
Pin Configurations ........................................................... 4
Pin Definitions .................................................................. 5
Functional Overview ........................................................ 7
Single Read Accesses ................................................ 7
Single Write Accesses Initiated by ADSP ................... 7
Single Write Accesses Initiated by ADSC ................... 7
Burst Sequences ......................................................... 7
Sleep Mode ................................................................. 8
Interleaved Burst Sequence ........................................ 8
Linear Burst Sequence ................................................ 8
ZZ Mode Electrical Characteristics .............................. 8
Truth Table ........................................................................ 9
Partial Truth Table for Read/Write ................................ 10
Maximum Ratings ........................................................... 11
Operating Range ............................................................. 11
Neutron Soft Error Immunity ......................................... 11
Electrical Characteristics ............................................... 11
Capacitance .................................................................... 13
Thermal Resistance ........................................................ 13
AC Test Loads and Waveforms ..................................... 13
Document Number: 38-05516 Rev. *S
Switching Characteristics .............................................. 14
Switching Waveforms .................................................... 15
Ordering Information ...................................................... 19
Ordering Code Definitions ......................................... 19
Package Diagrams .......................................................... 20
Acronyms ........................................................................ 21
Document Conventions ................................................. 21
Units of Measure ....................................................... 21
Errata ............................................................................... 22
Part Numbers Affected .............................................. 22
Product Status ........................................................... 22
Ram9 Sync ZZ Pin Issues Errata Summary .............. 22
Document History Page ................................................. 23
Sales, Solutions, and Legal Information ...................... 26
Worldwide Sales and Design Support ....................... 26
Products .................................................................... 26
PSoC® Solutions ...................................................... 26
Cypress Developer Community ................................. 26
Technical Support ..................................................... 26
Page 3 of 26
CY7C1347G
Pin Configurations
BYTE C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1347G
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPB
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSSQ
DQA
DQA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
DQPA
BYTE B
BYTE A
MODE
A
A
A
A
A1
A0
NC/72M
NC/36M
VSS
VDD
NC/18M
NC/9M
A
A
A
A
A
A
A
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
BYTE D
DQPC
DQC
DQC
VDDQ
VSSQ
DQC
DQC
DQC
DQC
VSSQ
VDDQ
DQC
DQC
NC
VDD
NC
VSS
DQD
DQD
VDDQ
VSSQ
DQD
DQD
DQD
DQD
VSSQ
VDDQ
DQD
DQD
DQPD
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
CE1
CE2
BWD
BWC
BWB
BWA
CE3
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout [1]
Note
1. Errata: The ZZ pin (Pin 64) needs to be externally connected to ground. For more information, see "Errata" on page 22.
Document Number: 38-05516 Rev. *S
Page 4 of 26
CY7C1347G
Pin Definitions
Name
A0, A1, A
I/O
Description
InputAddress Inputs Used to Select One of the 128 K Address Locations. Sampled at the rising edge of
Synchronous the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A[1:0] feeds the
2-bit counter.
BWA, BWB,
InputByte Write Select Inputs, Active LOW. Qualified with BWE to conduct byte writes to the SRAM.
BWC, BWD Synchronous Sampled on the rising edge of CLK.
GW
InputGlobal Write Enable Input, Active LOW. When asserted LOW on the rising edge of CLK, a global write
Synchronous is conducted (ALL bytes are written, regardless of the values on BW[A:D] and BWE).
BWE
InputByte Write Enable Input, Active LOW. Sampled on the rising edge of CLK. This signal must be asserted
Synchronous LOW to conduct a byte write.
CLK
Input-Clock
Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst
counter when ADV is asserted LOW, during a burst operation.
CE1
InputChip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2
Synchronous and CE3 to select or deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only when a
new external address is loaded.
CE2
InputChip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1
Synchronous and CE3 to select or deselect the device. CE2 is sampled only when a new external address is loaded.
CE3
InputChip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1
Synchronous and CE2 to select or deselect the device. CE3 is sampled only when a new external address is loaded.
OE
InputOutput Enable, Asynchronous Input, Active LOW. Controls the direction of the I/O pins. When LOW,
Asynchronous the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tristated, and act as input data
pins. OE is masked during the first clock of a read cycle when emerging from a deselected state.
ADV
InputAdvance Input Signal, Sampled on the Rising Edge of CLK. When asserted, it automatically
Synchronous increments the address in a burst cycle.
ADSP
InputAddress Strobe from Processor, Sampled on the Rising Edge of CLK. When asserted LOW,
Synchronous addresses presented to the device are captured in the address registers. A[1:0] are also loaded into the
burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored
when CE1 is deasserted HIGH.
ADSC
InputAddress Strobe from Controller, Sampled on the Rising Edge of CLK. When asserted LOW,
Synchronous addresses presented to the device are captured in the address registers. A[1:0] are also loaded into the
burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized.
Document Number: 38-05516 Rev. *S
Page 5 of 26
CY7C1347G
Pin Definitions (continued)
Name
ZZ
[2]
I/O
Description
InputZZ “Sleep” Input. This active HIGH input places the device in a non-time-critical “sleep” condition with
Asynchronous data integrity preserved. During normal operation, this pin must be LOW or left floating. ZZ pin has an
internal pull-down.
DQA, DQB,
I/OBidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that is triggered by the
DQC, DQD, Synchronous rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the
addresses presented during the previous clock rise of the read cycle. The direction of the pins is
DQPA,
DQPB,
controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPs
DQPC,
are placed in a tristate condition.
DQPD
VDD
Power Supply Power Supply Inputs to the Core of the Device.
Ground
Ground for the Core of the Device.
VDDQ
I/O Power
Supply
Power Supply for the I/O circuitry.
VSSQ
I/O Ground
Ground for the I/O circuitry.
VSS
MODE
NC,
NC/9M,
NC/18M,
NC/36M,
NC/72M,
NC/144M,
NC/288M,
NC/576M,
NC/1G
InputStatic
Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDDQ or left floating
selects interleaved burst sequence. This is a strap pin and must remain static during device operation.
Mode pin has an internal pull-up.
–
No Connects. Not internally connected to the die. NC/9M, NC/18M, NC/36M, NC/72M, NC/144M,
NC/288M, NC/576M, and NC/1G are address expansion pins that are not internally connected to the die.
Note
2. Errata: The ZZ pin needs to be externally connected to ground. For more information, see "Errata" on page 22.
Document Number: 38-05516 Rev. *S
Page 6 of 26
CY7C1347G
Functional Overview
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. Maximum
access delay from the clock rise (tCO) is 2.6 ns (250 MHz device).
The CY7C1347G supports secondary cache in systems using
either a linear or interleaved burst sequence. The linear burst
sequence is suited for processors that use a linear burst
sequence. The burst order is user selectable, and is determined
by sampling the MODE input. Accesses can be initiated with
either the Address Strobe from Processor (ADSP) or the Address
Strobe from Controller (ADSC). Address advancement through
the burst sequence is controlled by the ADV input. A two-bit
on-chip wraparound burst counter captures the first address in a
burst sequence and automatically increments the address for the
rest of the burst access.
Byte write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BW[A:D]) inputs. A Global Write
Enable (GW) overrides all byte write inputs and writes data to all
four bytes. All writes are simplified with on-chip synchronous self
timed write circuitry.
Three synchronous Chip Selects (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tristate control. ADSP is ignored if CE1 is
HIGH.
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)
CE1, CE2, CE3 are all asserted active, and (3) the write signals
(GW, BWE) are all deasserted HIGH. ADSP is ignored if CE1 is
HIGH. The address presented to the address inputs (A[16:0]) is
stored into the address advancement logic and the Address
Register while being presented to the memory core. The
corresponding data is allowed to propagate to the input of the
Output Registers. At the rising edge of the next clock the data is
allowed to propagate through the Output Register and onto the
data bus within 2.6 ns (250 MHz device) if OE is active LOW. The
only exception occurs when the SRAM is emerging from a
deselected state to a selected state, its outputs are always
tristated during the first cycle of the access. After the first cycle
of the access, the outputs are controlled by the OE signal.
Consecutive single read cycles are supported. After the SRAM
is deselected at clock rise by the chip select and either ADSP or
ADSC signals, its output tristates immediately.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions are
satisfied at clock rise: (1) ADSP is asserted LOW, and (2) CE1,
CE2, CE3 are all asserted active. The address presented to
A[16:0] is loaded into the Address Register and the address
advancement logic while being delivered to the RAM core. The
write signals (GW, BWE, and BW[A:D]) and ADV inputs are
ignored during this first cycle.
Document Number: 38-05516 Rev. *S
ADSP-triggered write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQs and DQPs inputs is written into the
corresponding address location in the RAM core. If GW is HIGH,
then the write operation is controlled by BWE and BW[A:D]
signals. The CY7C1347G provides byte write capability that is
described in "Partial Truth Table for Read/Write" on page 10.
Asserting the Byte Write Enable input (BWE) with the selected
Byte Write (BW[A:D]) input selectively writes to only the desired
bytes.
Bytes not selected during a byte write operation remain
unaltered. A synchronous self timed write mechanism is
provided to simplify the write operations.
Because the CY7C1347G is a common I/O device, the Output
Enable (OE) must be deasserted HIGH before presenting data
to the DQs and DQPs inputs. Doing so tristates the output
drivers. As a safety precaution, DQs and DQPs are automatically
tristated whenever a write cycle is detected, regardless of the
state of OE.
Single Write Accesses Initiated by ADSC
ADSC write accesses are initiated when the following conditions
are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deasserted
HIGH, (3) CE1, CE2, CE3 are all asserted active, and (4) the
appropriate combination of the write inputs (GW, BWE, and
BW[A:D]) are asserted active to conduct a write to the desired
byte(s). ADSC-triggered write accesses require a single clock
cycle to complete. The address presented to A[16:0] is loaded into
the address register and the address advancement logic while
being delivered to the RAM core. The ADV input is ignored
during this cycle. If a global write is conducted, the data
presented to the DQs and DQPs is written into the corresponding
address location in the RAM core. If a byte write is conducted,
only the selected bytes are written. Bytes not selected during a
byte write operation remain unaltered. A synchronous self timed
write mechanism has been provided to simplify the write
operations.
Because the CY7C1347G is a common I/O device, the Output
Enable (OE) must be deasserted HIGH before presenting data
to the DQs and DQPs inputs. Doing so tristates the output
drivers. As a safety precaution, DQs and DQPs are automatically
tristated whenever a write cycle is detected, regardless of the
state of OE.
Burst Sequences
The CY7C1347G provides a two-bit wraparound counter, fed by
A[1:0], that implements either an interleaved or linear burst
sequence. The interleaved burst sequence is designed
specifically to support Intel Pentium applications. The linear
burst sequence is designed to support processors that follow a
linear burst sequence. The burst sequence is user-selectable
through the MODE input.
Asserting ADV LOW at clock rise automatically increments the
burst counter to the next address in the burst sequence. Both
read and write burst operations are supported.
Page 7 of 26
CY7C1347G
Sleep Mode
Interleaved Burst Sequence
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
While in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered valid
nor is the completion of the operation guaranteed. The device
must be deselected before entering the “sleep” mode. CE1, CE2,
CE3, ADSP, and ADSC must remain inactive for the duration of
tZZREC after the ZZ input returns LOW.
First
Address
A[1:0]
Second
Address
A[1:0]
Third
Address
A[1:0]
Fourth
Address
A[1:0]
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Fourth
Address
A[1:0]
Linear Burst Sequence
First
Address
A[1:0]
Second
Address
A[1:0]
Third
Address
A[1:0]
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
IDDZZ
Snooze mode standby current
ZZ > VDD 0.2 V
tZZS
Device operation to ZZ
ZZ > VDD 0.2 V
tZZREC
ZZ recovery time
ZZ < 0.2 V
tZZI
ZZ Active to snooze current
tRZZI
Min
Max
Unit
–
40
mA
–
2tCYC
ns
2tCYC
–
ns
This parameter is sampled
–
2tCYC
ns
ZZ Inactive to exit snooze current This parameter is sampled
0
–
ns
Document Number: 38-05516 Rev. *S
Page 8 of 26
CY7C1347G
Truth Table
The truth table for part number CY7C1347G follow.
Next Cycle [3, 4, 5, 6, 7]
Add. Used CE1 CE2 CE3
ZZ
ADSP ADSC ADV WRITE OE
CLK
DQ
Deselect cycle, power-down
None
H
X
X
L
X
L
X
X
X
L–H Tristate
Deselect cycle, power-down
None
L
L
X
L
L
X
X
X
X
L–H Tristate
Deselect cycle, power-down
None
L
X
H
L
L
X
X
X
X
L–H Tristate
Deselect cycle, power-down
None
L
L
X
L
H
L
X
X
X
L–H Tristate
Deselect cycle, power-down
None
L
X
H
L
H
L
X
X
X
L–H Tristate
Snooze mode, power-down
None
X
X
X
H
X
X
X
X
X
Read Cycle, Begin Burst
External
L
H
L
L
L
X
X
X
L
L–H Q
Read Cycle, Begin Burst
External
L
H
L
L
L
X
X
X
H
L–H Tristate
Write Cycle, Begin Burst
External
L
H
L
L
H
L
X
L
X
L–H D
Read Cycle, Begin Burst
External
L
H
L
L
H
L
X
H
L
L–H Q
Read Cycle, Begin Burst
External
L
H
L
L
H
L
X
H
H
L–H Tristate
Read Cycle, Continue Burst
Next
X
X
X
L
H
H
L
H
H
L–H Tristate
Read Cycle, Continue Burst
Next
X
X
X
L
H
H
L
H
L
L–H Q
Read Cycle, Continue Burst
Next
H
X
X
L
X
H
L
H
L
L–H Q
Read Cycle, Continue Burst
Next
H
X
X
L
X
H
L
H
H
L–H Tristate
Write cycle, continue burst
Next
X
X
X
L
H
H
L
L
X
L–H D
Write cycle, continue burst
Next
H
X
X
L
X
H
L
L
X
L–H D
Read cycle, suspend burst
Current
X
X
X
L
H
H
H
H
L
L–H Q
Read cycle, suspend burst
Current
X
X
X
L
H
H
H
H
H
L–H Tristate
Read cycle, suspend burst
Current
H
X
X
L
X
H
H
H
L
L–H Q
Read cycle, suspend burst
Current
H
X
X
L
X
H
H
H
H
L–H Tristate
Write cycle, suspend burst
Current
X
X
X
L
H
H
H
L
X
L–H D
Write cycle, suspend burst
Current
H
X
X
L
X
H
H
L
X
L–H D
X
Tristate
Notes
3. X = “Do not Care.” H = Logic HIGH, L = Logic LOW.
4. WRITE = L when any one or more Byte Write Enable signals (BWA, BWB, BWC, BWD) and BWE = L or GW = L. WRITE = H when all Byte Write Enable signals (BWA,
BWB, BWC, BWD), BWE, GW = H.
5. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW[A:D]. Writes may occur only on subsequent clocks after
the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH before the start of the write cycle to allow the outputs to tristate. OE is a do not care
for the remainder of the write cycle.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tristate when OE is inactive
or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document Number: 38-05516 Rev. *S
Page 9 of 26
CY7C1347G
Partial Truth Table for Read/Write
The partial truth table for read/write for part number CY7C1347G follow.
Function [8, 9]
GW
BWE
BWD
BWC
BWB
BWA
Read
H
H
X
X
X
X
Read
H
L
H
H
H
H
Write byte A – DQA
H
L
H
H
H
L
Write byte B – DQB
H
L
H
H
L
H
Write bytes B, A
H
L
H
H
L
L
Write byte C – DQC
H
L
H
L
H
H
Write bytes C, A
H
L
H
L
H
L
Write bytes C, B
H
L
H
L
L
H
Write bytes C, B, A
H
L
H
L
L
L
Write byte D – DQD
H
L
L
H
H
H
Write bytes D, A
H
L
L
H
H
L
Write bytes D, B
H
L
L
H
L
H
Write bytes D, B, A
H
L
L
H
L
L
Write bytes D, C
H
L
L
L
H
H
Write bytes D, C, A
H
L
L
L
H
L
Write bytes D, C, B
H
L
L
L
L
H
Write all bytes
H
L
L
L
L
L
Write all bytes
L
X
X
X
X
X
Notes
8. X = “Do not Care.” H = Logic HIGH, L = Logic LOW.
9. This table is only a partial listing of the byte write combinations. Any combination of BWx is valid. Appropriate write is based on which byte write is active.
Document Number: 38-05516 Rev. *S
Page 10 of 26
CY7C1347G
Maximum Ratings
Operating Range
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage temperature 65 C to +150 C
Commercial
Ambient temperature
with power applied 55 C to +125 C
Industrial
Supply voltage on VDD relative to GND 0.5 V to +4.6 V
Supply voltage on VDDQ relative to GND 0.5 V to +VDD
DC voltage applied to outputs
in high Z State 0.5 V to VDD + 0.5 V
DC input voltage 0.5 V to VDD + 0.5 V
Latch-up Current .................................................... > 200 mA
VDD
VDDQ
0 °C to +70 °C 3.3 V5% / + 2.5 V 5% to
10%
VDD
-40 °C to +85 °C
Neutron Soft Error Immunity
Test
Parameter Description Conditions
Typ
Max*
Unit
LSBU
Logical
single-bit
upsets
25 °C
361
394
FIT/
Mb
LMBU
Logical
multi-bit
upsets
25 °C
0
0.01
FIT/
Mb
SEL
Single event
latch-up
85 °C
0
0.1
FIT/
Dev
Current into outputs (LOW) ........................................ 20 mA
Static discharge voltage
(MIL-STD-883, Method 3015) ................................. > 2001 V
Ambient
Temperature
Range
* No LMBU or SEL events occurred during testing; this column represents a
statistical 2, 95% confidence limit calculation. For more details refer to Application
Note, Accelerated Neutron SER Testing and Calculation of Terrestrial Failure
Rates – AN54908.
Electrical Characteristics
Over the Operating Range
Parameter [10, 11]
Description
Test Conditions
Min
Max
Unit
VDD
Power supply voltage
3.135
3.6
V
VDDQ
I/O supply voltage
2.375
VDD
V
VOH
Output HIGH voltage
For 3.3 V I/O, IOH = –4.0 mA
2.4
–
V
For 2.5 V I/O, IOH = –1.0 mA
2.0
–
V
For 3.3 V I/O, IOL = 8.0 mA
–
0.4
V
For 2.5 V I/O, IOL = 1.0 mA
–
0.4
V
For 3.3 V I/O
2.0
VDD + 0.3
V
For 2.5 V I/O
1.7
VDD + 0.3
V
For 3.3 V I/O
–0.3
0.8
V
For 2.5 V I/O
–0.3
0.7
V
Input leakage current except ZZ GND < VI < VDDQ
and MODE
5
5
A
Input current of MODE
Input = VSS
30
–
A
Input = VDD
–
5
A
Input = VSS
5
–
A
Input = VDD
–
30
A
GND VI VDDQ, output disabled
5
5
A
VOL
VIH
VIL
IX
Output LOW voltage
Input HIGH
voltage[10]
[10]
Input LOW voltage
Input current of ZZ
IOZ
Output leakage current
Notes
10. Overshoot: VIH(AC) < VDD + 1.5 V (pulse width less than tCYC/2). Undershoot: VIL(AC) > –2 V (pulse width less than tCYC/2).
11. tpower-up: assumes a linear ramp from 0 V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
Document Number: 38-05516 Rev. *S
Page 11 of 26
CY7C1347G
Electrical Characteristics (continued)
Over the Operating Range
Parameter [10, 11]
IDD
ISB1
Description
VDD operating supply current
Automatic CE power-down
current – TTL inputs
Test Conditions
VDD = Max., IOUT = 0 mA,
f = fMAX = 1/tCYC
Max. VDD, device deselected,
VIN > VIH or VIN < VIL,
f = fMAX = 1/tCYC
Min
Max
Unit
4 ns cycle,
250 MHz
–
325
mA
5 ns cycle,
200 MHz
–
265
mA
6 ns cycle,
166 MHz
–
240
mA
7.5 ns cycle,
133 MHz
–
225
mA
4 ns cycle,
250 MHz
–
120
mA
5 ns cycle,
200 MHz
–
110
mA
6 ns cycle,
166 MHz
–
100
mA
7.5 ns cycle,
133 MHz
–
90
mA
ISB2
Automatic CE power-down
current – CMOS inputs
Max. VDD, device deselected,
VIN < 0.3 V or
VIN > VDDQ – 0.3 V,
f=0
All speeds
–
40
mA
ISB3
Automatic CE power-down
current – CMOS inputs
Max. VDD, device deselected,
VIN < 0.3 V or
VIN > VDDQ – 0.3 V,
f = fMAX = 1/tCYC
4 ns cycle,
250 MHz
–
105
mA
5 ns cycle,
200 MHz
–
95
mA
6 ns cycle,
166 MHz
–
85
mA
7.5 ns cycle,
133 MHz
–
75
mA
–
45
mA
ISB4
Automatic CE power-down
current – TTL inputs
Document Number: 38-05516 Rev. *S
Max. VDD, device deselected,
VIN VIH or VIN VIL,
f=0
Page 12 of 26
CY7C1347G
Capacitance
Parameter [12]
Description
CIN
Input capacitance
CCLK
Clock input capacitance
CIO
I/O capacitance
100-pin TQFP Unit
Max
Test Conditions
TA = 25 C, f = 1 MHz,
VDD = 3.3 V, VDDQ = 3.3 V
5
pF
5
pF
5
pF
Test Conditions
100-pin TQFP
Package
Unit
Test conditions follow standard test methods and
procedures for measuring thermal impedance, per
EIA/JESD51.
30.32
C/W
6.85
C/W
Thermal Resistance
Parameter [12]
Description
JA
Thermal resistance
(junction to ambient)
JC
Thermal resistance
(junction to case)
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms
3.3 V I/O Test Load
R = 317
3.3 V
OUTPUT
OUTPUT
RL = 50
Z0 = 50
All input pulses
VDDQ
GND
5 pF
R = 351
10%
90%
10%
90%
1 ns
1 ns
VT = 1.5 V
Including
JIG and
scope
(a)
(c)
(b)
2.5 V I/O Test Load
R = 1667
2.5 V
OUTPUT
OUTPUT
RL = 50
Z0 = 50
VT = 1.25 V
(a)
All input pulses
VDDQ
GND
5 pF
Including
JIG and
scope
R = 1538
(b)
10%
90%
10%
90%
1 ns
1 ns
(c)
Note
12. Tested initially and after any design or process changes that may affect these parameters.
Document Number: 38-05516 Rev. *S
Page 13 of 26
CY7C1347G
Switching Characteristics
Over the Operating Range
Parameter [13, 14]
tPOWER
Description
VDD(typical) to the first access [15]
-250
-200
-166
-133
Unit
Min
Max
Min
Max
Min
Max
Min
Max
1
–
1
–
1
–
1
–
ms
Clock
tCYC
Clock cycle time
4.0
–
5.0
–
6.0
–
7.5
–
ns
tCH
Clock HIGH
1.7
–
2.0
–
2.5
–
3.0
–
ns
tCL
Clock LOW
1.7
–
2.0
–
2.5
–
3.0
–
ns
Output Times
tCO
Data output valid after CLK rise
–
2.6
–
2.8
–
3.5
–
4.0
ns
tDOH
Data output hold after CLK rise
1.0
–
1.0
–
1.5
–
1.5
–
ns
tCLZ
Clock to low Z [16, 17, 18]
0
–
0
–
0
–
0
–
ns
tCHZ
Clock to high Z [16, 17, 18]
–
2.6
–
2.8
–
3.5
–
4.0
ns
tOEV
OE LOW to output valid
–
2.6
–
2.8
–
3.5
–
4.5
ns
0
–
0
–
0
–
0
–
ns
–
2.6
–
2.8
–
3.5
–
4.0
ns
tOELZ
OE LOW to output low Z
tOEHZ
OE HIGH to output high Z [16, 17, 18]
[16, 17, 18]
Setup Times
tAS
Address setup before CLK rise
1.2
–
1.2
–
1.5
–
1.5
–
ns
tADS
ADSC, ADSP setup before CLK rise
1.2
–
1.2
–
1.5
–
1.5
–
ns
tADVS
ADV setup before CLK rise
1.2
–
1.2
–
1.5
–
1.5
–
ns
tWES
GW, BWE, BWX setup before CLK rise
1.2
–
1.2
–
1.5
–
1.5
–
ns
tDS
Data input setup before CLK rise
1.2
–
1.2
–
1.5
–
1.5
–
ns
tCES
Chip enable setup before CLK rise
1.2
–
1.2
–
1.5
–
1.5
–
ns
tAH
Address hold after CLK rise
0.3
–
0.5
–
0.5
–
0.5
–
ns
tADH
ADSP, ADSC hold after CLK rise
0.3
–
0.5
–
0.5
–
0.5
–
ns
tADVH
ADV hold after CLK Rise
0.3
–
0.5
–
0.5
–
0.5
–
ns
tWEH
GW, BWE, BWX hold after CLK rise
0.3
–
0.5
–
0.5
–
0.5
–
ns
tDH
Data input hold after CLK rise
0.3
–
0.5
–
0.5
–
0.5
–
ns
tCEH
Chip enable hold after CLK rise
0.3
–
0.5
–
0.5
–
0.5
–
ns
Hold Times
Notes
13. Timing references level is 1.5 V when VDDQ = 3.3 V and is 1.25 V when VDDQ = 2.5 V on all datasheets.
14. Test conditions shown in (a) of Figure 2 on page 13 unless otherwise noted.
15. This part has an internal voltage regulator; tPOWER is the time that the power must be supplied above VDD(min) initially before a read or write operation can be initiated.
16. tCHZ, tCLZ, tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of Figure 2 on page 13. Transition is measured ±200 mV from steady-state voltage.
17. At any voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus.
These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve
High Z before Low Z under the same system conditions.
18. This parameter is sampled and not 100% tested.
Document Number: 38-05516 Rev. *S
Page 14 of 26
CY7C1347G
Switching Waveforms
Figure 3. Read Cycle Timing [19]
t CYC
CLK
t
t
CH
t
CL
t
ADH
ADS
ADSP
t ADS
tADH
ADSC
t AS
ADDRESS
tAH
A1
A2
t WES
A3
Burst continued with
new base address
tWEH
GW, BWE,
BW [A:D]
t CES
Deselect
cycle
tCEH
CE
t ADVS
tADVH
ADV
ADV
suspends
burst.
OE
t OEHZ
t CLZ
Data Out (Q)
High-Z
Q(A1)
t OEV
t CO
t OELZ
t DOH
Q(A2)
t CHZ
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
t CO
Single READ
BURST READ
DON’T CARE
Burst wraps around
to its initial state
UNDEFINED
Note
19. In this diagram, when CE is LOW, CE1 is LOW, CE2 is HIGH, and CE3 is LOW. When CE is HIGH, CE1 is HIGH, CE2 is LOW, or CE3 is HIGH.
Document Number: 38-05516 Rev. *S
Page 15 of 26
CY7C1347G
Switching Waveforms (continued)
Figure 4. Write Cycle Timing [20, 21]
t CYC
CLK
tCH
t ADS
tCL
tADH
ADSP
t ADS
ADSC extends burst
tADH
t ADS
tADH
ADSC
t AS
tAH
A1
ADDRESS
A2
A3
Byte write signals are
ignored for first cycle when
ADSP initiates burst
t WES tWEH
BWE,
BW[A :B]
t WES tWEH
GW
t CES
tCEH
CE
t
t
ADVS ADVH
ADV
ADV suspends burst
OE
t DS
Data In (D)
High-Z
t
OEHZ
tDH
D(A1)
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
Data Out (Q)
BURST READ
Single WRITE
BURST WRITE
DON’T CARE
Extended BURST WRITE
UNDEFINED
Notes
20. In this diagram, when CE is LOW, CE1 is LOW, CE2 is HIGH, and CE3 is LOW. When CE is HIGH, CE1 is HIGH, CE2 is LOW, or CE3 is HIGH.
21. Full width write can be initiated by either GW LOW, or by GW HIGH, BWE LOW, and BWx LOW.
Document Number: 38-05516 Rev. *S
Page 16 of 26
CY7C1347G
Switching Waveforms (continued)
Figure 5. Read/Write Cycle Timing [22, 23, 24]
tCYC
CLK
tCL
tCH
t ADS
tADH
ADSP
ADSC
t AS
ADDRESS
A1
tAH
A2
A3
A4
t WES
tWEH
t DS
tDH
A5
A6
BWE,
BW[A:D]
t CES
tCEH
CE
ADV
OE
tCO
t OELZ
Data In (D)
High-Z
tCLZ
Data Out (Q)
High-Z
Q(A1)
Back-to-Back READs
tOEHZ
D(A5)
D(A3)
Q(A2)
Q(A4)
Single WRITE
Q(A4+1)
Q(A4+2)
Q(A4+3)
BURST READ
DON’T CARE
D(A6)
Back-to-Back
WRITEs
UNDEFINED
Notes
22. In this diagram, when CE is LOW, CE1 is LOW, CE2 is HIGH, and CE3 is LOW. When CE is HIGH, CE1 is HIGH, CE2 is LOW, or CE3 is HIGH.
23. The data bus (Q) remains in High Z following a write cycle, unless a new read access is initiated by ADSP or ADSC.
24. GW is HIGH.
Document Number: 38-05516 Rev. *S
Page 17 of 26
CY7C1347G
Switching Waveforms (continued)
Figure 6. ZZ Mode Timing [25, 26]
CLK
t
ZZ
I
t
t
ZZ
ZZREC
ZZI
SUPPLY
I
DDZZ
t RZZI
A LL INPUTS
DESELECT or READ Only
(except ZZ)
Outputs (Q)
High-Z
DON’T CARE
Notes
25. Device must be deselected when entering ZZ mode. See "Truth Table" on page 9 for all possible signal conditions to deselect the device.
26. DQs are in High Z when exiting ZZ sleep mode.
Document Number: 38-05516 Rev. *S
Page 18 of 26
CY7C1347G
Ordering Information
The table below contains only the parts that are currently available. If you don’t see what you are looking for, please contact your local
sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary page at
http://www.cypress.com/products
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors. To find the office
closest to you, visit us at http://www.cypress.com/go/datasheet/offices
Speed
(MHz)
133
Package
Diagram
Ordering Code
Package Type
Operating
Range
CY7C1347G-133AXC
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
Commercial
CY7C1347G-133AXI
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
Industrial
166
CY7C1347G-166AXC
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
Commercial
200
CY7C1347G-200AXC
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
Commercial
250
CY7C1347G-250AXC
51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
Commercial
Ordering Code Definitions
CY
7
C 1347
G - XXX XX
X
X
Temperature range: X = C or I
C = Commercial; I = Industrial
X = Pb-free; X Absent = Leaded
Package Type: XX = A
A = 100-pin TQFP
Speed Grade: XXX = 133 MHz or 166 MHz or 200 MHz or 250 MHz
Process Technology: G 90 nm
Part Identifier: 1347 = SCD, 128K × 36 (4Mb)
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
Document Number: 38-05516 Rev. *S
Page 19 of 26
CY7C1347G
Package Diagrams
Figure 7. 100-pin TQFP (14 × 20 × 1.4 mm) A100RA Package Outline, 51-85050
ș2
ș1
ș
SYMBOL
DIMENSIONS
MIN. NOM. MAX.
A
1.60
A1
0.05
A2
1.35 1.40 1.45
0.15
NOTE:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. BODY LENGTH DIMENSION DOES NOT
INCLUDE MOLD PROTRUSION/END FLASH.
D
15.80 16.00 16.20
MOLD PROTRUSION/END FLASH SHALL
D1
13.90 14.00 14.10
E
21.80 22.00 22.20
NOT EXCEED 0.0098 in (0.25 mm) PER SIDE.
BODY LENGTH DIMENSIONS ARE MAX PLASTIC
E1
19.90 20.00 20.10
R1
0.08
0.20
R2
0.08
0.20
ș
0°
7°
ș1
0°
ș2
11°
13°
12°
0.20
c
b
0.22 0.30 0.38
L
0.45 0.60 0.75
L1
L2
L3
e
BODY SIZE INCLUDING MOLD MISMATCH.
3. JEDEC SPECIFICATION NO. REF: MS-026.
1.00 REF
0.25 BSC
0.20
0.65 TYP
51-85050 *G
Document Number: 38-05516 Rev. *S
Page 20 of 26
CY7C1347G
Acronyms
Acronym
Document Conventions
Description
Units of Measure
CE
Chip Enable
CMOS
Complementary Metal Oxide Semiconductor
°C
degree Celsius
I/O
Input/Output
k
kilohm
JEDEC
Joint Electron Device Engineering Council
MHz
megahertz
LMBU
Logical Multi-Bit Upsets
µA
microampere
LSBU
Logical Single-Bit Upsets
µs
microsecond
OE
Output Enable
mA
milliampere
SEL
Single Event Latch-up
SRAM
Static Random Access Memory
TQFP
Thin Quad Flat Pack
TTL
Transistor-Transistor Logic
WE
Write Enable
Document Number: 38-05516 Rev. *S
Symbol
Unit of Measure
mV
millivolt
mm
millimeter
ms
millisecond
ns
nanosecond
ohm
%
percent
pF
picofarad
ps
picosecond
V
volt
W
watt
Page 21 of 26
CY7C1347G
Errata
This section describes the Ram9 Sync ZZ pin issue. Details include trigger conditions, the devices affected, proposed workaround
and silicon revision applicability. Please contact your local Cypress sales representative if you have further questions.
Part Numbers Affected
Density & Revision
Package Type
Operating Range
4Mb-Ram9 Synchronous SRAMs: CY7C134*G
100-pin TQFP
Commercial and
Industrial
Product Status
All of the devices in the Ram9 4Mb Sync family are qualified and available in production quantities.
Ram9 Sync ZZ Pin Issues Errata Summary
The following table defines the errata applicable to available Ram9 4Mb Sync family devices.
Item
1.
Issues
ZZ Pin
Description
Device
When asserted HIGH, the ZZ pin places
device in a “sleep” condition with data integrity
preserved.The ZZ pin currently does not have
an internal pull-down resistor and hence
cannot be left floating externally by the user
during normal mode of operation.
4M-Ram9 (90 nm)
Fix Status
For the 4M Ram9 (90 nm)
devices, there is no plan to fix
this issue.
1. ZZ Pin Issue
■
Problem Definition
The problem occurs only when the device is operated in the normal mode with ZZ pin left floating. The ZZ pin on the SRAM device
does not have an internal pull-down resistor. Switching noise in the system may cause the SRAM to recognize a HIGH on the ZZ
input, which may cause the SRAM to enter sleep mode. This could result in incorrect or undesirable operation of the SRAM.
■
Trigger Conditions
Device operated with ZZ pin left floating.
■
Scope of Impact
When the ZZ pin is left floating, the device delivers incorrect data.
■
Workaround
Tie the ZZ pin externally to ground.
■
Fix Status
For the 4M Ram9 (90 nm) devices, there is no plan to fix this issue.
Document Number: 38-05516 Rev. *S
Page 22 of 26
CY7C1347G
Document History Page
Document Title: CY7C1347G, 4-Mbit (128K × 36) Pipelined Sync SRAM
Document Number: 38-05516
Revision
ECN
Orig. of
Change
Submission
Date
**
224364
RKF
05/17/2004
New data sheet.
*A
276690
VBL
10/14/2004
Updated Ordering Information (Updated part numbers (Changed TQFP
package to Pb-free TQFP package); added comment on the BG and BZ
Pb-free package availability below the table).
*B
333625
SYT
03/16/2005
Updated Features (Removed 225 MHz and 100 MHz frequencies related
information).
Updated Selection Guide (Removed 225 MHz and 100 MHz frequencies
related information).
Updated Pin Configurations (Updated Address Expansion balls in the pinouts
for 100-pin TQFP Package as per JEDEC standards).
Updated Pin Definitions:
Removed “NC” and its details.
Added “NC, NC/9M, NC/18M, NC/36M, NC/72M, NC/144M, NC/288M,
NC/576M, NC/1G” and their details.
Updated Electrical Characteristics (Updated test conditions for VOL and VOH
parameters; removed 225 MHz and 100 MHz frequencies related information).
Updated Switching Characteristics (Removed 225 MHz and 100 MHz
frequencies related information).
Updated Thermal Resistance (Replaced TBDs for JA and JC to their
respective values).
Updated Ordering Information (Updated part numbers (By shading and
unshading MPNs as per availability); changed the package name for 100-pin
TQFP from A100RA to A101 in Package Name column; removed comment on
the availability of BG Pb-free package).
*C
419256
RXU
01/10/2006
Changed status from Preliminary to Final.
Changed address of Cypress Semiconductor Corporation from “3901 North
First Street” to “198 Champion Court”.
Updated Truth Table (Swapped typo CE2 and CE3 in the column heading).
Updated Electrical Characteristics (Changed “Input Load Current except ZZ
and MODE” to “Input Leakage Current except ZZ and MODE”; updated Note 11
(Changed test condition from VIH < VDD to VIH VDD)).
Updated Ordering Information (Updated part numbers; removed Package
Name column; added Package Diagram column in the table).
Updated Package Diagrams:
spec 51-85050 – Changed revision from *A to *B.
Updated to new template.
*D
480124
VKN
07/14/2006
Updated Maximum Ratings (Added “Supply Voltage on VDDQ Relative to GND”
and its corresponding details).
Updated Ordering Information (Updated part numbers).
*E
1078184
VKN
05/23/2007
Updated Switching Waveforms (Updated Figure 4).
*F
2633279
NXR /
AESA
01/15/2009
Updated Ordering Information (Updated part numbers).
Updated to new template.
*G
2756998
VKN
08/28/2009
Added Neutron Soft Error Immunity.
Updated Ordering Information (Updated part numbers (By including parts that
are available); and modified the disclaimer for the Ordering information).
Updated Package Diagrams:
spec 51-85180 – Changed revision from *A to *B.
Document Number: 38-05516 Rev. *S
Description of Change
Page 23 of 26
CY7C1347G
Document History Page (continued)
Document Title: CY7C1347G, 4-Mbit (128K × 36) Pipelined Sync SRAM
Document Number: 38-05516
Revision
ECN
Orig. of
Change
Submission
Date
*H
2998771
NJY
08/02/2010
Updated Package Diagrams:
spec 51-85050 – Changed revision from *B to *C.
spec 51-85115 – Changed revision from *B to *C.
spec 51-85180 – Changed revision from *B to *C.
Added Acronyms.
Updated to new template.
Completing Sunset Review.
*I
3208774
NJY
03/29/2011
Updated Ordering Information:
Updated part numbers.
Added Ordering Code Definitions.
Updated Package Diagrams:
spec 51-85050 – Changed revision from *C to *D.
*J
3310077
OSN
07/12/2011
Added Units of Measure.
Updated to new template.
Completing Sunset Review.
*K
3587066
NJY / PRIT
05/10/2012
Updated Features (Removed non Pb-free 119-ball BGA package and 165-ball
FBGA package related information; removed Industrial Temperature related
information).
Updated Functional Description (Removed the Note “For best practice
recommendations, refer to the Cypress application note, SRAM System
Guidelines – AN1064.” and its reference).
Updated Pin Configurations (Removed 165-ball FBGA package related
information).
Updated Operating Range (Removed Industrial Temperature Range).
Updated Capacitance (Removed 165-ball FBGA package related information).
Updated Thermal Resistance (Removed 165-ball FBGA package related
information).
Updated Package Diagrams (Removed spec 51-85180 *C).
*L
3690005
PRIT
07/24/2012
No technical updates.
Completing Sunset Review.
*M
3980577
PRIT
05/02/2013
Updated Package Diagrams:
spec 51-85115 – Changed revision from *C to *D.
Added Errata.
*N
4039646
PRIT
06/25/2013
Added Errata Footnotes.
Updated to new template.
Completing Sunset Review.
*O
4149033
PRIT
10/07/2013
Updated Errata.
*P
4419265
PRIT
06/25/2014
Included Industrial Temperature Range related information in all instances
across the document.
Updated Ordering Information (Updated part numbers).
Updated Package Diagrams:
spec 51-85050 – Changed revision from *D to *E.
Completing Sunset Review.
*Q
4569232
PRIT
11/14/2014
Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
Document Number: 38-05516 Rev. *S
Description of Change
Page 24 of 26
CY7C1347G
Document History Page (continued)
Document Title: CY7C1347G, 4-Mbit (128K × 36) Pipelined Sync SRAM
Document Number: 38-05516
Revision
ECN
Orig. of
Change
Submission
Date
Description of Change
*R
5376171
PRIT
07/27/2016
Removed 119-ball BGA package related information in all instances across the
document.
Updated Ordering Information:
Updated part numbers.
Updated Package Diagrams:
Removed spec 51-85115 *D.
Updated to new template.
Completing Sunset Review.
*S
6042415
RMES
01/23/2018
Updated Package Diagrams:
spec 51-85050 – Changed revision from *E to *G.
Updated to new template.
Completing Sunset Review.
Document Number: 38-05516 Rev. *S
Page 25 of 26
CY7C1347G
Sales, Solutions, and Legal Information
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Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
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Community | Projects | Video | Blogs | Training | Components
Technical Support
cypress.com/support
cypress.com/pmic
cypress.com/touch
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2004-2018. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
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are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
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Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
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Document Number: 38-05516 Rev. *S
Revised January 23, 2018
Page 26 of 26
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