CY7C1350B-100AI

350B PRELIMINARY CY7C1350B 128Kx36 Pipelined SRAM with NoBL™ Architecture Features • Pin compatible and functionally equivalent to ZBT™ devices IDT71V546, MT55L128L36P, and MCM63Z736 • Supports 166-MHz bus operations with zero wait states — Data is transferred on every clock • Internally self-timed output buffer control to eliminate the need to use OE • Fully registered (inputs and outputs) for pipelined operation • Byte Write capability • 128K x 36 common I/O architecture • Single 3.3V power supply • Fast clock-to-output times — 3.5 ns (for 166-MHz device) — 3.8 ns (for 150-MHz device) — 4.0 ns (for 143-MHz device) — 4.2 ns (for 133-MHz device) — 5.0 ns (for 100-MHz device) • • • • • • — 7.0 ns (for 80-MHz device) Clock Enable (CEN) pin to suspend operation Synchronous self-timed writes Asynchronous output enable JEDEC-standard 100 TQFP package Burst Capability—linear or interleaved burst order Low standby power (17.325 mW max.) Functional Description The CY7C1350B is a 3.3V, 128K by 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350B is equipped with the advanced No Bus Latency™ (NoBL™) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of the SRAM, especially in systems that require frequent Write/Read transitions. The CY7C1350B is pin/functionally compatible to ZBT SRAMs IDT71V546, MT55L128L36P, and MCM63Z736. All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable (CEN) signal, which when deasserted suspends operation and extends the previous clock cycle. Maximum access delay from the clock rise is 3.5 ns (166-MHz device). Write operations are controlled by the four Byte Write Select (BWS[3:0]) and a Write Enable (WE) input. All writes are conducted with on-chip synchronous self-timed write circuitry. Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output three-state control. In order to avoid bus contention, the output drivers are synchronously three-stated during the data portion of a write sequence. Logic Block Diagram CLK CE ADV/LD A[16:0] CEN CE 1 CE2 CE3 WE BWS[3:0] MODE 17 CONTROL and WRITE LOGIC 17 128Kx36 MEMORY ARRAY 36 D Data-In REG. Q 36 36 CLK OOUTPUT REGISTERS and LOGIC 36 DQ[31:0] DP[3:0] OE . Selection Guide -166 Maximum Access Time (ns) Maximum Operating Current (mA) Maximum CMOS Standby Current (mA) Shaded areas contain advance information. NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device Technology. -150 3.8 375 5 -143 4.0 350 5 -133 4.2 300 5 -100 5.0 250 5 -80 7.0 200 5 3.5 Commercial Commercial 400 5 Cypress Semiconductor Corporation Document #: 38-05045 Rev. ** • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised September 7, 2001 PRELIMINARY CY7C1350B Pin Configuration 100-Pin TQFP ADV/LD BWS3 BWS2 BWS1 BWS0 CE1 CE2 CE3 VDD CEN CLK VSS NC WE OE A6 A7 NC A8 82 A9 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 DP 2 DQ16 DQ17 VDDQ VSS DQ18 DQ19 DQ20 DQ21 VSS VDDQ DQ22 DQ23 VDDQ VDD VDD VSS DQ24 DQ25 VDDQ VSS DQ26 DQ27 DQ28 DQ29 VSS VDDQ DQ30 DQ31 DP3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 100 83 DP1 DQ15 DQ14 VDDQ VSS DQ13 DQ12 DQ11 DQ10 VSS VDDQ DQ9 DQ8 VSS VDD VDD VSS DQ7 DQ6 VDDQ VSS DQ5 DQ4 DQ3 DQ2 VSS VDDQ DQ1 DQ0 DP0 CY7C1350B A11 A12 A13 VSS DNU VDD DNU Document #: 38-05045 Rev. ** MODE DNU DNU A10 A14 A15 A16 A5 A4 A3 A2 A1 A0 Page 2 of 14 PRELIMINARY Pin Definitions Pin Number 50–44, 81–82, 99, 100, 32–37 96–93 Name A[16:0] I/O InputSynchronous InputSynchronous Description CY7C1350B Address Inputs used to select one of the 131,072 address locations. Sampled at the rising edge of the CLK. Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on the rising edge of CLK. BWS0 controls DQ[7:0] and DP0, BWS1 controls DQ[15:8] and DP1, BWS2 controls DQ[23:16] and DP2, BWS3 controls DQ[31:24] and DP3. See Write Cycle Description table for details. Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal must be asserted LOW to initiate a write sequence. Advance/Load Input used to advance the on-chip address counter or load a new address. When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address can be loaded into the device for an access. After being deselected, ADV/LD should be driven LOW in order to load a new address. Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is only recognized if CEN is active LOW. Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2, and CE3 to select/deselect the device. Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3 to select/deselect the device. Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select/deselect the device. Output Enable, active LOW. Combined with the synchronous logic block inside the device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE is masked during the data portion of a write sequence, during the first clock when emerging from a deselected state, when the device has been deselected. Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized by the SRAM. When deasserted HIGH the Clock signal is masked. Since deasserting CEN does not deselect the device, CEN can be used to extend the previous cycle when required. Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by A[16:0] during the previous clock rise of the read cycle. The direction of the pins is controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH, DQ[31:0] are placed in a three-state condition. The outputs are automatically three-stated during the data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of OE. Bidirectional Data Parity I/O lines. Functionally, these signals are identical to DQ[31:0]. During write sequences, DP0 is controlled by BWS0, DP1 is controlled by BWS1, DP2 is controlled by BWS2, and DP3 is controlled by BWS3. Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order. Pulled LOW selects the linear burst order. MODE should not change states during operation. When left floating MODE will default HIGH, to an interleaved burst order. Power supply inputs to the core of the device. Should be connected to 3.3V power supply. Power supply for the I/O circuitry. Should be connected to a 3.3V power supply. BWS[3:0] 88 85 WE ADV/LD InputSynchronous InputSynchronous 89 98 97 92 86 CLK CE1 CE2 CE3 OE Input-Clock InputSynchronous InputSynchronous InputSynchronous InputAsynchronous 87 CEN InputSynchronous 29–28, DQ[31:0] 25–22, 19–18, 13–12, 9–6, 3–2, 79–78, 75–72, 69–68, 63–62 59–56, 53–52 30, 1, 80 51 DP[3:0] I/OSynchronous I/OSynchronous Input Strap pin 31 MODE 15, 16, 41, 65, 66, 91 4, 11, 14, 20, 27, 54, 61, 70, 77 VDD VDDQ Power Supply I/O Power Supply Document #: 38-05045 Rev. ** Page 3 of 14 PRELIMINARY Pin Definitions (continued) Pin Number 5, 10, 17, 21, 26, 40, 55, 60, 64, 67, 71, 76, 90 83, 84 Name VSS I/O Ground Description CY7C1350B Ground for the device. Should be connected to ground of the system. NC - No connects. Reserved for address inputs for depth expansion. Pin 83 and 84 will be used for 256K and 512K depths respectively. Do Not Use pins. These pins should be left floating or tied to VSS. Burst Read Accesses The CY7C1350B has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four Reads without reasserting the address inputs. ADV/LD must be driven LOW in order to load a new address into the SRAM, as described in the Single Read Access section above. The sequence of the burst counter is determined by the MODE input signal. A LOW input on MODE selects a linear burst mode, a HIGH selects an interleaved burst sequence. Both burst counters use A0 and A1 in the burst sequence, and will wrap-around when incremented sufficiently. A HIGH input on ADV/LD will increment the internal burst counter regardless of the state of chip enables inputs or WE. WE is latched at the beginning of a burst cycle. Therefore, the type of access (Read or Write) is maintained throughout the burst sequence. Single Write Accesses Write access are initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2, and CE3 are ALL asserted active, and (3) the write signal WE is asserted LOW. The address presented to A0−A16 is loaded into the Address Register. The write signals are latched into the Control Logic block. On the subsequent clock rise the data lines are automatically three-stated regardless of the state of the OE input signal. This allows the external logic to present the data on DQ[31:0] and DP[3:0]. In addition, the address for the subsequent access (Read/Write/Deselect) is latched into the Address Register (provided the appropriate control signals are asserted). On the next clock rise the data presented to DQ[31:0] and DP[3:0] (or a subset for byte write operations, see Write Cycle Description table for details) inputs is latched into the device and the write is complete. The data written during the Write operation is controlled by BWS[3:0] signals. The CY7C1350B provides byte write capability that is described in the Write Cycle Description table. Asserting the Write Enable input (WE) with the selected Byte Write Select (BWS[3:0]) input will selectively write to only the desired bytes. Bytes not selected during a byte write operation will remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. Byte write capability has been included in order to greatly simplify Read/Modify/Write sequences, which can be reduced to simple byte write operations. Because the CY7C1350B is a common I/O device, data should not be driven into the device while the outputs are active. The Output Enable (OE) can be deasserted HIGH before presenting data to the DQ[31:0] and DP[3:0] inputs. Doing so will three-state the output drivers. As a safety precaution, DQ[31:0] 38, 39, 42, 43 DNU Introduction Functional Overview The CY7C1350B is a synchronous-pipelined Burst SRAM designed specifically to eliminate wait states during Write/Read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock signal is qualified with the Clock Enable input signal (CEN). If CEN is HIGH, the clock signal is not recognized and all internal states are maintained. All synchronous operations are qualified with CEN. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (tCO) is 3.5 ns (166-MHz device). Accesses can be initiated by asserting all three Chip Enables (CE1, CE2, CE3) active at the rising edge of the clock. If Clock Enable (CEN) is active LOW and ADV/LD is asserted LOW, the address presented to the device will be latched. The access can either be a read or write operation, depending on the status of the Write Enable (WE). BWS[3:0] can be used to conduct byte write operations. Write operations are qualified by the Write Enable (WE). All writes are simplified with on-chip synchronous self-timed write circuitry. Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) simplify depth expansion. All operations (Reads, Writes, and Deselects) are pipelined. ADV/LD should be driven LOW once the device has been deselected in order to load a new address for the next operation. Single Read Accesses A read access is initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2, and CE3 are ALL asserted active, (3) the Write Enable input signal WE is deasserted HIGH, and (4) ADV/LD is asserted LOW. The address presented to the address inputs (A0−A16) is latched into the Address Register and presented to the memory core and control logic. The control logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At the rising edge of the next clock the requested data is allowed to propagate through the output register and onto the data bus within 3.5 ns (166-MHz device) provided OE is active LOW. After the first clock of the read access the output buffers are controlled by OE and the internal control logic. OE must be driven LOW in order for the device to drive out the requested data. During the second clock, a subsequent operation (Read/Write/Deselect) can be initiated. Deselecting the device is also pipelined. Therefore, when the SRAM is deselected at clock rise by one of the chip enable signals, its output will three-state following the next clock rise. Document #: 38-05045 Rev. ** Page 4 of 14 PRELIMINARY and DP[3:0] are automatically three-stated during the data portion of a write cycle, regardless of the state of OE. Burst Write Accesses The CY7C1350B has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four WRITE operations without reasserting the address inputs. ADV/LD must be driven LOW in order to load the initial address, as described in the Single Write Access section above. When ADV/LD is driven HIGH on the subsequent clock rise, the chip enables (CE1, CE2, and CE3) and WE inputs are ignored and the burst counter is incremented. The correct BWS[3:0] inputs must be driven in each cycle of the burst write in order to write the correct bytes of data. CY7C1350B Linear Burst Sequence First Address Ax+1, Ax 00 01 10 11 Second Address Ax+1, Ax 01 10 11 00 Third Address Ax+1, Ax 10 11 00 01 Fourth Address Ax+1, Ax 11 00 01 10 Interleaved Burst Sequence First Address Ax+1, Ax 00 01 10 11 Second Address Ax+1, Ax 01 00 11 10 Third Address Ax+1, Ax 10 11 00 01 Fourth Address Ax+1, Ax 11 10 01 00 Cycle Description Truth Table[1, 2, 3, 4, 5, 6] Operation Deselected Suspend Begin Read Begin Write Burst Read Operation Address Used External External External Internal CE 1 X 0 0 X CEN 0 1 0 0 0 ADV/ LD/ L X 0 0 1 WE X X 1 0 X BWSx X X X Valid X CLK L-H L-H L-H L-H L-H Comments I/Os three-state following next recognized clock. Clock ignored, all operations suspended. Address latched. Address latched, data presented two valid clocks later. Burst Read operation. Previous access was a Read operation. Addresses incremented internally in conjunction with the state of MODE. Burst Write operation. Previous access was a Write operation. Addresses incremented internally in conjunction with the state of MODE. Bytes written are determined by BWS[3:0]. Burst Write Operation Internal X 0 1 X Valid L-H Notes: 1. X=”Don't Care”, 1=Logic HIGH, 0=Logic LOW, CE stands for ALL Chip Enables active. BWSx = 0 signifies at least one Byte Write Select is active, BWSx = Valid signifies that the desired byte write selects are asserted, see Write Cycle Description table for details. 2. Write is defined by WE and BWS[3:0]. See Write Cycle Description table for details. 3. The DQ and DP pins are controlled by the current cycle and the OE signal. 4. CEN=1 inserts wait states. 5. Device will power-up deselected and the I/Os in a three-state condition, regardless of OE. 6. OE assumed LOW. Document #: 38-05045 Rev. ** Page 5 of 14 PRELIMINARY Write Cycle Description[7, 8] Function Read Write − No bytes written Write Byte 0 − (DQ[7:0] and DP0) Write Byte 1 − (DQ[15:8] and DP1) Write Bytes 1, 0 Write Byte 2 − (DQ[23:16] and DP2) Write Bytes 2, 0 Write Bytes 2, 1 Write Bytes 2, 1, 0 Write Byte 3 − (DQ[31:24] and DP3) Write Bytes 3, 0 Write Bytes 3, 1 Write Bytes 3, 1, 0 Write Bytes 3, 2 Write Bytes 3, 2, 0 Write Bytes 3, 2, 1 Write All Bytes WE 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BWS3 X 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 BWS2 X 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 CY7C1350B BWS1 X 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 BWS0 X 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature .................................. −65°C to +150°C Ambient Temperature with Power Applied .................................................. −55°C to +125°C Supply Voltage on VDD Relative to GND .........−0.5V to +4.6V DC Voltage Applied to Outputs in High Z State[9] .....................................−0.5V to VDDQ + 0.5V DC Input Voltage[9] ..................................−0.5V to VDDQ + 0.5V Current into Outputs (LOW) ........................................ 20 mA Static Discharge Voltage .......................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current.................................................... >200 mA Operating Range Range Com’l Ind’l Ambient Temperature[10] 0°C to +70°C 3.3V ± 5% –40°C to +85°C VDD/VDDQ Notes: 7. X=”Don't Care”, 1=Logic HIGH, 0=Logic LOW. 8. Write is initiated by the combination of WE and BWSx. Bytes written are determined by BWS[3:0]. Bytes not selected during byte writes remain unaltered. All I/Os are three-stated during byte writes. 9. Minimum voltage equals –2.0V for pulse duration less than 20 ns. 10. TA is the case temperature. Document #: 38-05045 Rev. ** Page 6 of 14 PRELIMINARY Electrical Characteristics Over the Operating Range Parameter VDD VDDQ VOH VOL VIH VIL IX Description Power Supply Voltage I/O Supply Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current Input Current of MODE IOZ ICC Output Leakage Current VDD Operating Supply GND ≤ VI ≤ VDDQ, Output Disabled VDD = Max., IOUT = 0 mA, f = fMAX = 1/tCYC 5.0-ns cycle, 166 MHz 6.6-ns cycle, 150 MHz 7.0-ns cycle, 143 MHz 7.5-ns cycle, 133 MHz 10.0-ns cycle, 100 MHz 12.5-ns cycle, 80 MHz ISB1 Automatic CE Power-Down Current—TTL Inputs Max. VDD, Device Deselected, VIN ≥ VIH or VIN ≤ VIL f = fMAX = 1/tCYC 5.0-ns cycle, 166 MHz 6.6-ns cycle, 150 MHz 7.0-ns cycle, 143 MHz 7.5-ns cycle, 133 MHz 10.0-ns cycle, 100 MHz 12.5-ns cycle, 80 MHz ISB2 Automatic CE Power-Down Current—CMOS Inputs Automatic CE Power-Down Current—CMOS Inputs Max. VDD, Device Deselected, VIN ≤ 0.3V or VIN > VDDQ – 0.3V, f = 0 Max. VDD, Device Deselected, or VIN ≤ 0.3V or VIN > VDDQ – 0.3V f = fMAX = 1/tCYC All speed grades [9] CY7C1350B Test Conditions Min. 3.135 3.135 Max. 3.465 3.465 0.4 Unit V V V V V V µA µA µA mA mA mA mA mA mA mA mA mA mA mA mA mA VDD = Min., IOH = –4.0 mA [11] 2.4 2.0 −0.3 VDD + 0.3V 0.8 5 30 5 400 375 350 300 250 200 80 70 60 50 40 35 5 VDD = Min., IOL = 8.0 mA[11] GND ≤ VI ≤ VDDQ −5 −30 −5 ISB3 5.0-ns cycle, 166 MHz 6.6-ns cycle, 150 MHz 7.0-ns cycle, 143 MHz 7.5-ns cycle, 133 MHz 10.0-ns cycle, 100 MHz 12.5-ns cycle, 80 MHz 70 60 50 40 30 25 mA mA mA mA mA mA Shaded areas contain advance information. Note: 11. The load used for VOH and VOL testing is shown in Figure (b) of the AC Test Loads. Document #: 38-05045 Rev. ** Page 7 of 14 PRELIMINARY Capacitance[12] Parameter CIN CCLK CI/O Description Input Capacitance Clock Input Capacitance Input/Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VDD = 3.3V, VDDQ = 3.3V Max. 4 4 4 CY7C1350B Unit pF pF pF AC Test Loads and Waveforms 3.3V Z0 =50Ω OUTPUT RL =50Ω VL = 1.5V 3.0V 5 pF INCLUDING JIG AND SCOPE R=351Ω GND R=317Ω [13] OUTPUT ALL INPUT PULSES (a) (b) 1350B-2 Thermal Resistance Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Still Air, soldered on a 4.25 x 1.125 inch, 4-layer printed circuit board Symbol ΘJA ΘJC TQFP Typ. 28 4 Units °C/W °C/W Notes 12 12 Notes: 12. Tested initially and after any design or process change that may affect these parameters. 13. A/C test conditions assume signal transition time of 2 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading shown in part (a) of AC Test Loads. Document #: 38-05045 Rev. ** Page 8 of 14 PRELIMINARY Switching Characteristics Over the Operating Range[13, 14, 15] -166 Parameter tCYC tCH tCL tAS tAH tCO tDOH tCENS tCENH tWES tWEH tALS tALH tDS tDH tCES tCEH tCHZ tCLZ tEOHZ tEOLZ tEOV Description Clock Cycle Time Clock HIGH Clock LOW Address Set-Up Before CLK Rise Address Hold After CLK Rise Data Output Valid After CLK Rise Data Output Hold After CLK Rise CEN Set-Up Before CLK Rise CEN Hold After CLK Rise GW, BWS[3:0] Set-Up Before CLK Rise GW, BWS[3:0] Hold After CLK Rise ADV/LD Set-Up Before CLK Rise ADV/LD Hold after CLK Rise Data Input Set-Up Before CLK Rise Chip Enable Set-Up Before CLK Rise Chip Enable Hold After CLK Rise Clock to High-Z[12, 14, 15, 16] Clock to Low-Z 14, 15, 16] [12, 14, 15, 16] [12, CY7C1350B -150 6.6 2.5 2.5 1.5 0.5 -143 7.0 2.8 2.8 2.0 0.5 -133 7.5 3.0 3.0 2.0 0.5 -100 10 4.0 4.0 2.2 0.5 -80 12.5 4.0 4.0 2.5 1.0 ns ns ns ns ns 7.0 1.5 2.5 1.0 2.5 1.0 2.5 1.0 2.5 1.0 2.5 1.0 ns ns ns ns ns ns ns ns ns ns ns ns 5.0 7.0 0 ns ns ns ns 7.0 ns Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit 5.0 1.4 1.4 1.5 0.5 3.5 1.5 1.5 0.5 1.5 0.5 1.5 0.5 1.5 1.5 0.5 1.5 0.5 1.5 0.5 1.5 0.5 1.5 0.5 3.2 3.0 0.0 3.2 0 3.5 1.5 1.5 3.0 0 4.0 3.2 3.8 1.5 2.0 0.5 2.0 0.5 2.0 0.5 1.7 0.5 2.0 0.5 1.5 1.5 4.0 1.5 2.0 0.5 2.0 0.5 2.0 0.5 1.7 0.5 2.0 0.5 3.5 4.0 0 1.5 1.5 4.2 1.5 2.2 0.5 2.2 0.5 2.2 0.5 2.0 0.5 2.2 0.5 3.5 4.2 0 4.2 1.5 1.5 5.0 Data Input Hold After CLK Rise 0.5 1.5 0.5 1.5 1.5 3.5 5.0 1.5 1.5 OE HIGH to Output High-Z 14, 15, 16] OE LOW to Output Low-Z[12, OE LOW to Output Valid[14] 5.0 Shaded areas contain advanced information. Notes: 14. tCHZ, tCLZ, tOEV, tEOLZ, and tEOHZ are specified with A/C test conditions shown in part (a) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage. 15. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z prior to Low-Z under the same system conditions. 16. This parameter is sampled and not 100% tested. Document #: 38-05045 Rev. ** Page 9 of 14 PRELIMINARY Switching Waveforms READ/WRITE/DESELECT Sequence WRITE DESELECT SUSPEND READ READ CY7C1350B DESELECT CLK tCH tCL tCYC tCENS tCENH CEN tAS tAH CEN HIGH blocks all synchronous inputs RA3 RA4 WA5 RA6 RA7 ADDRESS RA1 WA2 WE & BWS[3:0] tWS tWH tCES tCEH CE tDS tDH D2 In tCHZ tDOH Q3 Out Q4 Out D5 In Q6 Out tCHZ Q7 Out tCLZ tDOH Q1 Out DataIn/Out Device originally deselected tCO The combination of WE & BWS[3:0] define a write cycle (see Write Cycle Description table). CE is the combination of CE1, CE2, and CE3. All chip enables need to be active in order to select the device. Any chip enable can deselect the device. RAx stands for Read Address X, WAx stands for Write Address X, Dx stands for Data-in for location X, Qx stands for Data-out for location X. ADV/LD held LOW. OE held LOW. = DON’T CARE = UNDEFINED Document #: 38-05045 Rev. ** Page 10 of 14 DESELECT WRITE READ READ READ PRELIMINARY Switching Waveforms (continued) Burst Sequences Begin Read Burst Read Burst Read Burst Read Begin Read Begin Write Burst Write Burst Write Burst Write CY7C1350B CLK tALS tALH tCH tCL tCYC ADV/LD tAS tAH ADDRESS RA1 WA2 RA3 WE tWS tWH tWS tWH BWS[3:0] tCES tCEH CE tCHZ Q1+1 Out tCO Q1+2 Out Q1+3 Out tDS tCLZ D2+1 In D2+2 In D2+3 In Q3 Out tCLZ tDOH Q1 Out tDH D2 In DataIn/Out Device originally deselected tCO The combination of WE & BWS[3:0] define a write cycle (see Write Cycle Description table). CE is the combination of CE1, CE2, and CE3. All chip enables need to be active in order to select the device. Any chip enable can deselect the device. RAx stands for Read Address X, WA stands for Write Address X, Dx stands for Data-in for location X, Qx stands for Data-out for location X. CEN held LOW. During burst writes, byte writes can be conducted by asserting the appropriate BWS[3:0] input signals. Burst order determined by the state of the MODE input. CEN held LOW. OE held LOW. = DON’T CARE = UNDEFINED Document #: 38-05045 Rev. ** Burst Read Page 11 of 14 Burst Read PRELIMINARY Switching Waveforms (continued) OE Timing CY7C1350B OE tEOHZ tEOV I/O’s Three-state tEOLZ Ordering Information Speed (MHz) 166 150 143 133 Ordering Code CY7C1350B-166AC CY7C1350B-150AC CY7C1350B-143AC CY7C1350B-133AC CY7C1350B-133AI 100 CY7C1350B-100AC CY7C1350B-100AI Shaded areas contain advanced information. Package Name A101 A101 A101 A101 A101 A101 A101 Package Type 100-Lead (14 x 20 x 1.4 mm) Thin Quad Flat Pack 100-Lead (14 x 20 x 1.4 mm) Thin Quad Flat Pack 100-Lead (14 x 20 x 1.4 mm) Thin Quad Flat Pack 100-Lead (14 x 20 x 1.4 mm) Thin Quad Flat Pack 100-Lead (14 x 20 x 1.4 mm) Thin Quad Flat Pack 100-Lead (14 x 20 x 1.4 mm) Thin Quad Flat Pack 100-Lead (14 x 20 x 1.4 mm) Thin Quad Flat Pack Operating Range Commercial Commercial Commercial Commercial Industrial Commercial Industrial Document #: 38-05045 Rev. ** Page 12 of 14 PRELIMINARY CY7C1350B Package Diagram 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101 51-85050-A Document #: 38-05045 Rev. ** Page 13 of 14 © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. PRELIMINARY CY7C1350B Document Title: CY7C1350B 128K x 36 Pipelined SRAM with NoBL™ Architecture Document Number: 38-05045 REV. ** ECN NO. 109953 Issue Date 01/07/02 Orig. of Change SZV Description of Change Change from Spec number: 38-00910 to 38-05045 Document #: 38-05045 Rev. ** Page 14 of 14