CY7C1350B-133AI

350B PRELIMINARY CY7C1350B 128Kx36 Pipelined SRAM with NoBL™ Architecture Features Functional Description • Pin compatible and functionally equivalent to ZBT™ devices IDT71V546, MT55L128L36P, and MCM63Z736 • Supports 166-MHz bus operations with zero wait states — Data is transferred on every clock • Internally self-timed output buffer control to eliminate the need to use OE • Fully registered (inputs and outputs) for pipelined operation • Byte Write capability • 128K x 36 common I/O architecture • Single 3.3V power supply • Fast clock-to-output times — 3.5 ns (for 166-MHz device) — 3.8 ns (for 150-MHz device) — 4.0 ns (for 143-MHz device) — 4.2 ns (for 133-MHz device) All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable (CEN) signal, which when deasserted suspends operation and extends the previous clock cycle. Maximum access delay from the clock rise is 3.5 ns (166-MHz device). Write operations are controlled by the four Byte Write Select (BWS[3:0]) and a Write Enable (WE) input. All writes are conducted with on-chip synchronous self-timed write circuitry. — 5.0 ns (for 100-MHz device) • • • • • • The CY7C1350B is a 3.3V, 128K by 36 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1350B is equipped with the advanced No Bus Latency™ (NoBL™) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of the SRAM, especially in systems that require frequent Write/Read transitions. The CY7C1350B is pin/functionally compatible to ZBT SRAMs IDT71V546, MT55L128L36P, and MCM63Z736. — 7.0 ns (for 80-MHz device) Clock Enable (CEN) pin to suspend operation Synchronous self-timed writes Asynchronous output enable JEDEC-standard 100 TQFP package Burst Capability—linear or interleaved burst order Low standby power (17.325 mW max.) Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output three-state control. In order to avoid bus contention, the output drivers are synchronously three-stated during the data portion of a write sequence. Logic Block Diagram CE ADV/LD A[16:0] 36 D Data-In REG. Q 36 17 CEN CE1 CE2 CE3 WE BWS[3:0] MODE CONTROL and WRITE LOGIC 36 128Kx36 MEMORY ARRAY 17 CLK OOUTPUT REGISTERS and LOGIC CLK 36 DQ[31:0] DP[3:0] OE . Selection Guide Maximum Access Time (ns) -166 -150 -143 -133 -100 -80 3.5 3.8 4.0 4.2 5.0 7.0 Maximum Operating Current (mA) Commercial 400 375 350 300 250 200 Maximum CMOS Standby Current (mA) Commercial 5 5 5 5 5 5 Shaded areas contain advance information. NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device Technology. Cypress Semiconductor Corporation Document #: 38-05045 Rev. *A • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised January 18, 2003 PRELIMINARY CY7C1350B Pin Configuration VSS CLK WE CEN OE ADV/LD 90 89 88 87 86 85 A9 VDD 91 81 CE3 92 A8 BWS0 93 82 BWS1 94 NC BWS2 95 83 BWS3 96 NC CE2 97 84 A7 CE1 98 A6 99 100 100-Pin TQFP 1 80 DP1 2 79 DQ15 DQ17 3 78 DQ14 VDDQ 4 77 VDDQ VSS 5 76 VSS DQ18 6 75 DQ13 DQ19 7 74 DQ12 DQ20 8 73 DQ11 DQ21 9 72 DQ10 VSS 10 71 VSS VDDQ 11 70 VDDQ DQ22 12 69 DQ9 DQ23 13 68 DQ8 VDDQ 14 67 VSS VDD 15 66 VDD VDD 16 65 VSS 17 64 VDD VSS DQ24 18 63 DQ7 DQ25 19 62 DQ6 VDDQ 20 61 VDDQ VSS 21 60 VSS DQ26 22 59 DQ5 DQ27 23 58 DQ4 DQ28 24 57 DQ3 DQ29 25 56 DQ2 VSS 26 55 VSS VDDQ 27 54 VDDQ DQ30 28 53 DQ1 DQ31 29 52 DQ0 DP3 30 51 DP0 Document #: 38-05045 Rev. *A 46 47 48 49 50 A13 A14 A15 A16 41 VDD A12 40 VSS 45 39 DNU 44 38 DNU A11 37 A0 A10 36 A1 43 35 A2 DNU 34 A3 DNU 33 42 32 A4 CY7C1350B A5 MODE 31 DP2 DQ16 Page 2 of 14 PRELIMINARY CY7C1350B Pin Definitions Pin Number Name I/O Description 50–44, 81–82, 99, 100, 32–37 A[16:0] InputSynchronous Address Inputs used to select one of the 131,072 address locations. Sampled at the rising edge of the CLK. 96–93 BWS[3:0] InputSynchronous Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on the rising edge of CLK. BWS0 controls DQ[7:0] and DP0, BWS1 controls DQ[15:8] and DP1, BWS2 controls DQ[23:16] and DP2, BWS3 controls DQ[31:24] and DP3. See Write Cycle Description table for details. 88 WE InputSynchronous Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal must be asserted LOW to initiate a write sequence. 85 ADV/LD InputSynchronous Advance/Load Input used to advance the on-chip address counter or load a new address. When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address can be loaded into the device for an access. After being deselected, ADV/LD should be driven LOW in order to load a new address. 89 CLK Input-Clock Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is only recognized if CEN is active LOW. 98 CE1 InputSynchronous Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2, and CE3 to select/deselect the device. 97 CE2 InputSynchronous Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3 to select/deselect the device. 92 CE3 InputSynchronous Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select/deselect the device. 86 OE InputAsynchronous Output Enable, active LOW. Combined with the synchronous logic block inside the device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE is masked during the data portion of a write sequence, during the first clock when emerging from a deselected state, when the device has been deselected. 87 CEN InputSynchronous Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized by the SRAM. When deasserted HIGH the Clock signal is masked. Since deasserting CEN does not deselect the device, CEN can be used to extend the previous cycle when required. 29–28, DQ[31:0] 25–22, 19–18, 13–12, 9–6, 3–2, 79–78, 75–72, 69–68, 63–62 59–56, 53–52 I/OSynchronous Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by A[16:0] during the previous clock rise of the read cycle. The direction of the pins is controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH, DQ[31:0] are placed in a three-state condition. The outputs are automatically three-stated during the data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of OE. 30, 1, 80 51 DP[3:0] I/OSynchronous Bidirectional Data Parity I/O lines. Functionally, these signals are identical to DQ[31:0]. During write sequences, DP0 is controlled by BWS0, DP1 is controlled by BWS1, DP2 is controlled by BWS2, and DP3 is controlled by BWS3. 31 MODE Input Strap pin Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order. Pulled LOW selects the linear burst order. MODE should not change states during operation. When left floating MODE will default HIGH, to an interleaved burst order. 15, 16, 41, 65, 66, 91 VDD Power Supply Power supply inputs to the core of the device. Should be connected to 3.3V power supply. 4, 11, 14, 20, 27, 54, 61, 70, 77 VDDQ I/O Power Supply Power supply for the I/O circuitry. Should be connected to a 3.3V power supply. Document #: 38-05045 Rev. *A Page 3 of 14 PRELIMINARY CY7C1350B Pin Definitions (continued) Pin Number Name I/O Description 5, 10, 17, 21, 26, 40, 55, 60, 64, 67, 71, 76, 90 VSS Ground 83, 84 NC - No connects. Reserved for address inputs for depth expansion. Pin 83 and 84 will be used for 256K and 512K depths respectively. - Do Not Use pins. These pins should be left floating or tied to VSS. 38, 39, 42, 43 DNU Ground for the device. Should be connected to ground of the system. Introduction Functional Overview The CY7C1350B is a synchronous-pipelined Burst SRAM designed specifically to eliminate wait states during Write/Read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock signal is qualified with the Clock Enable input signal (CEN). If CEN is HIGH, the clock signal is not recognized and all internal states are maintained. All synchronous operations are qualified with CEN. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (tCO) is 3.5 ns (166-MHz device). Accesses can be initiated by asserting all three Chip Enables (CE1, CE2, CE3) active at the rising edge of the clock. If Clock Enable (CEN) is active LOW and ADV/LD is asserted LOW, the address presented to the device will be latched. The access can either be a read or write operation, depending on the status of the Write Enable (WE). BWS[3:0] can be used to conduct byte write operations. Write operations are qualified by the Write Enable (WE). All writes are simplified with on-chip synchronous self-timed write circuitry. Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) simplify depth expansion. All operations (Reads, Writes, and Deselects) are pipelined. ADV/LD should be driven LOW once the device has been deselected in order to load a new address for the next operation. Single Read Accesses A read access is initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2, and CE3 are ALL asserted active, (3) the Write Enable input signal WE is deasserted HIGH, and (4) ADV/LD is asserted LOW. The address presented to the address inputs (A0−A16) is latched into the Address Register and presented to the memory core and control logic. The control logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At the rising edge of the next clock the requested data is allowed to propagate through the output register and onto the data bus within 3.5 ns (166-MHz device) provided OE is active LOW. After the first clock of the read access the output buffers are controlled by OE and the internal control logic. OE must be driven LOW in order for the device to drive out the requested data. During the second clock, a subsequent operation (Read/Write/Deselect) can be initiated. Deselecting the device is also pipelined. Therefore, when the SRAM is deselected at clock rise by one of the chip enable signals, its output will three-state following the next clock rise. Document #: 38-05045 Rev. *A Burst Read Accesses The CY7C1350B has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four Reads without reasserting the address inputs. ADV/LD must be driven LOW in order to load a new address into the SRAM, as described in the Single Read Access section above. The sequence of the burst counter is determined by the MODE input signal. A LOW input on MODE selects a linear burst mode, a HIGH selects an interleaved burst sequence. Both burst counters use A0 and A1 in the burst sequence, and will wrap-around when incremented sufficiently. A HIGH input on ADV/LD will increment the internal burst counter regardless of the state of chip enables inputs or WE. WE is latched at the beginning of a burst cycle. Therefore, the type of access (Read or Write) is maintained throughout the burst sequence. Single Write Accesses Write access are initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2, and CE3 are ALL asserted active, and (3) the write signal WE is asserted LOW. The address presented to A0−A16 is loaded into the Address Register. The write signals are latched into the Control Logic block. On the subsequent clock rise the data lines are automatically three-stated regardless of the state of the OE input signal. This allows the external logic to present the data on DQ[31:0] and DP[3:0]. In addition, the address for the subsequent access (Read/Write/Deselect) is latched into the Address Register (provided the appropriate control signals are asserted). On the next clock rise the data presented to DQ[31:0] and DP[3:0] (or a subset for byte write operations, see Write Cycle Description table for details) inputs is latched into the device and the write is complete. The data written during the Write operation is controlled by BWS[3:0] signals. The CY7C1350B provides byte write capability that is described in the Write Cycle Description table. Asserting the Write Enable input (WE) with the selected Byte Write Select (BWS[3:0]) input will selectively write to only the desired bytes. Bytes not selected during a byte write operation will remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. Byte write capability has been included in order to greatly simplify Read/Modify/Write sequences, which can be reduced to simple byte write operations. Because the CY7C1350B is a common I/O device, data should not be driven into the device while the outputs are active. The Output Enable (OE) can be deasserted HIGH before presenting data to the DQ[31:0] and DP[3:0] inputs. Doing so will three-state the output drivers. As a safety precaution, DQ[31:0] Page 4 of 14 PRELIMINARY and DP[3:0] are automatically three-stated during the data portion of a write cycle, regardless of the state of OE. CY7C1350B Linear Burst Sequence Burst Write Accesses First Address The CY7C1350B has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four WRITE operations without reasserting the address inputs. ADV/LD must be driven LOW in order to load the initial address, as described in the Single Write Access section above. When ADV/LD is driven HIGH on the subsequent clock rise, the chip enables (CE1, CE2, and CE3) and WE inputs are ignored and the burst counter is incremented. The correct BWS[3:0] inputs must be driven in each cycle of the burst write in order to write the correct bytes of data. Second Address Third Address Fourth Address Ax+1, Ax Ax+1, Ax Ax+1, Ax Ax+1, Ax 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 Interleaved Burst Sequence First Address Second Address Third Address Fourth Address Ax+1, Ax Ax+1, Ax Ax+1, Ax Ax+1, Ax 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 Cycle Description Truth Table[1, 2, 3, 4, 5, 6] Address Used Operation CE CEN ADV/ LD/ WE BWSx CLK Comments Deselected External 1 0 L X X L-H I/Os three-state following next recognized clock. Suspend - X 1 X X X L-H Clock ignored, all operations suspended. Begin Read External 0 0 0 1 X L-H Address latched. Begin Write External 0 0 0 0 Valid L-H Address latched, data presented two valid clocks later. Burst Read Operation Internal X 0 1 X X L-H Burst Read operation. Previous access was a Read operation. Addresses incremented internally in conjunction with the state of MODE. Burst Write Operation Internal X 0 1 X Valid L-H Burst Write operation. Previous access was a Write operation. Addresses incremented internally in conjunction with the state of MODE. Bytes written are determined by BWS[3:0]. Notes: 1. X=”Don't Care”, 1=Logic HIGH, 0=Logic LOW, CE stands for ALL Chip Enables active. BWSx = 0 signifies at least one Byte Write Select is active, BWSx = Valid signifies that the desired byte write selects are asserted, see Write Cycle Description table for details. 2. Write is defined by WE and BWS[3:0]. See Write Cycle Description table for details. 3. The DQ and DP pins are controlled by the current cycle and the OE signal. 4. CEN=1 inserts wait states. 5. Device will power-up deselected and the I/Os in a three-state condition, regardless of OE. 6. OE assumed LOW. Document #: 38-05045 Rev. *A Page 5 of 14 PRELIMINARY CY7C1350B Write Cycle Description[7, 8] Function WE BWS3 BWS2 BWS1 BWS0 1 X X X X Read Write − No bytes written 0 1 1 1 1 Write Byte 0 − (DQ[7:0] and DP0) 0 1 1 1 0 Write Byte 1 − (DQ[15:8] and DP1) 0 1 1 0 1 Write Bytes 1, 0 0 1 1 0 0 Write Byte 2 − (DQ[23:16] and DP2) 0 1 0 1 1 Write Bytes 2, 0 0 1 0 1 0 Write Bytes 2, 1 0 1 0 0 1 Write Bytes 2, 1, 0 0 1 0 0 0 Write Byte 3 − (DQ[31:24] and DP3) 0 0 1 1 1 Write Bytes 3, 0 0 0 1 1 0 Write Bytes 3, 1 0 0 1 0 1 Write Bytes 3, 1, 0 0 0 1 0 0 Write Bytes 3, 2 0 0 0 1 1 Write Bytes 3, 2, 0 0 0 0 1 0 Write Bytes 3, 2, 1 0 0 0 0 1 Write All Bytes 0 0 0 0 0 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Current into Outputs (LOW) ........................................ 20 mA Static Discharge Voltage .......................................... >2001V (per MIL-STD-883, Method 3015) Storage Temperature .................................. −65°C to +150°C Latch-Up Current.................................................... >200 mA Ambient Temperature with Power Applied.................................................. −55°C to +125°C Operating Range Supply Voltage on VDD Relative to GND.........−0.5V to +4.6V Range DC Voltage Applied to Outputs in High Z State[9] .....................................−0.5V to VDDQ + 0.5V Com’l DC Input Voltage[9] ..................................−0.5V to VDDQ + 0.5V Ind’l Ambient Temperature[10] VDD/VDDQ 0°C to +70°C 3.3V ± 5% –40°C to +85°C Notes: 7. X=”Don't Care”, 1=Logic HIGH, 0=Logic LOW. 8. Write is initiated by the combination of WE and BWSx. Bytes written are determined by BWS[3:0]. Bytes not selected during byte writes remain unaltered. All I/Os are three-stated during byte writes. 9. Minimum voltage equals –2.0V for pulse duration less than 20 ns. 10. TA is the case temperature. Document #: 38-05045 Rev. *A Page 6 of 14 PRELIMINARY CY7C1350B Electrical Characteristics Over the Operating Range Parameter Description Test Conditions VDD Power Supply Voltage VDDQ I/O Supply Voltage [11] VOH Output HIGH Voltage VDD = Min., IOH = –4.0 mA VOL Output LOW Voltage VDD = Min., IOL = 8.0 mA[11] VIH Input HIGH Voltage VIL Input LOW Voltage IX Input Load Current GND ≤ VI ≤ VDDQ GND ≤ VI ≤ VDDQ, Output Disabled ICC VDD Operating Supply VDD = Max., IOUT = 0 mA, f = fMAX = 1/tCYC ISB1 Automatic CE Power-Down Current—TTL Inputs Max. VDD, Device Deselected, VIN ≥ VIH or VIN ≤ VIL f = fMAX = 1/tCYC Unit 3.135 3.465 V 3.135 3.465 V V 0.4 V 2.0 VDD + 0.3V V −0.3 0.8 V −5 5 µA −30 30 µA −5 5 µA 5.0-ns cycle, 166 MHz 400 mA 6.6-ns cycle, 150 MHz 375 mA 7.0-ns cycle, 143 MHz 350 mA 7.5-ns cycle, 133 MHz 300 mA 10.0-ns cycle, 100 MHz 250 mA 12.5-ns cycle, 80 MHz 200 mA 5.0-ns cycle, 166 MHz 80 mA 6.6-ns cycle, 150 MHz 70 mA 7.0-ns cycle, 143 MHz 60 mA 7.5-ns cycle, 133 MHz 50 mA 10.0-ns cycle, 100 MHz 40 mA 12.5-ns cycle, 80 MHz 35 mA Input Current of MODE Output Leakage Current Max. 2.4 [9] IOZ Min. ISB2 Automatic CE Power-Down Current—CMOS Inputs Max. VDD, Device Deselected, VIN ≤ 0.3V or VIN > VDDQ – 0.3V, f = 0 All speed grades 5 mA ISB3 Automatic CE Power-Down Current—CMOS Inputs Max. VDD, Device Deselected, or VIN ≤ 0.3V or VIN > VDDQ – 0.3V f = fMAX = 1/tCYC 5.0-ns cycle, 166 MHz 70 mA 6.6-ns cycle, 150 MHz 60 mA 7.0-ns cycle, 143 MHz 50 mA 7.5-ns cycle, 133 MHz 40 mA 10.0-ns cycle, 100 MHz 30 mA 12.5-ns cycle, 80 MHz 25 mA Shaded areas contain advance information. Note: 11. The load used for VOH and VOL testing is shown in Figure (b) of the AC Test Loads. Document #: 38-05045 Rev. *A Page 7 of 14 PRELIMINARY CY7C1350B Capacitance[12] Parameter Description Test Conditions CIN Input Capacitance TA = 25°C, f = 1 MHz, VDD = 3.3V, VDDQ = 3.3V CCLK Clock Input Capacitance CI/O Input/Output Capacitance Max. Unit 4 pF 4 pF 4 pF AC Test Loads and Waveforms [13] R=317Ω 3.3V OUTPUT [14] OUTPUT Z0 =50Ω RL =50Ω VL = 1.5V (a) ALL INPUT PULSES 3.0V 5 pF INCLUDING JIG AND SCOPE R=351Ω (b) GND 1350B-2 Thermal Resistance Description Thermal Resistance (Junction to Ambient) Test Conditions Still Air, soldered on a 4.25 x 1.125 inch, 4-layer printed circuit board Thermal Resistance (Junction to Case) Symbol TQFP Typ. Units Notes ΘJA 28 °C/W 12 ΘJC 4 °C/W 12 Notes: 12. Tested initially and after any design or process change that may affect these parameters. 13. Overshoot: VIH(AC) < VDD + 1.5V for t < tTCYC/2; undershoot: VIL(AC) < 0.5V for t < tTCYC/2; power-up: VIH < 2.6V and VDD < 2.4V and VDDQ < 1.4V for t < 200 ms. 14. A/C test conditions assume signal transition time of 2 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading shown in part (a) of AC Test Loads. Document #: 38-05045 Rev. *A Page 8 of 14 PRELIMINARY CY7C1350B Switching Characteristics Over the Operating Range[14, 15, 16] -166 Parameter Description -150 -143 -133 -100 -80 Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit tCYC Clock Cycle Time 5.0 6.6 7.0 7.5 10 12.5 ns tCH Clock HIGH 1.4 2.5 2.8 3.0 4.0 4.0 ns tCL Clock LOW 1.4 2.5 2.8 3.0 4.0 4.0 ns tAS Address Set-Up Before CLK Rise 1.5 1.5 2.0 2.0 2.2 2.5 ns tAH Address Hold After CLK Rise 0.5 0.5 0.5 0.5 0.5 1.0 ns tCO Data Output Valid After CLK Rise tDOH Data Output Hold After CLK Rise 1.5 tCENS CEN Set-Up Before CLK Rise 1.5 tCENH CEN Hold After CLK Rise 0.5 tWES GW, BWS[3:0] Set-Up Before CLK Rise tWEH 3.5 3.8 4.0 4.2 5.0 7.0 ns 1.5 1.5 1.5 1.5 ns 1.5 2.0 2.0 2.2 2.5 ns 0.5 0.5 0.5 0.5 1.0 ns 1.5 1.5 2.0 2.0 2.2 2.5 ns GW, BWS[3:0] Hold After CLK Rise 0.5 0.5 0.5 0.5 0.5 1.0 ns tALS ADV/LD Set-Up Before CLK Rise 1.5 1.5 2.0 2.0 2.2 2.5 ns tALH ADV/LD Hold after CLK Rise 0.5 0.5 0.5 0.5 0.5 1.0 ns tDS Data Input Set-Up Before CLK Rise 1.5 1.5 1.7 1.7 2.0 2.5 ns tDH Data Input Hold After CLK Rise 0.5 0.5 0.5 0.5 0.5 1.0 ns tCES Chip Enable Set-Up Before CLK Rise 1.5 1.5 2.0 2.0 2.2 2.5 ns tCEH Chip Enable Hold After CLK Rise 0.5 0.5 0.5 0.5 0.5 1.0 ns tCHZ Clock to High-Z[12, 15, 16, 17] 1.5 tCLZ [12, 15, 16, 17] 1.5 tEOHZ tEOLZ tEOV Clock to Low-Z OE HIGH to Output High-Z [12, OE LOW to Output Low-Z[12, OE LOW to Output Valid[15] 1.5 3.2 1.5 3.0 15, 16, 17] 15, 16, 17] 3.2 0.0 3.5 1.5 3.0 0 3.2 1.5 3.5 1.5 4.0 0 3.5 1.5 3.5 1.5 4.2 0 4.0 1.5 5.0 1.5 5.0 0 4.2 1.5 ns 7.0 0 5.0 ns ns ns 7.0 ns Shaded areas contain advanced information. Notes: 15. tCHZ, tCLZ, tOEV, tEOLZ, and tEOHZ are specified with A/C test conditions shown in part (a) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage. 16. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z prior to Low-Z under the same system conditions. 17. This parameter is sampled and not 100% tested. Document #: 38-05045 Rev. *A Page 9 of 14 PRELIMINARY CY7C1350B Switching Waveforms DESELECT DESELECT SUSPEND READ READ WRITE READ DESELECT READ READ WRITE READ/WRITE/DESELECT Sequence CLK tCH tCL tCENS tCYC tCENH CEN tAS tAH ADDRESS WE & BWS[3:0] CEN HIGH blocks all synchronous inputs WA2 RA1 RA3 RA4 WA5 RA6 RA7 tWS tWH tCES tCEH CE tDOH tCLZ DataIn/Out Q1 Out Device originally deselected tDS tDH tCHZ tCHZ tDOH D2 In Q3 Out Q4 Out D5 In Q6 Out Q7 Out tCO The combination of WE & BWS[3:0] define a write cycle (see Write Cycle Description table). CE is the combination of CE1, CE2, and CE3. All chip enables need to be active in order to select the device. Any chip enable can deselect the device. RAx stands for Read Address X, WAx stands for Write Address X, Dx stands for Data-in for location X, Qx stands for Data-out for location X. ADV/LD held LOW. OE held LOW. = DON’T CARE Document #: 38-05045 Rev. *A = UNDEFINED Page 10 of 14 PRELIMINARY CY7C1350B Switching Waveforms (continued) Burst Read Burst Read Begin Read Burst Write Burst Write Burst Write Begin Write Burst Read Burst Read Burst Read Begin Read Burst Sequences CLK tALH tALS tCH tCL tCYC ADV/LD tAS tAH ADDRESS RA1 WA2 RA3 WE tWS tWH tWS tWH BWS[3:0] tCES tCEH CE DataIn/Out tCHZ tDOH tCLZ Q1 Out Device originally deselected tCO Q1+1 Out Q1+2 Out tCO tCLZ tDH Q1+3 Out D2 In D2+1 In D2+2 In D2+3 In Q3 Out tDS The combination of WE & BWS[3:0] define a write cycle (see Write Cycle Description table). CE is the combination of CE1, CE2, and CE3. All chip enables need to be active in order to select the device. Any chip enable can deselect the device. RAx stands for Read Address X, WA stands for Write Address X, Dx stands for Data-in for location X, Qx stands for Data-out for location X. CEN held LOW. During burst writes, byte writes can be conducted by asserting the appropriate BWS[3:0] input signals. Burst order determined by the state of the MODE input. CEN held LOW. OE held LOW. = DON’T CARE Document #: 38-05045 Rev. *A = UNDEFINED Page 11 of 14 PRELIMINARY CY7C1350B Switching Waveforms (continued) OE Timing OE tEOV tEOHZ Three-state I/O’s tEOLZ Ordering Information Speed (MHz) Ordering Code Package Name Package Type Operating Range 166 CY7C1350B-166AC A101 100-Lead (14 x 20 x 1.4 mm) Thin Quad Flat Pack Commercial 150 CY7C1350B-150AC A101 100-Lead (14 x 20 x 1.4 mm) Thin Quad Flat Pack Commercial 143 CY7C1350B-143AC A101 100-Lead (14 x 20 x 1.4 mm) Thin Quad Flat Pack Commercial 133 CY7C1350B-133AC A101 100-Lead (14 x 20 x 1.4 mm) Thin Quad Flat Pack Commercial CY7C1350B-133AI A101 100-Lead (14 x 20 x 1.4 mm) Thin Quad Flat Pack Industrial CY7C1350B-100AC A101 100-Lead (14 x 20 x 1.4 mm) Thin Quad Flat Pack Commercial CY7C1350B-100AI A101 100-Lead (14 x 20 x 1.4 mm) Thin Quad Flat Pack Industrial 100 Shaded areas contain advanced information. Document #: 38-05045 Rev. *A Page 12 of 14 PRELIMINARY CY7C1350B Package Diagram 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101 51-85050-A Document #: 38-05045 Rev. *A Page 13 of 14 © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. PRELIMINARY CY7C1350B Document Title: CY7C1350B 128K x 36 Pipelined SRAM with NoBL™ Architecture Document Number: 38-05045 REV. ECN NO. Issue Date Orig. of Change ** 109953 01/07/02 SZV Change from Spec number: 38-00910 to 38-05045 *A 123109 01/18/03 RBI Add power up requirements to AC test loads and waveforms information Document #: 38-05045 Rev. *A Description of Change Page 14 of 14