CY7C1352B-133AC

PRELIMINARY CY7C1352B 256K x18 Pipelined SRAM with NoBL™ Architecture • Low standby power Features Functional Description The CY7C1352B is a 3.3V 256K by 18 synchronous-pipelined Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1352B is equipped with the advanced No Bus Latency™ (NoBL™) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of the SRAM, especially in systems that require frequent Read/Write transitions. The CY7C1352B is pin/functionally compatible to ZBT SRAMs MCM63Z819 and MT55L256L18P. All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable (CEN) signal, which when deasserted suspends operation and extends the previous clock cycle. Maximum access delay from the clock rise is 3.5 ns (166-MHz device). Write operations are controlled by the four Byte Write Select (BWS[1:0]) and a Write Enable (WE) input. All writes are conducted with on-chip synchronous self-timed write circuitry. Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output three-state control. In order to avoid bus contention, the output drivers are synchronously three-stated during the data portion of a write sequence. Logic Block Diagram CLK CE ADV/LD A[17:0] 18 D Data-In REG. Q 18 18 CEN CE1 CE2 CE3 WE BWS [1:0] Mode CONTROL and WRITE LOGIC 256Kx18 MEMORY ARRAY 18 18 CLK OUTPUT REGISTERS and LOGIC • Pin compatible and functionally equivalent to ZBT™ devices MCM63Z818 and MT55L256L18P • Supports 166-MHz bus operations with zero wait states — Data is transferred on every clock • Internally self-timed output buffer control to eliminate the need to use OE • Fully registered (inputs and outputs) for pipelined operation • Byte Write Capability • 256K x 18 common I/O architecture • Single 3.3V power supply • Fast clock-to-output times — 3.5 ns (for 166-MHz device) — 3.8 ns (for 150-MHz device) — 4.0 ns (for 143-MHz device) — 4.2 ns (for 133-MHz device) — 5.0 ns (for 100-MHz device) — 7.0 ns (for 80-MHz device) • Clock Enable (CEN) pin to suspend operation • Synchronous self-timed writes • Asynchronous output enable • JEDEC-standard 100-pin TQFP package • Burst Capability—linear or interleaved burst order 18 DQ[15:0] DP[1:0] OE . Selection Guide Maximum Access Time (ns) Maximum Operating Current (mA) Commercial Maximum CMOS Standby Current (mA) Commercial -166 -150 -143 -133 -100 -80 3.5 3.8 4.0 4.2 5.0 7.0 400 375 350 300 250 200 5 5 5 5 5 5 Shaded areas contain advance information. NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device Technology. Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 May 26, 2000 PRELIMINARY CY7C1352B Pin Configuration A8 A9 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 A6 A7 CE1 CE2 NC NC BWS1 BWS0 CE3 VDD VSS CLK WE CEN OE ADV/LD NC NC 100-Pin TQFP CY7C1352B 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 2 A16 DNU DNU A10 A11 A12 A13 A14 A15 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 VDDQ VSS NC NC DQ8 DQ9 VSS VDDQ DQ10 DQ11 VDDQ VDD VDD VSS DQ12 DQ13 VDDQ VSS DQ14 DQ15 DP1 NC VSS VDDQ NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 MODE A5 A4 A3 A2 A1 A0 DNU DNU VSS VDD NC NC NC A17 NC NC VDDQ VSS NC DP0 DQ7 DQ6 VSS VDDQ DQ5 DQ4 VSS VDD VDD VSS DQ3 DQ2 VDDQ VSS DQ1 DQ0 NC NC VSS VDDQ NC NC NC PRELIMINARY CY7C1352B Pin Definitions Pin Number Name 80, 50−44, 81− A[17:0] 82, 99− 100, 32−37 94, 93 BWS[1:0] I/O InputSynchronous Description Address Inputs used to select one of the 262,144 address locations. Sampled at the rising edge of the CLK. InputSynchronous 88 WE 85 ADV/LD InputSynchronous InputSynchronous 89 CLK Input-Clock 98 CE1 97 CE2 92 CE3 86 OE InputSynchronous InputSynchronous InputSynchronous InputAsynchronous 87 CEN InputSynchronous 23−22, 19−18, 13−12, 9−8, 73−72, 69−68, 63−62, 59−58 DQ[15:0] I/OSynchronous 24, 74 DP[1:0] I/OSynchronous 31 MODE Input Strap pin 15, 16, 41, 65, 66, 91 4, 11, 14, 20, 27, 54, 61, 70, 77 5, 10, 17, 21, 26, 40, 55, 60, 64, 67, 71, 76, 90 VDD Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on the rising edge of CLK. BWS0 controls DQ[7:0] and DP0, BWS1 controls DQ[15:8] and DP1. See Write Cycle Description table for details. Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal must be asserted LOW to initiate a write sequence. Advance/Load Input used to advance the on-chip address counter or load a new address. When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW, a new address can be loaded into the device for an access. After being deselected, ADV/LD should be driven LOW in order to load a new address. Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is only recognized if CEN is active LOW. Chip Enable 1 Input active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 and CE3 to select/deselect the device. Chip Enable 2 Input active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3 to select/deselect the device. Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select/deselect the device. Output Enable, active LOW. Combined with the synchronous logic block inside the device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE is masked during the data portion of a write sequence, during the first clock when emerging from a deselected state, when the device has been deselected. Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized by the SRAM. When deasserted HIGH the Clock signal is masked. Since deasserting CEN does not deselect the device, CEN can be used to extend the previous cycle when required. Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by A[16:0] during the previous clock rise of the read cycle. The direction of the pins is controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH, DQ [15:0] are placed in a three-state condition. The outputs are automatically three-stated during the data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of OE. Bidirectional Data Parity I/O lines. Functionally, these signals are identical to DQ [15:0]. During write sequences, DP0 is controlled by BWS0 and DP 1 is controlled by BWS1 Mode input. Selects the burst order of the device. Tied HIGH selects the interleaved burst order. Pulled LOW selects the linear burst order. MODE should not change states during operation. When left floating, MODE will default HIGH to an interleaved burst order. Power supply inputs to the core of the device. Should be connected to 3.3V power supply. Power supply for the I/O circuitry. Should be connected to a 3.3V power supply. VDDQ VSS Power Supply I/O Power Supply Ground Ground for the device. Should be connected to ground of the system. 3 PRELIMINARY CY7C1352B Pin Definitions (continued) Pin Number Name 1−3, 6−7, 25, NC 28−30, 51−53, 56−57, 75, 78− 79, 95−96 83, 84 NC 38, 39, 42, 43 DNU I/O - - Description No Connects. These pins are not connected to the internal device. No Connects. Reserved for address inputs for depth expansion. Pin 83 is reserved for 512K depth and pin 84 is reserved for 1-Mb depth devices. Do Not Use pins. These pins should be left floating or tied to VSS. Burst Read Accesses Introduction The CY7C1352B has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four Reads without reasserting the address inputs. ADV/LD must be driven LOW in order to load a new address into the SRAM, as described in the Single Read Access section above. The sequence of the burst counter is determined by the MODE input signal. A LOW input on MODE selects a linear burst mode, a HIGH selects an interleaved burst sequence. Both burst counters use A0 and A1 in the burst sequence, and will wrap-around when incremented sufficiently. A HIGH input on ADV/LD will increment the internal burst counter regardless of the state of chip enables inputs or WE. WE is latched at the beginning of a burst cycle. Therefore, the type of access (Read or Write) is maintained throughout the burst sequence. Functional Overview The CY7C1352B is a synchronous-pipelined Burst SRAM designed specifically to eliminate wait states during Write-Read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock signal is qualified with the Clock Enable input signal (CEN). If CEN is HIGH, the clock signal is not recognized and all internal states are maintained. All synchronous operations are qualified with CEN. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (tCO) is 3.5 ns (166-MHz device). Accesses can be initiated by asserting all three chip enables (CE1, CE2, CE3) active at the rising edge of the clock. If Clock Enable (CEN) is active LOW and ADV/LD is asserted LOW, the address presented to the device will be latched. The access can either be a read or write operation, depending on the status of the Write Enable (WE). BWS[1:0] can be used to conduct byte write operations. Single Write Accesses Write accesses are initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2, and CE3 are ALL asserted active, and (3) the write signal WE is asserted LOW. The address presented to A0−A17 is loaded into the Address Register. The write signals are latched into the Control Logic block. Write operations are qualified by the Write Enable (WE). All writes are simplified with on-chip synchronous self-timed write circuitry. On the subsequent clock rise the data lines are automatically three-stated regardless of the state of the OE input signal. This allows the external logic to present the data on DQ[15:0] and DP [1:0]. In addition, the address for the subsequent access (Read/Write/Deselect) is latched into the Address Register (provided the appropriate control signals are asserted). Three synchronous Chip Enables (CE1, CE 2, CE 3) and an asynchronous Output Enable (OE) simplify depth expansion. All operations (Reads, Writes, and Deselects) are pipelined. ADV/LD should be driven LOW once the device has been deselected in order to load a new address for the next operation. Single Read Accesses On the next clock rise the data presented to DQ[15:0] and DP [1:0] (or a subset for byte write operations, see Write Cycle Description table for details) inputs is latched into the device and the write is complete. A read access is initiated when the following conditions are satisfied at clock rise: (1) CEN is asserted LOW, (2) CE1, CE2, and CE3 are ALL asserted active, (3) the Write Enable input signal WE is deasserted HIGH, and (4) ADV/LD is asserted LOW. The address presented to the address inputs (A 0−A17) is latched into the Address Register and presented to the memory core and control logic. The control logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At the rising edge of the next clock the requested data is allowed to propagate through the output register and onto the data bus within 3.5 ns (166-MHz device) provided OE is active LOW. After the first clock of the read access the output buffers are controlled by OE and the internal control logic. OE must be driven LOW in order for the device to drive out the requested data. During the second clock, a subsequent operation (Read/Write/Deselect) can be initiated. Deselecting the device is also pipelined. Therefore, when the SRAM is deselected at clock rise by one of the chip enable signals, its output will three-state following the next clock rise. The data written during the Write operation is controlled by BWS[1:0] signals. The CY7C1352B provides byte write capability that is described in the write cycle description table. Asserting the Write Enable input (WE) with the selected Byte Write Select (BWS[1:0]) input will selectively write to only the desired bytes. Bytes not selected during a byte write operation will remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. Byte write capability has been included in order to greatly simplify Read/Modify/Write sequences, which can be reduced to simple byte write operations. Because the CY7C1352B is a common I/O device, data should not be driven into the device while the outputs are active. The Output Enable (OE) can be deasserted HIGH before presenting data to the DQ[15:0] and DP[1:0] inputs. Doing so will threestate the output drivers. As a safety precaution, DQ [15:0] and DP [1:0] are automatically three-stated during the data portion of a write cycle, regardless of the state of OE. 4 PRELIMINARY CY7C1352B When ADV/LD is driven HIGH on the subsequent clock rise, the chip enables (CE1, CE2, and CE3) and WE inputs are ignored and the burst counter is incremented. The correct BWS[1:0] inputs must be driven in each cycle of the burst write in order to write the correct bytes of data. Burst Write Accesses The CY7C1352B has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four Write operations without reasserting the address inputs. ADV/LD must be driven LOW in order to load the initial address, as described in the Single Write Access section above. Cycle Description Truth Table[1, 2, 3, 4, 5, 6] Address used Operation CE CEN ADV/ LD/ WE BWSx Deselected External 1 0 L X X L-H I/Os three-state following next recognized clock. Suspend - X 1 X X X L-H Clock ignored, all operations suspended. Begin Read External 0 0 0 1 X L-H Address latched. Begin Write External 0 0 0 0 Valid L-H Address latched, data presented two valid clocks later. Burst READ Operation Internal X 0 1 X X L-H Burst Read operation. Previous access was a Read operation. Addresses incremented internally in conjunction with the state of MODE. Burst WRITE Operation Internal X 0 1 X Valid L-H Burst Write operation. Previous access was a Write operation. Addresses incremented internally in conjunction with the state of MODE. Bytes written are determined by BWS[1:0]. Interleaved Burst Sequence First Address Second Address Third Address CLK Comments Linear Burst Sequence Fourth Address First Address Second Address Third Address Fourth Address Ax+1, Ax Ax+1, Ax Ax+1, Ax Ax+1, Ax Ax+1, Ax Ax+1, Ax Ax+1, Ax Ax+1, Ax 00 01 10 11 00 01 10 11 01 00 11 10 01 10 11 00 10 11 00 01 10 11 00 01 11 10 01 00 11 00 01 10 Write Cycle Descriptions[1, 2] WE BWS 1 BWS0 Read Function 1 X X Write − No bytes written 0 1 1 Write Byte 0 − (DQ[7:0] and DP0) 0 1 0 Write Byte 1 − (DQ[15:8] and DP 1) 0 0 1 Write All Bytes 0 0 0 Notes: 1. X=”Don't Care”, 1=Logic HIGH, 0=Logic LOW, CE stands for ALL Chip Enables active. BWSx = 0 signifies at least one Byte Write Select is active, BWSx = Valid signifies that the desired byte write selects are asserted, see Write Cycle Description table for details. 2. Write is defined by WE and BWS[1:0]. See Write Cycle Description table for details. 3. The DQ and DP pins are controlled by the current cycle and the OE signal. 4. CEN=1 inserts wait states. 5. Device will power-up deselected and the I/Os in a three-state condition, regardless of OE. 6. OE assumed LOW. 5 PRELIMINARY CY7C1352B Current into Outputs (LOW)......................................... 20 mA Maximum Ratings Static Discharge Voltage .......................................... >2001V (per MIL-STD-883, Method 3015) (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ..................................... −65°C to +150°C Latch-Up Current .................................................... >200 mA Ambient Temperature with Power Applied .................................................. −55°C to +125°C Operating Range Supply Voltage on VDD Relative to GND .........−0.5V to +4.6V Range DC Voltage Applied to Outputs in High Z State[7] .....................................−0.5V to VDDQ + 0.5V Com’l Ambient Temperature[8] VDD/VDDQ 0°C to +70°C 3.3V ± 5% DC Input Voltage[7] ..................................−0.5V to VDDQ + 0.5V Electrical Characteristics Over the Operating Range Parameter Description Test Conditions VDD Power Supply Voltage VDDQ I/O Supply Voltage VOH Output HIGH Voltage VOL Output LOW Voltage VIH Input HIGH Voltage VDD = Min., IOH = –4.0 mA [9] VDD = Min., IOL = 8.0 mA[9] Min. Max. Unit 3.135 3.465 V 3.135 3.465 V 2.4 V 0.4 V 2.0 VDD + 0.3V V −0.3 0.8 V −5 5 µA Input Current of MODE −30 30 µA IOZ Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled −5 5 µA ICC VDD Operating Supply 5.0-ns cycle, 166 MHz 400 mA 6.6-ns cycle, 150 MHz 375 mA 7.0-ns cycle, 143 MHz 350 mA 7.5-ns cycle, 133 MHz 300 mA 10-ns cycle, 100 MHz 250 mA 12.5-ns cycle, 80 MHz 200 mA 5.0-ns cycle, 166 MHz 90 mA 6.6-ns cycle, 150 MHz 80 mA 7.0-ns cycle, 143 MHz 70 mA 7.5-ns cycle, 133 MHz 60 mA 10-ns cycle, 100 MHz 50 mA 12.5-ns cycle, 80 MHz 40 mA [7] VIL Input LOW Voltage IX Input Load Current ISB1 Automatic CE Power-Down Current—TTL Inputs GND ≤ VI ≤ VDDQ VDD = Max., IOUT = 0 mA, f = fMAX = 1/tCYC Max. VDD, Device Deselected, VIN ≥ VIH or VIN ≤ VIL f = fMAX = 1/tCYC ISB2 Automatic CE PowerDown Current—CMOS Inputs Max. VDD, Device Deselected, VIN All speed grades ≤ 0.3V or VIN > V DDQ – 0.3V, f=0 5 mA ISB3 Automatic CE PowerDown Current—CMOS Inputs Max. VDD, Device Deselected, or VIN ≤ 0.3V or VIN > VDDQ – 0.3V f = fMAX = 1/tCYC 5.0-ns cycle, 166 MHz 80 mA 6.6-ns cycle, 150 MHz 70 mA 7.0-ns cycle, 143 MHz 60 mA 7.5-ns cycle, 133 MHz 50 mA 10-ns cycle, 100 MHz 40 mA 12.5-ns cycle, 80 MHz 30 mA Shaded areas contain advance information. Notes: 7. Minimum voltage equals –2.0V for pulse duration less than 20 ns. 8. TA is the case temperature. 9. The load used for VOH and VCL testing is shown in part (b) of A/C Test Loads and Waveforms. 6 PRELIMINARY CY7C1352B Capacitance[10] Parameter Description Test Conditions CIN Input Capacitance TA = 25°C, f = 1 MHz, VDD = 3.3V. VDDQ = 3.3V CCLK Clock Input Capacitance CI/O Input/Output Capacitance Max. Unit 4 pF 4 pF 4 pF AC Test Loads and Waveforms R=317Ω 3.3V OUTPUT [11] OUTPUT Z0 =50Ω RL =50Ω ALL INPUT PULSES 3.0V 5 pF R=351Ω GND VL = 1.5V (a) INCLUDING JIG AND SCOPE (b) 1352B-2 Thermal Resistance Description Thermal Resistance (Junction to Ambient) Test Conditions Symbol TQFP Typ. Units Notes Still Air, soldered on a 4.25 x 1.125 inch, 4layer printed circuit board ΘJA 28 °C/W 10 ΘJC 4 °C/W 10 Thermal Resistance (Junction to Case) Note: 10. Tested initially and after any design or process change that may affect these parameters. 11. AC test conditions assume signal transition time of 2 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading shown in (a) of AC Test Loads and Waveforms. 7 PRELIMINARY CY7C1352B Switching Characteristics Over the Operating Range[11, 12, 13] -166 Parameter Description -150 -143 -133 -100 -80 Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit tCYC Clock Cycle Time 5.0 6.6 7.0 7.5 10 12.5 ns tCH Clock HIGH 1.4 2.5 2.8 3.0 4.0 4.0 ns tCL Clock LOW 1.4 2.5 2.8 3.0 4.0 4.0 ns tAS Address Set-Up Before CLK Rise 1.5 1.5 2.0 2.0 2.2 2.5 ns tAH Address Hold After CLK Rise 0.5 0.5 0.5 0.5 0.5 1.0 ns tCO Data Output Valid After CLK Rise tDOH Data Output Hold After CLK Rise 1.5 1.5 1.5 1.5 1.5 1.5 ns tCENS CEN Set-Up Before CLK Rise 1.5 1.5 2.0 2.0 2.2 2.5 ns tCENH CEN Hold After CLK Rise 0.5 0.5 0.5 0.5 0.5 1.0 ns tWES GW, BWS[1:0] Set-Up Before CLK Rise 1.5 1.5 2.0 2.0 2.2 2.5 ns tWEH GW, BWS[1:0] Hold After CLK Rise 0.5 0.5 0.5 0.5 0.5 1.0 ns tALS ADV/LD Set-Up Before CLK Rise 1.5 1.5 2.0 2.0 2.2 2.5 ns tALH ADV/LD Hold after CLK Rise 0.5 0.5 0.5 0.5 0.5 1.0 ns tDS Data Input Set-Up Before CLK Rise 1.5 1.5 1.7 1.7 2.0 2.5 ns tDH Data Input Hold After CLK Rise 0.5 0.5 0.5 0.5 0.5 1.0 ns tCES Chip Enable Set-Up Before CLK Rise 1.5 1.5 2.0 2.0 2.2 2.5 ns tCEH Chip Enable Hold After CLK Rise 0.5 0.5 0.5 0.5 0.5 1.0 ns tCHZ Clock to High-Z[10, 12, 13, 14] 1.5 tCLZ [10, 12, 13, 14] 1.5 Clock to Low-Z 3.5 [10, tEOHZ OE HIGH to Output High-Z tEOLZ OE LOW to Output Low-Z[10, tEOV OE LOW to Output Valid[12] 1.5 3.2 1.5 0 4.0 1.5 3.5 1.5 3.0 12, 13, 14] 12, 13, 14] 3.2 3.8 3.0 0 3.5 1.5 3.5 1.5 4.0 0 3.2 4.2 1.5 3.5 1.5 4.2 0 4.0 5.0 1.5 5.0 1.5 5.0 0 4.2 7.0 ns ns 7.0 0 5.0 ns ns ns 7.0 ns Shaded areas contain advance information. Notes: 12. tCHZ, tCLZ, tOEV, tEOLZ , and tEOHZ are specified with A/C test conditions shown in part (a) of AC Test Loads and waveforms. Transition is measured ± 200 mV from steady-state voltage. 13. At any given voltage and temperature, tEOHZ is less than t EOLZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z prior to Low-Z under the same system conditions. 14. This parameter is sampled and not 100% tested. 8 PRELIMINARY CY7C1352B Switching Waveforms DESELECT DESELECT SUSPEND READ READ WRITE READ DESELECT READ READ WRITE Read/Write/Deselect Sequence CLK tCH tCL tCENS tCYC tCENH CEN tAS tAH ADDRESS WE & BWS[1:0] CEN HIGH blocks all synchronous inputs WA2 RA1 RA3 WA5 RA4 RA6 RA7 tWS tWH tCES tCEH CE tCLZ tDOH DataIn/Out Q11a Out Device originally deselected tDS tDH tCHZ tCHZ tDOH D2 In Q4 Out Q31a Out D5 In Q6 Out Q7 Out tCO The combination of WE & BWS[1:0] defines a write cycle (see Write Cycle Description table). CE is the combination of CE1, CE2, and CE3. All chip enables need to be active in order to select the device. Any chip enable can deselect the device. RAx stands for Read Address X, WAx stands for Write Address X, Dx stands for Data-in for location X, Qx stands for Data-out for location X. ADV/LD held LOW. OE held LOW. = UNDEFINED = DON’T CARE 9 PRELIMINARY CY7C1352B Burst Read Burst Read Begin Read Burst Write Burst Write Burst Write Begin Write Burst Read Burst Read Burst Read Burst Sequences Begin Read Switching Waveforms (continued) CLK tALH tALS tCH tCL tCYC ADV/LD tAS tAH ADDRESS RA1 WA2 RA3 WE tWS tWH tWS tWH BWS[1:0] tCES tCEH CE tCLZ DataIn/Out tCHZ tDOH Q11a Out Device originally deselected tCO Q1+1 Out Q1+2 Out Q1+3 Out tCO tCLZ tDH D2 In D2+1 In D2+2 In D2+3 In Q3 Out tDS The combination of WE & BWS [1:0] defines a write cycle (see Write Cycle Description table). CE is the combination of CE1, CE2, and CE3. All chip enables need to be active in order to select the device. Any chip enable can deselect the device. RAx stands for Read Address X, WA stands for Write Address X, Dx stands for Data-in for location X, Qx stands for Data-out for location X. CEN held LOW. During burst writes, byte writes can be conducted by asserting the appropriate BWS[1:0] input signals. Burst order determined by the state of the MODE input. CEN held LOW. OE held LOW. = UNDEFINED = DON’T CARE 10 PRELIMINARY CY7C1352B Switching Waveforms (continued) OE Timing OE tEOV tEOHZ Three-state I/O’s tEOLZ Ordering Information Speed (MHz) Ordering Code Package Name Package Type Operating Range 166 CY7C1352B-166AC A101 100-Lead (14 x 20 x 1.4 mm) Thin Quad Flat Pack Commercial 150 CY7C1352B-150AC A101 100-Lead (14 x 20 x 1.4 mm) Thin Quad Flat Pack Commercial 143 CY7C1352B-143AC A101 100-Lead (14 x 20 x 1.4 mm) Thin Quad Flat Pack Commercial 133 CY7C1352B-133AC A101 100-Lead (14 x 20 x 1.4 mm) Thin Quad Flat Pack Commercial 100 CY7C1352B-100AC A101 100-Lead (14 x 20 x 1.4 mm) Thin Quad Flat Pack Commercial 80 CY7C1352B-80AC A101 100-Lead (14 x 20 x 1.4 mm) Thin Quad Flat Pack Commercial Shaded areas contain advance information. Document #: 38−00934-A 11 PRELIMINARY CY7C1352B Package Diagram 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101 51-85050-A © Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.