CY7C1355A-133AC

CY7C1357A CY7C1355A 256K x 36/512K x 18 Synchronous Flow-Thru SRAM with NoBL™ Architecture Features • Zero Bus Latency, no dead cycles between write and read cycles • Fast access times: 2.5 ns, 3.0 ns, and 3.5 ns • Fast clock speed: 133, 117, and 100 MHz • Fast OE access time: 6.5, 7.0, and 7.5ns • Internally synchronized registered outputs eliminate the need to control OE • • • • • • • • • • • 3.3V –5% and +5% power supply 3.3V or 2.5V I/O supply Single WEN (READ/WRITE) control pin Positive clock-edge triggered, address, data, and control signal registers for fully pipelined applications Interleaved or linear four-word burst capability Individual byte write (BWa–BWd) control (may be tied LOW) CEN pin to enable clock and suspend operations Three chip enables for simple depth expansion Automatic Power-down feature available using ZZ mode or CE deselect. JTAG boundary scan (except CY7C1357A) Low-profile 119-bump, 14-mm × 22-mm BGA (Ball Grid Array) for CY7C1355A, and 100-pin TQFP packages for both devices All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, depth-expansion Chip Enables (CE, CE2, and CE3), Cycle Start Input (ADV/LD), Clock Enable (CEN), Byte Write Enables (BWa, BWb, BWc, and BWd), and read-write control (WEN). BWc and BWd apply to CY7C1355A only. Address and control signals are applied to the SRAM during one clock cycle, and one cycle later, its associated data occurs, either read or write. A Clock Enable (CEN) pin allows operation of the CY7C1355A/CY7C1357A to be suspended as long as necessary. All synchronous inputs are ignored when (CEN) is HIGH and the internal device registers will hold their previous values. There are three Chip Enable pins (CE, CE2, CE3) that allow the user to deselect the device when desired. If any one of these three are not active when ADV/LD is LOW, no new memory operation can be initiated and any burst cycle in progress is stopped. However, any pending data transfers (read or write) will be completed. The data bus will be in high-impedance state one cycle after chip is deselected or a write cycle is initiated. The CY7C1355A and CY7C1357A have an on-chip 2-bit burst counter. In the burst mode, the CY7C1355A and CY7C1357A provide four cycles of data for a single address presented to the SRAM. The order of the burst sequence is defined by the MODE input pin. The MODE pin selects between linear and interleaved burst sequence. The ADV/LD signal is used to load a new external address (ADV/LD = LOW) or increment the internal burst counter (ADV/LD = HIGH) Output Enable (OE), Sleep Enable (ZZ) and burst sequence select (MODE) are the asynchronous signals. OE can be used to disable the outputs at any given time. ZZ may be tied to LOW if it is not used. Four pins are used to implement JTAG test capabilities. The JTAG circuitry is used to serially shift data to and from the device. JTAG inputs use LVTTL/LVCMOS levels to shift data during this testing mode of operation. 7C1355A-117 7C1357A-117 7 385 30 7C1355A-100 7C1357A-100 7.5 350 30 Functional Description The CY7C1355A and CY7C1357A SRAMs are designed to eliminate dead cycles when transitions from READ to WRITE or vice versa. These SRAMs are optimized for 100 percent bus utilization and achieves Zero Bus Latency (ZBL). They integrate 262,144 × 36 and 524,288 × 18 SRAM cells, respectively, with advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operation. These employ high-speed, low power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists of Six transistors. Selection Guide 7C1355A-133 7C1357A-133 Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 6.5 410 30 Unit ns mA mA Cypress Semiconductor Corporation Document #: 38-05265 Rev. *A • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised August 23, 2002 CY7C1357A CY7C1355A Functional Block Diagram 256Kx36[1] ZZ MODE CEN ADV/LD WE WEN BWa, BWb BWc, BWd CE, CE1, CE2,CE3 A0, A1, SA A A0, A1, Control Control Logic Mux CLK OE Output Buffers DQa-DQd Functional Block Diagram 512Kx18[1] ZZ MODE CEN ADV/LD R/W WEN BWa, BWb CE, CE1, CE2,CE3 A0, A1,SA A A0, A1, 512K x 9 x 2 SRAM Array Address Control Control Logic Mux CLK OE Output Buffers DQa, DQb Note: 1. The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions and timing diagrams for detailed information. Document #: 38-05265 Rev. *A DO Sel DI Input Registers DO Sel DI Input Registers 256K x 9 x 4 SRAM Array Address Page 2 of 28 CY7C1357A CY7C1355A Pin Configurations 100-pin TQFP Packages 256Kx36—CY7C1355A Top View A A CE1 CE2 BWd BWc BWb BWa CE3 VCC VSS CLK WEN /WE CEN OE ADV/LD NC A A A 512Kx18—CY7C1357A Top View A A CE1 CE2 NC NC BWb BWa CE3 VCC VSS CLK WEN /WE CEN OE ADV/LD NC A A A 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 DQc DQc DQc VCCQ VSS DQc DQc DQc DQc VSS VCCQ DQc DQc VSS VCC VCC VSS DQd DQd VCCQ VSS DQd DQd DQd DQd VSS VCCQ DQd DQd DQd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 100-pin TQFP 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 DQb DQb DQb VCCQ VSS DQb DQb DQb DQb VSS VCCQ DQb DQb VSS VSS VCC ZZ DQa DQa VCCQ VSS DQa DQa DQa DQa VSS VCCQ DQa DQa DQa NC NC NC VCCQ VSS NC NC DQb DQb VSS VCCQ DQb DQb VSS VCC VCC VSS DQb DQb VCCQ VSS DQb DQb DQb NC VSS VCCQ NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 100-pin TQFP 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A NC NC VCCQ VSS NC DQa DQa DQa VSS VCCQ DQa DQa VSS VSS VCC ZZ DQa DQa VCCQ VSS DQa DQa NC NC VSS VCCQ NC NC NC 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Document #: 38-05265 Rev. *A MODE SA SA SA SA SA1 SA0 TMS TDI VSS VCC TDO TCK A A A A A A A MODE A A A A A1 A0 TMS NC TDI NC VSS VCC TDO NC TCK NC A A A A A A A Page 3 of 28 CY7C1357A CY7C1355A Pin Configurations (continued) 119-ball Bump BGA 256Kx36—CY7C1355A Top View 1 A B C D E F G H J K L M N P R T U VCCQ NC NC DQc DQc VCCQ DQc DQc VCCQ DQd DQd VCCQ DQd DQd NC NC VCCQ 2 A CE2 A DQc DQc DQc DQc DQc VCC DQd DQd DQd DQd DQd A NC TMS 3 A A A VSS VSS VSS BWc VSS NC VSS BWd VSS VSS VSS MODE A TDI 4 NC ADV/LD VCC NC CE1 OE A WEN VCC CLK NC CEN A1 A0 VCC A TCK 5 A A A VSS VSS VSS BWb VSS NC VSS BWa VSS VSS VSS VSS A TDO 6 A CE3 A DQb DQb DQb DQb DQb VCC DQa DQa DQa DQa DQa A NC NC 7 VCCQ NC NC DQb DQb VCCQ DQb DQb VCCQ DQa DQa VCCQ DQa DQa NC ZZ VCCQ Document #: 38-05265 Rev. *A Page 4 of 28 CY7C1357A CY7C1355A Pin Descriptions (CY7C1355A) 256K × 36 TQFP Pins 37, 36, 32, 33, 34, 35, 44, 45, 46, 47, 48, 49, 50, 81, 82, 83, 99, 100 93, 94, 95, 96 256K × 36 PBGA Pins 4P 4N 2A, 3A, 5A, 6A, 3B, 5B, 2C, 3C, 5C, 6C, 4G, 2R, 6R, 3T, 4T, 5T 5L 5G 3G 3L Name A0, A1, A Type Description InputSynchronous Address Inputs: The address register is triggered by Synchronous a combination of the rising edge of CLK, ADV/LD LOW, CEN LOW and true chip enables. A0 and A1 are the two least significant bits of the address field and set the internal burst counter if burst cycle is initiated. InputSynchronous Byte Write Enables: Each nine-bit byte has its own Synchronous active LOW byte write enable. On load write cycles (when WEN and ADV/LD are sampled LOW), the appropriate byte write signal (BWx) must be valid. The byte write signal must also be valid on each cycle of a burst write. Byte write signals are ignored when WEN is sampled HIGH. The appropriate byte(s) of data are written into the device one cycle later. BWa controls DQa pins; BWb controls DQb pins; BWc controls DQc pins; BWd controls DQd pins. BWx can all be tied LOW if always doing a write to the entire 36-bit word. InputSynchronous Clock Enable Input: When CEN is sampled HIGH, all Synchronous other synchronous inputs, including clock are ignored and outputs remain unchanged. The effect of CEN sampled HIGH on the device outputs is as if the LOW-to-HIGH clock transition did not occur. For normal operation, CEN must be sampled LOW at rising edge of clock. InputRead Write: WEN signal is a synchronous input that identifies Synchronous whether the current loaded cycle and the subsequent burst cycles initiated by ADV/LD is a Read or Write operation. The data bus activity for the current cycle takes place one clock cycle later. InputClock Clock: This is the clock input to CY7C1355A. Except for OE, ZZ, and MODE, all timing references for the device are made with respect to the rising edge of CLK. BWa, BWb, BWc, BWd 87 4M CEN 88 4H WEN 89 4K CLK 98, 92 4E, 6B CE1, CE3 InputSynchronous Active LOW Chip Enable: CE1 and CE3 are used with Synchronous CE2 to enable the CY7C1355A. CE1 or CE3 sampled HIGH or CE2 sampled LOW, along with ADV/LD LOW at the rising edge of clock, initiates a deselect cycle. The data bus will be High-Z one clock cycle after chip deselect is initiated. InputSynchronous Active High Chip Enable: CE2 is used with CE1 and Synchronous CE3 to enable the chip. CE2 has inverted polarity but otherwise is identical to CE1 and CE3. Input Asynchronous Output Enable: OE must be LOW to read data. Asynchronous When OE is HIGH, the I/O pins are in high-impedance state. OE does not need to be actively controlled for read and write cycles. In normal operation, OE can be tied LOW. InputAdvance/Load: ADV/LD is a synchronous input that is used to load Synchronous the internal registers with new address and control signals when it is sampled LOW at the rising edge of clock with the chip is selected. When ADV/LD is sampled HIGH, then the internal burst counter is advanced for any burst that was in progress. The external addresses and WEN are ignored when ADV/LD is sampled HIGH. InputStatic Burst Mode: When MODE is HIGH or NC, the interleaved burst sequence is selected. When MODE is LOW, the linear burst sequence is selected. MODE is a static DC input. 97 2B CE2 86 4F OE 85 4B ADV/ LD 31 3R MODE 64 7T ZZ InputSleep Enable: This active HIGH input puts the device in low power Asynchronous consumption standby mode. For normal operation, this input has to be either LOW or NC. Document #: 38-05265 Rev. *A Page 5 of 28 CY7C1357A CY7C1355A Pin Descriptions (CY7C1355A) (continued) 256K × 36 TQFP Pins 51, 52, 53, 56–59, 62, 63 68, 69, 72–75, 78, 79, 80 1, 2, 3, 6–9, 12, 13 18, 19, 22–25, 28, 29, 30 256K × 36 PBGA Pins (a) 6P, 7P, 7N, 6N, 6M, 6L, 7L, 6K, 7K, (b) 7H, 6H, 7G, 6G, 6F, 6E, 7E, 7D, 6D, (c) 2D, 1D, 1E, 2E, 2F, 1G, 2G, 1H, 2H, (d) 1K, 2K, 1L, 2L, 2M, 1N, 2N, 1P, 2P 2U 3U 4U 5U Name DQa DQb DQc DQd Type Description Input/ Data Inputs/Outputs: Both the data input path and data output path Output are registered and triggered by the rising edge of CLK. Byte “a” is Synchronous DQa pins; Byte “b” is DQb pins; Byte “c” is DQc pins; Byte “d” is DQd pins. 38 39 43 42 TMS TDI TCK TDO VCC VSS Input IEEE 1149.1 test inputs: LVTTL-level inputs. If Serial Boundary Scan (JTAG) is not used, these pins can be floating (i.e., No Connect) or be connected to VCC. IEEE 1149.1 test output: LVTTL-level output. If Serial Boundary Scan (JTAG) is not used, these pins can be floating (i.e., No Connect). Power Supply: +3.3V –5% and +5%. Ground: GND. Output Power Supply Ground 15, 16, 41, 65, 4C, 2J, 4J, 6J, 91 4R 5, 10, 14, 17, 21, 26, 40, 55, 60, 66, 67, 71, 76, 90 3D, 5D, 3E, 5E, 3F, 5F, 3H, 5H, 3K, 5K, 3M, 5M, 3N, 5N, 3P, 5P, 5R 4, 11, 20, 27, 54, 1A, 7A, 1F, 7F, 61, 70, 77 1J, 7J, 1M, 7M, 1U, 7U 84 4A, 1B, 7B, 1C, 7C, 4D, 3J, 5J, 4L, 1R, 7R, 1T, 2T, 6T, 6U VCCQ I/O Power Supply – Power Supply for the I/O circuitry. NC No Connect: These signals are not internally connected. It can be left floating or be connected to VCC or to GND. Pin Descriptions (CY7C1357A) 512K × 18 TQFP Pins 37, 36, 32, 33, 34, 35, 44, 45, 46, 47, 48, 49, 50, 80, 81, 82, 83, 99, 100 93, 94, Name A0, A1, A Type InputSynchronous Description Synchronous Address Inputs: The address register is triggered by a combination of the rising edge of CLK, ADV/LD LOW, CEN LOW and true chip enables. A0 and A1 are the two least significant bits of the address field and set the internal burst counter if burst cycle is initiated. BWa, BWb InputSynchronous Synchronous Byte Write Enables: Each nine-bit byte has its own active low byte write enable. On load write cycles (when WEN and ADV/LD are sampled LOW), the appropriate byte write signal (BWx) must be valid. The byte write signal must also be valid on each cycle of a burst write. Byte write signals are ignored when WEN is sampled HIGH. The appropriate byte(s) of data are written into the device one cycle later. BWa controls DQa pins; BWb controls DQb pins. BWx can all be tied LOW if always doing write to the entire 18-bit word. Synchronous Clock Enable Input: When CEN is sampled HIGH, all other synchronous inputs, including clock are ignored and outputs remain unchanged. The effect of CEN sampled HIGH on the device outputs is as if the LOW-to-HIGH clock transition did not occur. For normal operation, CEN must be sampled LOW at rising edge of clock. Page 6 of 28 87 CEN InputSynchronous Document #: 38-05265 Rev. *A CY7C1357A CY7C1355A Pin Descriptions (CY7C1357A) (continued) 512K × 18 TQFP Pins 88 Name WEN Type InputSynchronous Description Read Write: WEN signal is a synchronous input that identifies whether the current loaded cycle and the subsequent burst cycles initiated by ADV/LD is a Read or Write operation. The data bus activity for the current cycle takes place one clock cycle later. Clock: This is the clock input to CY7C1357A. Except for OE, ZZ and MODE, all timing references for the device are made with respect to the rising edge of CLK. Synchronous Active Low Chip Enable: CE1 and CE3 are used with CE2 to enable the CY7C1357A. CE1 or CE3 sampled HIGH or CE2 sampled LOW, along with ADV/LD LOW at the rising edge of clock, initiates a deselect cycle. The data bus will be High-Z one clock cycle after chip deselect is initiated. Synchronous Active High Chip Enable: CE2 is used with CE1 and CE3 to enable the chip. CE2 has inverted polarity but otherwise is identical to CE1 and CE3. Asynchronous Output Enable: OE must be LOW to read data. When OE is HIGH, the I/O pins are in high-impedance state. OE does not need to be actively controlled for read and write cycles. In normal operation, OE can be tied LOW. Advance/Load: ADV/LD is a synchronous input that is used to load the internal registers with new address and control signals when it is sampled LOW at the rising edge of clock with the chip is selected. When ADV/LD is sampled HIGH, then the internal burst counter is advanced for any burst that was in progress. The external addresses and WEN are ignored when ADV/LD is sampled HIGH. Burst Mode: When MODE is HIGH or NC, the interleaved burst sequence is selected. When MODE is LOW, the linear burst sequence is selected. MODE is a static DC input. Sleep Enable: This active HIGH input puts the device in low power consumption standby mode. For normal operation, this input has to be either LOW or NC. Data Inputs/Outputs: Both the data input path and data output path are registered and triggered by the rising edge of CLK. Byte “a” is DQa pins; Byte “b” is DQb pins. Power Supply: +3.3V –5% and +5%. Ground: GND. 89 CLK InputClock InputSynchronous 98, 92 CE1, CE3 97 CE2 InputSynchronous InputAsynchronous 86 OE 85 ADV/ LD InputSynchronous 31 MODE Input 64 ZZ Input Asynchronous Input/ OutputSynchronous Supply Ground 58, 59, 62, 63, 68, 69, 72, 73, 74 8, 9, 12, 13, 18, 19, 22, 23, 24 15, 16, 41, 65, 91 5, 10, 14, 17, 21, 26, 40, 55, 60, 66, 67, 71, 76, 90 4, 11, 20, 27, 54, 61, 70, 77 1-3, 6, 7, 25, 28-30, 51-53, 56, 57, 75, 78, 79, 84, 95, 96, 38,39,42,43 DQa DQb VCC VSS VCCQ NC I/O Power Supply Power supply for the I/O circuitry. – No Connect: These signals are not internally connected. It can be left floating or be connected to VCC or to GND. Document #: 38-05265 Rev. *A Page 7 of 28 CY7C1357A CY7C1355A Partial Truth Table for Read/Write[2] Function Read No Write Write Byte a (DQa) Write Byte b (DQb) Write Byte d (DQd} Write all bytes [3] [3] WEN H L L L L L L BWa X H L H H H L BWb X H H L H H L BWc[4] X H H H L H L BWd[4] X H H H H L L Write Byte c (DQc)[3] [3] Interleaved Burst Address Table (MODE = VCC or NC) First Address (external) A...A00 A...A01 A...A10 A...A11 Second Address (internal) A...A01 A...A00 A...A11 A...A10 Third Address (internal) A...A10 A...A11 A...A00 A...A01 Fourth Address (internal)[5] A...A11 A...A10 A...A01 A...A00 Sleep Mode The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the “sleep” mode. CEs must remain inactive for the duration of tZZREC after the ZZ input returns LOW. CEN needs to active before going into the ZZ mode and before you want to come back out of the ZZ mode. Linear Burst Address Table (MODE = VSS) First Address (external) A...A00 A...A01 A...A10 Second Address (internal) A...A01 A...A10 A...A11 Third Address (internal) A...A10 A...A11 A...A00 Fourth Address (internal)[5] A...A11 A...A00 A...A01 A...A11 A...A00 A...A01 A...A10 Notes: 2. L means logic LOW. H means logic HIGH. X means “Don’t Care.” 3. Multiple bytes may be selected during the same cycle. 4. BWc and BWd apply to 256K × 36 device only. 5. Upon completion of the Burst sequence, the counter wraps around to its initial state and continues counting. Document #: 38-05265 Rev. *A Page 8 of 28 CY7C1357A CY7C1355A ZZ Mode Electrical Characteristics Parameter IDDZZ tZZS tZZREC Description Sleep mode standby current Device operation to ZZ ZZ recovery time Test Conditions ZZ > VDD – 0.2V ZZ > VDD – 0.2V ZZ < 0.2V 2tCYC Min. Max. 10 2tCYC Unit mA ns ns Truth Table[6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17] Operation Deselect Cycle Continue Deselect/NOP[18] Read Cycle (Begin Burst) Read Cycle (Continue Burst)[18] Dummy Read (Begin Burst)[19] Dummy Read (Continue Burst)[18, 19] Write Cycle (Begin Burst) Write Cycle (Continue Burst)[18] Abort Write (Begin Burst)[19] Abort Write (Continue Burst)[18, 19] Ignore Clock Edge/NOP[20] Previous Cycle X Deselect X Read X Read X Write X Write X Address Used X X External Next External Next External Next External Next X WEN ADV/LD X X H X H X L X L X X L H L H L H L H L H H CE H X L X L X L X L X X CEN L L L L L L L L L L H BWx X X X X X X L L H H X OE X X X X H H X X X X X DQ (1 cycle later) High-Z High-Z Q Q High-Z High-Z D D High-Z High-Z - IEEE 1149.1 Serial Boundary Scan (JTAG) Overview This device (except for CY7C1357A) incorporates a serial boundary scan access port (TAP). This port is designed to operate in a manner consistent with IEEE Standard 1149.1-1990 (commonly referred to as JTAG), but does not implement all of the functions required for IEEE 1149.1 compliance. Certain functions have been modified or eliminated because their implementation places extra delays in the critical speed path of the device. Nevertheless, the device supports the standard TAP controller architecture (the TAP controller is the state machine that controls the TAPs operation) and can be expected to function in a manner that does not conflict with the operation of devices with IEEE Standard 1149.1-compliant TAPs. The TAP operates using LVTTL/ LVCMOS logic level signaling. Disabling the JTAG Feature It is possible to use this device without using the JTAG feature. To disable the TAP controller without interfering with normal operation of the device, TCK should be tied LOW (VSS) to prevent clocking the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be pulled up to VCC through a resistor. TDO should be left unconnected. Upon power-up the device will come up in a reset state which will not interfere with the operation of the device. Test Access Port TCK—Test Clock (INPUT) Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK. Notes: 6. This assumes that CEN, CE, CE2, and CE2 are all True. 7. All addresses, control and data-in are only required to meet set-up and hold time with respect to the rising edge of clock. Data out is valid after a clock-to-data delay from the rising edge of clock. 8. DQc and DQd apply to 256Kx36 device only. 9. L means logic LOW. H means logic HIGH. X means “Don’t Care.” High-Z means High Impedance. BWx = L means [BWa*BWb*BWc*BWd] equals LOW. BWx = H means [BWa*BWb*BWc*BWd] equals HIGH. BWc and BWd apply to 256K × 36 device only. 10. CE = H means CE and CE2 are LOW along with CE2 being HIGH. CE = L means CE or CE2 is HIGH or CE2 is LOW. CE = X means CE, CE2, and CE2 are “Don’t Care.” 11. BWa enables WRITE to byte “a” (DQa pins). BWb enables WRITE to byte “b” (DQb pins). BWc enables WRITE to byte “c” (DQc pins). BWd enables WRITE to byte “d” (DQd pins). DQc, DQd, BWc, and BWd apply to 256K × 36 device only. 12. The device is not in Sleep Mode, i.e., the ZZ pin is LOW. 13. During Sleep Mode, the ZZ pin is HIGH and all the address pins and control pins are “Don’t Care.” The Sleep Mode can only be entered one cycle after the WRITE cycle, otherwise the WRITE cycle may not be completed. 14. All inputs, except OE, ZZ, and MODE pins, must meet set-up time and hold time specification against the clock (CLK) LOW-to-HIGH transition edge. 15. OE may be tied to LOW for all the operation. This device automatically turns off the output driver during WRITE cycle. 16. Device outputs are ensured to be in High-Z during device power-up. 17. This device contains a two-bit burst counter. The address counter is incremented for all Continue Burst cycles. Address wraps to the initial address every fourth burst cycle. 18. Continue Burst cycles, whether READ or WRITE, use the same control signals. The type of cycle performed, READ or WRITE, depends upon the WEN control signal at the BEGIN BURST cycle. A Continue Deselect cycle can only be entered if a Deselect cycle is executed first. 19. Dummy Read and Abort WRITE cycles can be entered to set up subsequent READ or WRITE cycles or to increment the burst counter. 20. When an Ignore Clock Edge cycle enters, the output data (Q) will remain the same if the previous cycle is READ cycle or remain High-Z if the previous cycle is WRITE or Deselect cycle. Document #: 38-05265 Rev. *A Page 9 of 28 CY7C1357A CY7C1355A TMS—Test Mode Select (INPUT) The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP controller state machine. It is allowable to leave this pin unconnected if the TAP is not used. The pin is pulled up internally, resulting in a logic HIGH level. TDI—Test Data In (INPUT) The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP controller state machine and the instruction that is currently loaded in the TAP instruction register (refer toFigure 1). It is allowable to leave this pin unconnected if it is not used in an application. The pin is pulled up internally, resulting in a logic HIGH level. TDI is connected to the most significant bit (MSB) of any register. (See Figure 2.) TDO—Test Data Out (OUTPUT) The TDO output pin is used to serially clock data-out from the registers. The output that is active depending on the state of the TAP state machine (refer to Figure 1). Output changes in response to the falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO. TDO is connected to the least significant bit (LSB) of any register. (See Figure 2.) Performing a TAP Reset The TAP circuitry does not have a reset pin (TRST, which is optional in the IEEE 1149.1 specification). A RESET can be performed for the TAP controller by forcing TMS HIGH (VCC) for five rising edges of TCK and pre-loads the instruction register with the IDCODE command. This type of reset does not affect the operation of the system logic. The reset affects test logic only. At power-up, the TAP is reset internally to ensure that TDO is in a High-Z state. Bypass Register The bypass register is a single-bit register that can be placed between TDI and TDO. It allows serial test data to be passed through the device TAP to another device in the scan chain with minimum delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. Boundary Scan Register The Boundary scan register is connected to all the input and bidirectional I/O pins (not counting the TAP pins) on the device. This also includes a number of NC pins that are reserved for future needs. There are a total of 70 bits for x36 device and 51 bits for x18 device. The boundary scan register, under the control of the TAP controller, is loaded with the contents of the device I/O ring when the controller is in Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE-Z instructions can be used to capture the contents of the I/O ring. The Boundary Scan Order table describes the order in which the bits are connected. The first column defines the bit’s position in the boundary scan register. The MSB of the register is connected to TDI, and LSB is connected to TDO. The second column is the signal name and the third column is the bump number. The third column is the TQFP pin number and the fourth column is the BGA bump number. Identification (ID) Register The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in Capture-DR state with the IDCODE command loaded in the instruction register. The register is then placed between the TDI and TDO pins when the controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins. The code is loaded from a 32-bit on-chip ROM. It describes various attributes of the device as described in the Identification Register Definitions table. Test Access Port Registers Overview The various TAP registers are selected (one at a time) via the sequences of ones and zeros input to the TMS pin as the TCK is strobed. Each of the TAPs registers are serial shift registers that capture serial input data on the rising edge of TCK and push serial data out on subsequent falling edge of TCK. When a register is selected, it is connected between the TDI and TDO pins. Instruction Register The instruction register holds the instructions that are executed by the TAP controller when it is moved into the run test/idle or the various data register states. The instructions are three bits long. The register can be loaded when it is placed between the TDI and TDO pins. The parallel outputs of the instruction register are automatically preloaded with the IDCODE instruction upon power-up or whenever the controller is placed in the test-logic reset state. When the TAP controller is in the Capture-IR state, the two least significant bits of the serial instruction register are loaded with a binary “01” pattern to allow for fault isolation of the board-level serial test data path. TAP Controller Instruction Set Overview There are two classes of instructions defined in the IEEE Standard 1149.1-1990; the standard (public) instructions and device specific (private) instructions. Some public instructions are mandatory for IEEE 1149.1 compliance. Optional public instructions must be implemented in prescribed ways. Although the TAP controller in this device follows the IEEE 1149.1 conventions, it is not IEEE 1149.1 compliant because some of the mandatory instructions are not fully implemented. The TAP on this device may be used to monitor all input and I/O pads, but can not be used to load address, data, or control signals into the device or to preload the I/O buffers. In other words, the device will not perform IEEE 1149.1 EXTEST, INTEST, or the preload portion of the SAMPLE/PRELOAD command. When the TAP controller is placed in Capture-IR state, the two least significant bits of the instruction register are loaded with 01. When the controller is moved to the Shift-IR state the instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the TAP executes newly loaded instructions only when the Document #: 38-05265 Rev. *A Page 10 of 28 CY7C1357A CY7C1355A controller is moved to Update-IR state. The TAP instruction sets for this device are listed in the following tables. EXTEST EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with all 0s. EXTEST is not implemented in this device. The TAP controller does recognize an all-0 instruction. When an EXTEST instruction is loaded into the instruction register, the device responds as if a SAMPLE/PRELOAD instruction has been loaded. There is one difference between two instructions. Unlike SAMPLE/PRELOAD instruction, EXTEST places the device outputs in a High-Z state. IDCODE The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the ID register when the controller is in Capture-DR mode and places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction loaded in the instruction upon power-up and at any time the TAP controller is placed in the test-logic reset state. SAMPLE-Z If the High-Z instruction is loaded in the instruction register, all output pins are forced to a High-Z state and the boundary scan register is connected between TDI and TDO pins when the TAP controller is in a Shift-DR state. SAMPLE/PRELOAD SAMPLE/PRELOAD is an IEEE 1149.1 mandatory instruction. The PRELOAD portion of the command is not implemented in this device, so the device TAP controller is not fully IEEE 1149.1-compliant. When the SAMPLE/PRELOAD instruction is loaded in the instruction register and the TAP controller is in the Capture-DR state, a snap shot of the data in the device’s input and I/O buffers is loaded into the boundary scan register. Because the device system clock(s) are independent from the TAP Clock (TCK), it is possible for the TAP to attempt to capture the input and I/O ring contents while the buffers are in transition (i.e., in a metastable state). Although allowing the TAP to sample metastable inputs will not harm the device, repeatable results can not be expected. To guarantee that the boundary scan register will capture the correct value of a signal, the device input signals must be stabilized long enough to meet the TAP controller’s capture set up plus hold time (tCS plus tCH). The device clock input(s) need not be paused for any other TAP operation except capturing the input and I/O ring contents into the boundary scan register. Moving the controller to Shift-DR state then places the boundary scan register between the TDI and TDO pins. Because the PRELOAD portion of the command is not implemented in this device, moving the controller to the Update-DR state with the SAMPLE/PRELOAD instruction loaded in the instruction register has the same effect as the Pause-DR command. BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP controller is in the Shift-DR state, the bypass register is placed between TDI and TDO. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. Document #: 38-05265 Rev. *A Page 11 of 28 CY7C1357A CY7C1355A 1[21] TEST-LOGIC RESET 0 1 SELECT IR-SCAN 0 1 CAPTURE-DR 0 SHIFT-DR 1 EXIT1-DR 0 PAUSE-DR 1 0 EXIT2-DR 1 UPDATE-DR 1 0 0 EXIT2-IR 1 UPDATE-IR 1 0 0 1 0 CAPTURE-IR 0 SHIFT-IR 1 EXIT1-IR 0 PAUSE-IR 1 0 1 0 0 REUN-TEST/ IDLE 1 SELECT DR-SCAN 0 1 1 Figure 1. TAP Controller State Diagram Note: 21. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document #: 38-05265 Rev. *A Page 12 of 28 CY7C1357A CY7C1355A ZZ 0 Bypass Register Selection Circuitry TDI Selection Circuitry TDO 2 Instruction Register 1 0 31 30 29 . . 2 1 0 Identification Register [22] x . . . . 2 1 0 Boundary Scan Register [22] TDI TAP Controller TDI Figure 2. TAP Controller Block Diagram TAP Electrical Characteristics Over the Operating Range Parameter VIH VIl ILI ILI ILO VOLC VOHC VOLT VOHT Description Input High (Logic 1) Voltage[23, 24] Input Low (Logic 0) Voltage[23, 24] 0V < VIN < VCC 0V < VIN < VCC Output disabled, 0V < VIN < VCCQ IOLC = 100 µA IOHC = 100 µA IOLT = 8.0 mA VCC – 0.2 0.4 Input Leakage Current TMS and TDI Input Leakage Current Output Leakage Current LVCMOS Output Low Voltage[23, 25] LVCMOS Output High Voltage[23, 25] LVTTL Output Low Voltage[23] Voltage[23] Test Conditions Min. 2.0 –0.3 –5.0 –30 –5.0 Max. VCC + 0.3 0.8 5.0 30 5.0 0.2 Unit V V µA µA µA V V V LVTTL Output High IOHT = 8.0 mA 2.4 V Notes: 22.X = 69 for the x36 configuration; X = 50 for the x18 configuration. 23. All Voltage referenced to VSS (GND). 24. Overshoot: VIH(AC) VDDQ – 0.3V f = f MAX = 1/t CYC Automatic CS Device deselected; all inputs < VIL Power-down Current— TTL or > VIH; all inputs static; VCC = max.; CLK frequency = 0 Inputs[31, 32, 33] 40 15 190 30 180 30 170 30 mA mA Notes: 28. Overshoot: VIH < +6.0V for t < tKC /2 Undershoot:VIL < -2.0V for t < tKC /2. 29. MODE pin has an internal pull-up and ZZ pin has an internal pull-down. These two pins exhibit an input leakage current of ±50 µA. 30. ICC is given with no output current. ICC increases with greater output loading and faster cycle times. 31. “Device Deselected” means the device is in Power-Down mode as defined in the truth table. “Device Selected” means the device is active. 32. Typical values are measured at 3.3V, 25°C, and 20 ns cycle time. 33. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC; f = 0 means no input lines are changing. Document #: 38-05265 Rev. *A Page 18 of 28 CY7C1357A CY7C1355A Capacitance[25] Parameter CI CI/O Description Input Capacitance Input/Output Capacitance DQ Test Conditions TA[34] = 25°C, VCC = 3.3V f = 1 MHz, Typ. 4 7 Max. 4 6.5 Unit pF pF Thermal Resistance Parameter ΘJA ΘJC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) R = 317Ω ALL INPUT PULSES VCCQ 10% 5 pF INCLUDING JIG AND SCOPE R = 351Ω GND ≤ 1 V/ns 90% 90% 10% ≤ 1 V/ns Test Conditions Still Air, soldered on a 4.25 ×1.125 inch, four-layer PCB TQFP Typ. 25 9 Unit °C/W °C/W AC Test Loads and Waveforms OUTPUT Z0 =50Ω RL = 50Ω VTH = 1.5V VCCQ OUTPUT (a) (b) 133-MHz 117 MHz Min. 8.5 3.0 3.0 6.5 2.0 3.0 2 0 3.5 1.5 1.5 0.5 0.5 1.5 1.5 0.5 0.5 3.5 3.5 0 3.5 2.0 3.0 2 3.5 3.5 7.0 Max. (c) 100 MHz Min. 10 3.5 3.5 7.5 2.0 3.0 2 0 3.5 1.8 1.8 0.5 0.5 3.5 4.0 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns Switching Characteristics Over the Operating Range[35] Parameter Clock tKC tKH tKL Output Times tKQ tKQX tKQLZ tKQHZ tOEQ tOELZ tOEHZ Set-up Times tS tSD Hold Times tH tHD Address and Controls[38] Data In[38] Address and Controls[38] Data In [38] Description Clock Cycle Time Clock HIGH Time Clock LOW Time Clock to Output Valid Clock to Output Invalid Clock to Output in Low-Z[25, 36, 37] Clock to Output in OE to Output in High-Z[25, 36, 37] OE to Output Valid Low-Z[25, 36, 37] OE to Output in High-Z[25, 36, 37] Min. 7.5 2.5 2.5 Max. Notes: 34. TA is the case temperature. 35. Test conditions as specified with the output loading as shown in part (a) of AC Test Loads unless otherwise noted. 36. Output loading is specified with CL = 5 pF as in part (a) of AC Test Loads. 37. At any given temperature and voltage condition, tKQHZ is less than tKQLZ and tOEHZ is less than tOELZ. 38. This is a synchronous device. All synchronous inputs must meet specified setup and hold time, except for “don’t care” as defined in the truth table. Document #: 38-05265 Rev. *A Page 19 of 28 CY7C1357A CY7C1355A Switching Waveforms Read Timing[39, 40, 41, 42, 43] tKC tKH tKL CLK CLK tS tH CKE CEN tS tH WEN tS tH R/W A ADDRESS BWa, BWb BW BWc, BWdx A1 A2 tS tH CE CE tS tH ADV/LD ADV/LD OE OE tKQLZ tKQ Q(A2 ) tKQX Q(A2 +1 ) Q(A2 +2 ) (CKE# HIGH, eliminates current L-H clock edge) Q(A2+3 ) (Burst Wraps around to initial state) Q(A2 ) tKQHZ DQ DQx Q(A1) Read Read BURST READ Deselec t Notes: 39. Q(A1) represents the first output from the external address A1. Q(A2) represents the first output from the external address A2; Q(A2+1) represents the next output data in the burst sequence of the base address A2, etc. where address bits SA0 and SA1 are advancing for the four word burst in the sequence defined by the state of the MODE input. 40. CE2 timing transitions are identical to the CE signal. For example, when CE is LOW on this waveform, CE2 is LOW. CE2 timing transitions are identical but inverted to the CE signal. For example, when CE is LOW on this waveform, CE2 is HIGH. 41. Burst ends when new address and control are loaded into the SRAM by sampling ADV/LD LOW. 42. WEN is “Don’t Care” when the SRAM is bursting (ADV/LD sampled HIGH). The nature of the burst access (Read or Write) is fixed by the state of the WEN signal when new address and control are loaded into the SRAM. 43. BWc and BWd apply to 256K × 36 device only. Document #: 38-05265 Rev. *A Page 20 of 28 CY7C1357A CY7C1355A Switching Waveforms (continued) Write Timing[40, 41, 42, 43, 44, 45] tKC tKH tKL CLK CLK tS tH CKE CEN tS tH R/W WEN tS tH ADDRESS A BWa, BWb BW BWc, BWd x CE CE A1 tS BW(A1) A2 tH BW(A2 ) BW(A2+1) BW(A2 +2) BW(A2+3) BW(A2) tS tH tS tH ADV/LD ADV/LD OE OE tSD tHD D(A1 ) D(A2) D(A2+1) D(A2+2) (CKE# HIGH, eliminates current L-H clock edge) (Burst Wraps around to initial state) D(A2+3) D(A2) DQ DQx Write Write Burst Write Deselect Notes: 44. D(A1) represents the first input to the external address A1. D(A2) represents the first input to the external address A2; D(A2+1) represents the next input data in the burst sequence of the base address A2, etc. where address bits SA0 and SA1 are advancing for the four word burst in the sequence defined by the state of the MODE input. 45. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when WEN signal is sampled LOW when ADV/LD is sampled LOW. The byte write information comes in one cycle before the actual data is presented to the SRAM. Document #: 38-05265 Rev. *A Page 21 of 28 CY7C1357A CY7C1355A Switching Waveforms (continued) Read/Write Timing[40, 43, 45, 46] tKC tKL tKH CLK tS tH CKE# tS tH R/W# tS tH ADDRESS BWa#, BWb# BWc#, BWd# A1 tS A2 tH BW(A) 2 A3 A4 BW(A) 4 A5 BW(A) 5 A6 A7 A8 A9 tS tH CE# tS tH ADV/LD# OE# tKQ tKQHZ Q(A ) 1 Read tKQLZ Q(A ) 3 Read D(A) 2 Write D(A) 4 Write D(A) 5 Write tKQX Q(A ) 6 Read D(A) 8 Q(A ) 7 DATA Out (Q) DATA In (D) Note: 46. Q(A1) represents the first output from the external address A1. D(A2) represents the input data to the SRAM corresponding to address A2. Document #: 38-05265 Rev. *A Page 22 of 28 CY7C1357A CY7C1355A Switching Waveforms (continued) CEN Timing[40, 43, 45, 46, 47] tKC tKL tKH CLK CLK tS tH CEN CKE# tS tH R/W# WEN tS tH ADDRESS A BWa#, BW BWb# x BWc#, BWd# A1 tS A2 tH A3 A4 A5 tS tH CE# CE tS tH ADV/LD# ADV/LD OE# OE tKQ tKQHZ DATA Out (Q) tKQLZ Q(A ) 1 tKQX tSD tHD Q(A ) 3 Q(A ) 4 DATA In (D) D(A) 2 Note: 47. CEN when sampled HIGH on the rising edge of clock will block that L-H transition of the clock from propagating into the SRAM. The part will behave as if the L-H clock transition did not occur. All internal register in the SRAM will retain their previous state. Document #: 38-05265 Rev. *A Page 23 of 28 CY7C1357A CY7C1355A Switching Waveforms (continued) CE Timing[40, 43, 45, 48, 49] tKC tKL tKH CLK CLK tS tH CEN CKE# tS tH R/W# WEN tS tH ADDRESS A BWa#, BWb# BWx BWc#, BWd# A1 A2 tS A3 tH A4 A5 tS tH CE# CE tS tH ADV/LD# ADV/LD tOEQ OE# OE tOELZ tKQHZ tOEHZ DATA Out (Q) Q(A ) 1 tKQLZ tKQ Q(A ) 2 tKQX tSD tHD Q(A ) 4 DATA In (D) D(A) 3 Notes: 48. Q(A1) represents the first output from the external address A1. D(A3) represents the input data to the SRAM corresponding to address A3, etc. 49. When either one of the Chip enables (CE, CE2 or CE2) is sampled inactive at the rising clock edge, a chip deselect cycle is initiated. The data-bus High-Z one cycle after the initiation of the deselect cycle. This allows for any pending data transfers (reads or writes) to be completed. Document #: 38-05265 Rev. *A Page 24 of 28 CY7C1357A CY7C1355A Switching Waveforms (continued) ZZ Mode Timing [ 50, 51] CLK CE1 CE2 LOW HIGH CE3 ZZ tZZS IDD IDD(active) IDDZZ tZZREC I/Os Three-state Note: 50. Device must be deselected when entering ZZ mode. See Cycle Descriptions Table for all possible signal conditions to deselect the device. 51. I/Os are in three-state when exiting ZZ sleep mode. Ordering Information Speed (MHz) 133 117 Ordering Code CY7C1355A-133AC CY7C1357A-133AC CY7C1355A-117AC CY7C1355A-117AI CY7C1355A-117BGC CY7C1355A-117BGI 100 CY7C1355A-100AC CY7C1357A-100AC CY7C1357A-100AI CY7C1355A-100BGC Package Name A101 A101 A101 BG119 BG119 A101 A101 BG119 Package Type 100-lead 14 × 20 × 1.4 mm Thin Quad Flat Pack 100-lead 14 × 20 × 1.4 mm Thin Quad Flat Pack 100-lead 14 × 20 × 1.4 mm Thin Quad Flat Pack 119-lead BGA (14 × 22 × 2.4 mm) 119-lead BGA (14 × 22 × 2.4 mm) 100-lead 14 × 20 × 1.4 mm Thin Quad Flat Pack 100-lead 14 × 20 × 1.4 mm Thin Quad Flat Pack 119-lead BGA (14 × 22 × 2.4 mm) Operating Range Commercial Commercial Industrial Commercial Industrial Commercial Industrial Commercial Document #: 38-05265 Rev. *A Page 25 of 28 CY7C1357A CY7C1355A Package Diagrams 100-pin Thin Plastic Quad Flatpack (14 × 20 × 1.4 mm) A101 51-85050-A Document #: 38-05265 Rev. *A Page 26 of 28 CY7C1357A CY7C1355A Package Diagrams (continued) 119-lead BGA (14 × 22 × 2.4) BG119 51-85115-*A No Bus Latency and NoBL are trademarks of Cypress Semiconductor Corporation. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05265 Rev. *A Page 27 of 28 © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY7C1357A CY7C1355A Document Title: CY7C1355A/CY7C1357A 256K x 36/512K x 18 Synchronous Flow-Thru SRAM with NoBL™ Architecture Document Number: 38-05265 REV ** *A ECN 114118 117837 Issue Date 7/16/02 08/26/02 Orig. of Change KKV HGK New Data Sheet Removed BGA package from 1357A Removed JTAG from 1357A Removed 1357A1 and 1355A1 part numbers Description of Change Document #: 38-05265 Rev. *A Page 28 of 28